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-rw-r--r--dts/src/arm/qcom-ipq8064.dtsi35
1 files changed, 17 insertions, 18 deletions
diff --git a/dts/src/arm/qcom-ipq8064.dtsi b/dts/src/arm/qcom-ipq8064.dtsi
index 7e784b0995..52d77e1059 100644
--- a/dts/src/arm/qcom-ipq8064.dtsi
+++ b/dts/src/arm/qcom-ipq8064.dtsi
@@ -326,26 +326,26 @@
};
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <7>;
+ snps,rd_osr_lmt = <7>;
+ snps,blen = <16 0 0 0 0 0 0>;
+ };
+
+ vsdcc_fixed: vsdcc-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "SDCC Power";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
- stmmac_axi_setup: stmmac-axi-config {
- snps,wr_osr_lmt = <7>;
- snps,rd_osr_lmt = <7>;
- snps,blen = <16 0 0 0 0 0 0>;
- };
-
- vsdcc_fixed: vsdcc-regulator {
- compatible = "regulator-fixed";
- regulator-name = "SDCC Power";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
rpm: rpm@108000 {
compatible = "qcom,rpm-ipq8064";
reg = <0x00108000 0x1000>;
@@ -549,8 +549,8 @@
};
timer@200a000 {
- compatible = "qcom,kpss-timer",
- "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
+ compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer",
+ "qcom,msm-timer";
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
@@ -562,8 +562,7 @@
<GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_EDGE_RISING)>;
reg = <0x0200a000 0x100>;
- clock-frequency = <25000000>,
- <32768>;
+ clock-frequency = <25000000>;
clocks = <&sleep_clk>;
clock-names = "sleep";
cpu-offset = <0x80000>;