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-rw-r--r--dts/src/arm64/apple/t8103.dtsi369
1 files changed, 356 insertions, 13 deletions
diff --git a/dts/src/arm64/apple/t8103.dtsi b/dts/src/arm64/apple/t8103.dtsi
index 9f8f4145db..9b0dad6b61 100644
--- a/dts/src/arm64/apple/t8103.dtsi
+++ b/dts/src/arm64/apple/t8103.dtsi
@@ -22,69 +22,279 @@
#address-cells = <2>;
#size-cells = <0>;
- cpu0: cpu@0 {
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu_e0>;
+ };
+ core1 {
+ cpu = <&cpu_e1>;
+ };
+ core2 {
+ cpu = <&cpu_e2>;
+ };
+ core3 {
+ cpu = <&cpu_e3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu_p0>;
+ };
+ core1 {
+ cpu = <&cpu_p1>;
+ };
+ core2 {
+ cpu = <&cpu_p2>;
+ };
+ core3 {
+ cpu = <&cpu_p3>;
+ };
+ };
+ };
+
+ cpu_e0: cpu@0 {
compatible = "apple,icestorm";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&ecluster_opp>;
+ capacity-dmips-mhz = <714>;
+ performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
- cpu1: cpu@1 {
+ cpu_e1: cpu@1 {
compatible = "apple,icestorm";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&ecluster_opp>;
+ capacity-dmips-mhz = <714>;
+ performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
- cpu2: cpu@2 {
+ cpu_e2: cpu@2 {
compatible = "apple,icestorm";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&ecluster_opp>;
+ capacity-dmips-mhz = <714>;
+ performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
- cpu3: cpu@3 {
+ cpu_e3: cpu@3 {
compatible = "apple,icestorm";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&ecluster_opp>;
+ capacity-dmips-mhz = <714>;
+ performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
- cpu4: cpu@10100 {
+ cpu_p0: cpu@10100 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10100>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&pcluster_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
};
- cpu5: cpu@10101 {
+ cpu_p1: cpu@10101 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10101>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&pcluster_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
};
- cpu6: cpu@10102 {
+ cpu_p2: cpu@10102 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10102>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&pcluster_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
};
- cpu7: cpu@10103 {
+ cpu_p3: cpu@10103 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10103>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&pcluster_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ };
+
+ l2_cache_0: l2-cache-0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x400000>;
+ };
+
+ l2_cache_1: l2-cache-1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0xc00000>;
+ };
+ };
+
+ ecluster_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-level = <1>;
+ clock-latency-ns = <7500>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <972000000>;
+ opp-level = <2>;
+ clock-latency-ns = <22000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1332000000>;
+ opp-level = <3>;
+ clock-latency-ns = <27000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1704000000>;
+ opp-level = <4>;
+ clock-latency-ns = <33000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <2064000000>;
+ opp-level = <5>;
+ clock-latency-ns = <50000>;
+ };
+ };
+
+ pcluster_opp: opp-table-1 {
+ compatible = "operating-points-v2";
+
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-level = <1>;
+ clock-latency-ns = <8000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <828000000>;
+ opp-level = <2>;
+ clock-latency-ns = <19000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-level = <3>;
+ clock-latency-ns = <21000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1284000000>;
+ opp-level = <4>;
+ clock-latency-ns = <23000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-level = <5>;
+ clock-latency-ns = <24000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1728000000>;
+ opp-level = <6>;
+ clock-latency-ns = <29000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1956000000>;
+ opp-level = <7>;
+ clock-latency-ns = <31000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <2184000000>;
+ opp-level = <8>;
+ clock-latency-ns = <34000>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <2388000000>;
+ opp-level = <9>;
+ clock-latency-ns = <36000>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <2592000000>;
+ opp-level = <10>;
+ clock-latency-ns = <51000>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <2772000000>;
+ opp-level = <11>;
+ clock-latency-ns = <54000>;
};
+ opp12 {
+ opp-hz = /bits/ 64 <2988000000>;
+ opp-level = <12>;
+ clock-latency-ns = <55000>;
+ };
+#if 0
+ /* Not available until CPU deep sleep is implemented */
+ opp13 {
+ opp-hz = /bits/ 64 <3096000000>;
+ opp-level = <13>;
+ clock-latency-ns = <55000>;
+ turbo-mode;
+ };
+ opp14 {
+ opp-hz = /bits/ 64 <3144000000>;
+ opp-level = <14>;
+ clock-latency-ns = <56000>;
+ turbo-mode;
+ };
+ opp15 {
+ opp-hz = /bits/ 64 <3204000000>;
+ opp-level = <15>;
+ clock-latency-ns = <56000>;
+ turbo-mode;
+ };
+#endif
};
timer {
@@ -116,6 +326,16 @@
clock-output-names = "clkref";
};
+ /*
+ * This is a fabulated representation of the input clock
+ * to NCO since we don't know the true clock tree.
+ */
+ nco_clkref: clock-ref-nco {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "nco_ref";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -124,6 +344,27 @@
ranges;
nonposted-mmio;
+ cpufreq_e: performance-controller@210e20000 {
+ compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
+ reg = <0x2 0x10e20000 0 0x1000>;
+ #performance-domain-cells = <0>;
+ };
+
+ cpufreq_p: performance-controller@211e20000 {
+ compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
+ reg = <0x2 0x11e20000 0 0x1000>;
+ #performance-domain-cells = <0>;
+ };
+
+ sio_dart: iommu@235004000 {
+ compatible = "apple,t8103-dart";
+ reg = <0x2 0x35004000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_sio_cpu>;
+ };
+
i2c0: i2c@235010000 {
compatible = "apple,t8103-i2c", "apple,i2c";
reg = <0x2 0x35010000 0x0 0x4000>;
@@ -191,6 +432,15 @@
status = "disabled"; /* only used in J293 */
};
+ fpwm1: pwm@235044000 {
+ compatible = "apple,t8103-fpwm", "apple,s5l-fpwm";
+ reg = <0x2 0x35044000 0x0 0x4000>;
+ power-domains = <&ps_fpwm1>;
+ clocks = <&clkref>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
serial0: serial@235200000 {
compatible = "apple,s5l-uart";
reg = <0x2 0x35200000 0x0 0x1000>;
@@ -219,6 +469,61 @@
status = "disabled";
};
+ admac: dma-controller@238200000 {
+ compatible = "apple,t8103-admac", "apple,admac";
+ reg = <0x2 0x38200000 0x0 0x34000>;
+ dma-channels = <24>;
+ interrupts-extended = <0>,
+ <&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>,
+ <0>,
+ <0>;
+ #dma-cells = <1>;
+ iommus = <&sio_dart 2>;
+ power-domains = <&ps_sio_adma>;
+ resets = <&ps_audio_p>;
+ };
+
+ mca: i2s@238400000 {
+ compatible = "apple,t8103-mca", "apple,mca";
+ reg = <0x2 0x38400000 0x0 0x18000>,
+ <0x2 0x38300000 0x0 0x30000>;
+
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 619 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 620 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 621 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 622 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 623 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 624 IRQ_TYPE_LEVEL_HIGH>;
+
+ resets = <&ps_audio_p>;
+ clocks = <&nco 0>, <&nco 1>, <&nco 2>,
+ <&nco 3>, <&nco 4>, <&nco 4>;
+ power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
+ <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>;
+ dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>,
+ <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>,
+ <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>,
+ <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>,
+ <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>,
+ <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>;
+ dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
+ "tx1a", "rx1a", "tx1b", "rx1b",
+ "tx2a", "rx2a", "tx2b", "rx2b",
+ "tx3a", "rx3a", "tx3b", "rx3b",
+ "tx4a", "rx4a", "tx4b", "rx4b",
+ "tx5a", "rx5a", "tx5b", "rx5b";
+
+ #sound-dai-cells = <1>;
+ };
+
+ nco: clock-controller@23b044000 {
+ compatible = "apple,t8103-nco", "apple,nco";
+ reg = <0x2 0x3b044000 0x0 0x14000>;
+ clocks = <&nco_clkref>;
+ #clock-cells = <1>;
+ };
+
aic: interrupt-controller@23b100000 {
compatible = "apple,t8103-aic", "apple,aic";
#interrupt-cells = <3>;
@@ -229,12 +534,12 @@
affinities {
e-core-pmu-affinity {
apple,fiq-index = <AIC_CPU_PMU_E>;
- cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>;
};
p-core-pmu-affinity {
apple,fiq-index = <AIC_CPU_PMU_P>;
- cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>;
};
};
};
@@ -378,7 +683,41 @@
<AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>;
};
- pcie0_dart_0: dart@681008000 {
+ ans_mbox: mbox@277408000 {
+ compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
+ reg = <0x2 0x77408000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "send-empty", "send-not-empty",
+ "recv-empty", "recv-not-empty";
+ #mbox-cells = <0>;
+ power-domains = <&ps_ans2>;
+ };
+
+ sart: iommu@27bc50000 {
+ compatible = "apple,t8103-sart";
+ reg = <0x2 0x7bc50000 0x0 0x10000>;
+ power-domains = <&ps_ans2>;
+ };
+
+ nvme@27bcc0000 {
+ compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2";
+ reg = <0x2 0x7bcc0000 0x0 0x40000>,
+ <0x2 0x77400000 0x0 0x4000>;
+ reg-names = "nvme", "ans";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>;
+ mboxes = <&ans_mbox>;
+ apple,sart = <&sart>;
+ power-domains = <&ps_ans2>, <&ps_apcie_st>;
+ power-domain-names = "ans", "apcie0";
+ resets = <&ps_ans2>;
+ };
+
+ pcie0_dart_0: iommu@681008000 {
compatible = "apple,t8103-dart";
reg = <0x6 0x81008000 0x0 0x4000>;
#iommu-cells = <1>;
@@ -387,22 +726,24 @@
power-domains = <&ps_apcie_gp>;
};
- pcie0_dart_1: dart@682008000 {
+ pcie0_dart_1: iommu@682008000 {
compatible = "apple,t8103-dart";
reg = <0x6 0x82008000 0x0 0x4000>;
#iommu-cells = <1>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&ps_apcie_gp>;
+ status = "disabled";
};
- pcie0_dart_2: dart@683008000 {
+ pcie0_dart_2: iommu@683008000 {
compatible = "apple,t8103-dart";
reg = <0x6 0x83008000 0x0 0x4000>;
#iommu-cells = <1>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&ps_apcie_gp>;
+ status = "disabled";
};
pcie0: pcie@690000000 {
@@ -477,6 +818,7 @@
<0 0 0 2 &port01 0 0 0 1>,
<0 0 0 3 &port01 0 0 0 2>,
<0 0 0 4 &port01 0 0 0 3>;
+ status = "disabled";
};
port02: pci@2,0 {
@@ -496,6 +838,7 @@
<0 0 0 2 &port02 0 0 0 1>,
<0 0 0 3 &port02 0 0 0 2>,
<0 0 0 4 &port02 0 0 0 3>;
+ status = "disabled";
};
};
};
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-26 01:25:17 +0000