diff options
Diffstat (limited to 'dts/src/arm64/arm')
21 files changed, 989 insertions, 598 deletions
diff --git a/dts/src/arm64/arm/corstone1000-fvp.dts b/dts/src/arm64/arm/corstone1000-fvp.dts new file mode 100644 index 0000000000..901a7fc833 --- /dev/null +++ b/dts/src/arm64/arm/corstone1000-fvp.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; + compatible = "arm,corstone1000-fvp"; + + smsc: ethernet@4010000 { + compatible = "smsc,lan91c111"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <2>; + }; + + vmmc_v3_3d: fixed_v3_3d { + compatible = "regulator-fixed"; + regulator-name = "vmmc_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sdmmc0: mmc@40300000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x40300000 0x1000>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; + + sdmmc1: mmc@50000000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x50000000 0x10000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; +}; diff --git a/dts/src/arm64/arm/corstone1000-mps3.dts b/dts/src/arm64/arm/corstone1000-mps3.dts new file mode 100644 index 0000000000..10d265be0c --- /dev/null +++ b/dts/src/arm64/arm/corstone1000-mps3.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "ARM Corstone1000 FPGA MPS3 board"; + compatible = "arm,corstone1000-mps3"; + + smsc: ethernet@4010000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <2>; + smsc,irq-push-pull; + }; + + usb_host: usb@40200000 { + compatible = "nxp,usb-isp1763"; + reg = <0x40200000 0x100000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + bus-width = <16>; + dr_mode = "host"; + }; +}; diff --git a/dts/src/arm64/arm/corstone1000.dtsi b/dts/src/arm64/arm/corstone1000.dtsi new file mode 100644 index 0000000000..6ad7829f9e --- /dev/null +++ b/dts/src/arm64/arm/corstone1000.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0>; + next-level-cache = <&L2_0>; + }; + }; + + memory@88200000 { + device_type = "memory"; + reg = <0x88200000 0x77e00000>; + }; + + gic: interrupt-controller@1c000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1c010000 0x1000>, + <0x1c02f000 0x2000>, + <0x1c04f000 0x1000>, + <0x1c06f000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; + }; + + refclk100mhz: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + smbclk: refclk24mhzx2 { + /* Reference 24MHz clock x 2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "smclk"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; + + uartclk: uartclk { + /* UART clock - 50MHz */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "uartclk"; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + timer@1a220000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x1a220000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + clock-frequency = <50000000>; + ranges; + + frame@1a230000 { + frame-number = <0>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x1a230000 0x1000>; + }; + }; + + uart0: serial@1a510000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a510000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: serial@1a520000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a520000 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + mhu_hse1: mailbox@1b820000 { + compatible = "arm,mhuv2-tx", "arm,primecell"; + reg = <0x1b820000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + arm,mhuv2-protocols = <0 0>; + secure-status = "okay"; /* secure-world-only */ + status = "disabled"; + }; + + mhu_seh1: mailbox@1b830000 { + compatible = "arm,mhuv2-rx", "arm,primecell"; + reg = <0x1b830000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + arm,mhuv2-protocols = <0 0>; + secure-status = "okay"; /* secure-world-only */ + status = "disabled"; + }; + }; +}; diff --git a/dts/src/arm64/arm/foundation-v8-gicv3.dtsi b/dts/src/arm64/arm/foundation-v8-gicv3.dtsi index e4a3c7dbcc..17fba3bc99 100644 --- a/dts/src/arm64/arm/foundation-v8-gicv3.dtsi +++ b/dts/src/arm64/arm/foundation-v8-gicv3.dtsi @@ -12,11 +12,11 @@ #size-cells = <1>; ranges = <0x0 0x0 0x2f000000 0x100000>; interrupt-controller; - reg = <0x0 0x2f000000 0x0 0x10000>, - <0x0 0x2f100000 0x0 0x200000>, - <0x0 0x2c000000 0x0 0x2000>, - <0x0 0x2c010000 0x0 0x2000>, - <0x0 0x2c02f000 0x0 0x2000>; + reg = <0x0 0x2f000000 0x0 0x10000>, + <0x0 0x2f100000 0x0 0x200000>, + <0x0 0x2c000000 0x0 0x2000>, + <0x0 0x2c010000 0x0 0x2000>, + <0x0 0x2c02f000 0x0 0x2000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; its: msi-controller@2f020000 { diff --git a/dts/src/arm64/arm/foundation-v8.dtsi b/dts/src/arm64/arm/foundation-v8.dtsi index 05ae893d1b..7b41537731 100644 --- a/dts/src/arm64/arm/foundation-v8.dtsi +++ b/dts/src/arm64/arm/foundation-v8.dtsi @@ -58,6 +58,8 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; @@ -84,6 +86,11 @@ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; }; + spe-pmu { + compatible = "arm,statistical-profiling-extension-v1"; + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; + }; + watchdog@2a440000 { compatible = "arm,sbsa-gwdt"; reg = <0x0 0x2a440000 0 0x1000>, @@ -115,7 +122,6 @@ bus@8000000 { compatible = "arm,vexpress,v2m-p1", "simple-bus"; - arm,v2m-memory-map = "rs1"; #address-cells = <2>; /* SMB chipselect number and offset */ #size-cells = <1>; @@ -221,7 +227,7 @@ clock-names = "uartclk", "apb_pclk"; }; - virtio-block@130000 { + virtio@130000 { compatible = "virtio,mmio"; reg = <0x130000 0x200>; interrupts = <42>; diff --git a/dts/src/arm64/arm/fvp-base-revc.dts b/dts/src/arm64/arm/fvp-base-revc.dts index b8a21092db..60472d65a3 100644 --- a/dts/src/arm64/arm/fvp-base-revc.dts +++ b/dts/src/arm64/arm/fvp-base-revc.dts @@ -47,48 +47,121 @@ compatible = "arm,armv8"; reg = <0x0 0x000>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C0_L2>; }; cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C0_L2>; }; cpu2: cpu@200 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x200>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C0_L2>; }; cpu3: cpu@300 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x300>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C0_L2>; }; cpu4: cpu@10000 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x10000>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C1_L2>; }; cpu5: cpu@10100 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x10100>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C1_L2>; }; cpu6: cpu@10200 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x10200>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C1_L2>; }; cpu7: cpu@10300 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x10300>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C1_L2>; + }; + C0_L2: l2-cache0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + }; + + C1_L2: l2-cache1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; }; }; @@ -186,38 +259,15 @@ }; panel { - compatible = "arm,rtsm-display", "panel-dpi"; + compatible = "arm,rtsm-display"; port { panel_in: endpoint { remote-endpoint = <&clcd_pads>; }; }; - - panel-timing { - clock-frequency = <63500127>; - hactive = <1024>; - hback-porch = <152>; - hfront-porch = <48>; - hsync-len = <104>; - vactive = <768>; - vback-porch = <23>; - vfront-porch = <3>; - vsync-len = <4>; - }; }; bus@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -264,6 +314,7 @@ <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <0 0 46 &gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/dts/src/arm64/arm/juno-base.dtsi b/dts/src/arm64/arm/juno-base.dtsi index 8e7a66943b..b897f5542c 100644 --- a/dts/src/arm64/arm/juno-base.dtsi +++ b/dts/src/arm64/arm/juno-base.dtsi @@ -26,9 +26,8 @@ compatible = "arm,mhu", "arm,primecell"; reg = <0x0 0x2b1f0000 0x0 0x1000>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mhu_lpri_rx", - "mhu_hpri_rx"; + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <1>; clocks = <&soc_refclk100mhz>; clock-names = "apb_pclk"; @@ -119,7 +118,7 @@ * The actual size is just 4K though 64K is reserved. Access to the * unmapped reserved region results in a DECERR response. */ - etf@20010000 { /* etf0 */ + etf_sys0: etf@20010000 { /* etf0 */ compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20010000 0 0x1000>; @@ -143,7 +142,7 @@ }; }; - tpiu@20030000 { + tpiu_sys: tpiu@20030000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0 0x20030000 0 0x1000>; @@ -196,7 +195,7 @@ }; }; - etr@20070000 { + etr_sys: etr@20070000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20070000 0 0x1000>; iommus = <&smmu_etr 0>; @@ -214,7 +213,7 @@ }; }; - stm@20100000 { + stm_sys: stm@20100000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x20100000 0 0x1000>, <0 0x28000000 0 0x1000000>; @@ -291,6 +290,18 @@ }; }; + cti0: cti@22020000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x22020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm0>; + }; + funnel@220c0000 { /* cluster0 funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x220c0000 0 0x1000>; @@ -351,6 +362,18 @@ }; }; + cti1: cti@22120000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x22120000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm1>; + }; + cpu_debug2: cpu-debug@23010000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23010000 0x0 0x1000>; @@ -376,6 +399,18 @@ }; }; + cti2: cti@23020000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm2>; + }; + funnel@230c0000 { /* cluster1 funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x230c0000 0 0x1000>; @@ -448,6 +483,18 @@ }; }; + cti3: cti@23120000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23120000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm3>; + }; + cpu_debug4: cpu-debug@23210000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23210000 0x0 0x1000>; @@ -473,6 +520,18 @@ }; }; + cti4: cti@23220000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23220000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm4>; + }; + cpu_debug5: cpu-debug@23310000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23310000 0x0 0x1000>; @@ -498,6 +557,100 @@ }; }; + cti5: cti@23320000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23320000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm5>; + }; + + cti_sys0: cti@20020000 { /* sys_cti_0 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs = <2 3>; + arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>; + arm,trig-out-sigs = <0 1>; + arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>; + arm,cs-dev-assoc = <&etr_sys>; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-in-sigs = <0 1>; + arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>; + arm,trig-out-sigs = <7 6>; + arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>; + arm,cs-dev-assoc = <&etf_sys0>; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs = <4 5 6 7>; + arm,trig-in-types = <STM_TOUT_SPTE STM_TOUT_SW + STM_TOUT_HETE STM_ASYNCOUT>; + arm,trig-out-sigs = <4 5>; + arm,trig-out-types = <STM_HWEVENT STM_HWEVENT>; + arm,cs-dev-assoc = <&stm_sys>; + }; + + trig-conns@3 { + reg = <3>; + arm,trig-out-sigs = <2 3>; + arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>; + arm,cs-dev-assoc = <&tpiu_sys>; + }; + }; + + cti_sys1: cti@20110000 { /* sys_cti_1 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20110000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs = <0>; + arm,trig-in-types = <GEN_INTREQ>; + arm,trig-out-sigs = <0>; + arm,trig-out-types = <GEN_HALTREQ>; + arm,trig-conn-name = "sys_profiler"; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-out-sigs = <2 3>; + arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>; + arm,trig-conn-name = "watchdog"; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-out-sigs = <1 6>; + arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>; + arm,trig-conn-name = "g_counter"; + }; + }; + gpu: gpu@2d000000 { compatible = "arm,juno-mali", "arm,mali-t624"; reg = <0 0x2d000000 0 0x10000>; @@ -545,8 +698,7 @@ <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; /* Standard AXI Translation entries as programmed by EDK2 */ - dma-ranges = <0x02000000 0x0 0x2c1c0000 0x0 0x2c1c0000 0x0 0x00040000>, - <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>, + dma-ranges = <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>, <0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; @@ -595,40 +747,54 @@ }; thermal-zones { - pmic { + pmic-thermal { polling-delay = <1000>; polling-delay-passive = <100>; thermal-sensors = <&scpi_sensors0 0>; + trips { + pmic_crit0: trip0 { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - soc { + soc-thermal { polling-delay = <1000>; polling-delay-passive = <100>; thermal-sensors = <&scpi_sensors0 3>; + trips { + soc_crit0: trip0 { + temperature = <80000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - big_cluster_thermal_zone: big-cluster { + big_cluster_thermal_zone: big-cluster-thermal { polling-delay = <1000>; polling-delay-passive = <100>; thermal-sensors = <&scpi_sensors0 21>; status = "disabled"; }; - little_cluster_thermal_zone: little-cluster { + little_cluster_thermal_zone: little-cluster-thermal { polling-delay = <1000>; polling-delay-passive = <100>; thermal-sensors = <&scpi_sensors0 22>; status = "disabled"; }; - gpu0_thermal_zone: gpu0 { + gpu0_thermal_zone: gpu0-thermal { polling-delay = <1000>; polling-delay-passive = <100>; thermal-sensors = <&scpi_sensors0 23>; status = "disabled"; }; - gpu1_thermal_zone: gpu1 { + gpu1_thermal_zone: gpu1-thermal { polling-delay = <1000>; polling-delay-passive = <100>; thermal-sensors = <&scpi_sensors0 24>; @@ -674,12 +840,10 @@ dma-coherent; }; - dma@7ff00000 { + dma-controller@7ff00000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0x7ff00000 0 0x1000>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, @@ -804,16 +968,6 @@ }; bus@8000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - #interrupt-cells = <1>; interrupt-map-mask = <0 0 15>; interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/src/arm64/arm/juno-cs-r1r2.dtsi b/dts/src/arm64/arm/juno-cs-r1r2.dtsi index eda3d9e18a..09d2b692e9 100644 --- a/dts/src/arm64/arm/juno-cs-r1r2.dtsi +++ b/dts/src/arm64/arm/juno-cs-r1r2.dtsi @@ -23,7 +23,7 @@ }; }; - etf@20140000 { /* etf1 */ + etf_sys1: etf@20140000 { /* etf1 */ compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20140000 0 0x1000>; @@ -67,7 +67,6 @@ port@0 { reg = <0>; csys2_funnel_in_port0: endpoint { - slave-mode; remote-endpoint = <&etf0_out_port>; }; }; @@ -75,11 +74,45 @@ port@1 { reg = <1>; csys2_funnel_in_port1: endpoint { - slave-mode; remote-endpoint = <&etf1_out_port>; }; }; }; }; + + cti_sys2: cti@20160000 { /* sys_cti_2 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20160000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs = <0 1>; + arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>; + arm,trig-out-sigs = <0 1>; + arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>; + arm,cs-dev-assoc = <&etf_sys1>; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-in-sigs = <2 3 4>; + arm,trig-in-types = <ELA_DBGREQ ELA_TSTART ELA_TSTOP>; + arm,trig-conn-name = "ela_clus_0"; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs = <5 6 7>; + arm,trig-in-types = <ELA_DBGREQ ELA_TSTART ELA_TSTOP>; + arm,trig-conn-name = "ela_clus_1"; + }; + }; }; diff --git a/dts/src/arm64/arm/juno-motherboard.dtsi b/dts/src/arm64/arm/juno-motherboard.dtsi index 40d95c58b5..be42932f7e 100644 --- a/dts/src/arm64/arm/juno-motherboard.dtsi +++ b/dts/src/arm64/arm/juno-motherboard.dtsi @@ -92,16 +92,23 @@ }; bus@8000000 { - motherboard-bus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x8000000 0 0x8000000 0x18000000>; + + motherboard-bus@8000000 { compatible = "arm,vexpress,v2p-p1", "simple-bus"; #address-cells = <2>; /* SMB chipselect number and offset */ #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - model = "V2M-Juno"; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; arm,hbi = <0x252>; arm,vexpress,site = <0>; - arm,v2m-memory-map = "rs1"; flash@0 { /* 2 * 32MiB NOR Flash memory mounted on CS0 */ @@ -153,64 +160,75 @@ apbregs@10000 { compatible = "syscon", "simple-mfd"; reg = <0x010000 0x1000>; + ranges = <0x0 0x10000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; - led0 { + led@8,0 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x01>; label = "vexpress:0"; linux,default-trigger = "heartbeat"; default-state = "on"; }; - led1 { + led@8,1 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x02>; label = "vexpress:1"; linux,default-trigger = "mmc0"; default-state = "off"; }; - led2 { + led@8,2 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x04>; label = "vexpress:2"; linux,default-trigger = "cpu0"; default-state = "off"; }; - led3 { + led@8,3 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x08>; label = "vexpress:3"; linux,default-trigger = "cpu1"; default-state = "off"; }; - led4 { + led@8,4 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x10>; label = "vexpress:4"; linux,default-trigger = "cpu2"; default-state = "off"; }; - led5 { + led@8,5 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x20>; label = "vexpress:5"; linux,default-trigger = "cpu3"; default-state = "off"; }; - led6 { + led@8,6 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x40>; label = "vexpress:6"; default-state = "off"; }; - led7 { + led@8,7 { compatible = "register-bit-led"; + reg = <0x08 0x04>; offset = <0x08>; mask = <0x80>; label = "vexpress:7"; @@ -218,7 +236,7 @@ }; }; - mmci@50000 { + mmc@50000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x050000 0x1000>; interrupts = <5>; @@ -246,7 +264,7 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; - wdt@f0000 { + watchdog@f0000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0f0000 0x10000>; interrupts = <7>; diff --git a/dts/src/arm64/arm/juno-r1-scmi.dts b/dts/src/arm64/arm/juno-r1-scmi.dts new file mode 100644 index 0000000000..dd9ea69f08 --- /dev/null +++ b/dts/src/arm64/arm/juno-r1-scmi.dts @@ -0,0 +1,27 @@ +#include "juno-r1.dts" +#include "juno-scmi.dtsi" + +/ { + funnel@20130000 { + power-domains = <&scmi_devpd 8>; + }; + + etf@20140000 { + power-domains = <&scmi_devpd 8>; + }; + + funnel@20150000 { + power-domains = <&scmi_devpd 8>; + }; +}; + +&cti_sys2 { + power-domains = <&scmi_devpd 8>; +}; + +&A57_0 { + clocks = <&scmi_dvfs 0>; +}; +&A57_1 { + clocks = <&scmi_dvfs 0>; +}; diff --git a/dts/src/arm64/arm/juno-r1.dts b/dts/src/arm64/arm/juno-r1.dts index 0e24e29eb9..1d90eeebb3 100644 --- a/dts/src/arm64/arm/juno-r1.dts +++ b/dts/src/arm64/arm/juno-r1.dts @@ -9,6 +9,7 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/arm/coresight-cti-dt.h> #include "juno-base.dtsi" #include "juno-cs-r1r2.dtsi" @@ -188,16 +189,20 @@ A57_L2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; }; A53_L2: l2-cache1 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; + cache-level = <2>; }; }; @@ -313,3 +318,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A57_0>; +}; + +&cti1 { + cpu = <&A57_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; diff --git a/dts/src/arm64/arm/juno-r2-scmi.dts b/dts/src/arm64/arm/juno-r2-scmi.dts new file mode 100644 index 0000000000..de2cbac1d1 --- /dev/null +++ b/dts/src/arm64/arm/juno-r2-scmi.dts @@ -0,0 +1,27 @@ +#include "juno-r2.dts" +#include "juno-scmi.dtsi" + +/ { + funnel@20130000 { + power-domains = <&scmi_devpd 8>; + }; + + etf@20140000 { + power-domains = <&scmi_devpd 8>; + }; + + funnel@20150000 { + power-domains = <&scmi_devpd 8>; + }; +}; + +&cti_sys2 { + power-domains = <&scmi_devpd 8>; +}; + +&A72_0 { + clocks = <&scmi_dvfs 0>; +}; +&A72_1 { + clocks = <&scmi_dvfs 0>; +}; diff --git a/dts/src/arm64/arm/juno-r2.dts b/dts/src/arm64/arm/juno-r2.dts index e609420ce3..d2ada69b0a 100644 --- a/dts/src/arm64/arm/juno-r2.dts +++ b/dts/src/arm64/arm/juno-r2.dts @@ -9,6 +9,7 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/arm/coresight-cti-dt.h> #include "juno-base.dtsi" #include "juno-cs-r1r2.dtsi" @@ -194,16 +195,20 @@ A72_L2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; }; A53_L2: l2-cache1 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; + cache-level = <2>; }; }; @@ -319,3 +324,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A72_0>; +}; + +&cti1 { + cpu = <&A72_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; diff --git a/dts/src/arm64/arm/juno-scmi.dts b/dts/src/arm64/arm/juno-scmi.dts new file mode 100644 index 0000000000..41588fa46d --- /dev/null +++ b/dts/src/arm64/arm/juno-scmi.dts @@ -0,0 +1,9 @@ +#include "juno.dts" +#include "juno-scmi.dtsi" + +&A57_0 { + clocks = <&scmi_dvfs 0>; +}; +&A57_1 { + clocks = <&scmi_dvfs 0>; +}; diff --git a/dts/src/arm64/arm/juno-scmi.dtsi b/dts/src/arm64/arm/juno-scmi.dtsi new file mode 100644 index 0000000000..31929e2377 --- /dev/null +++ b/dts/src/arm64/arm/juno-scmi.dtsi @@ -0,0 +1,223 @@ +/ { + etf@20010000 { + power-domains = <&scmi_devpd 8>; + }; + + tpiu@20030000 { + power-domains = <&scmi_devpd 8>; + }; + + funnel@20040000 { + power-domains = <&scmi_devpd 8>; + }; + + etr@20070000 { + power-domains = <&scmi_devpd 8>; + }; + + stm@20100000 { + power-domains = <&scmi_devpd 8>; + }; + + replicator@20120000 { + power-domains = <&scmi_devpd 8>; + }; + + funnel@220c0000 { + power-domains = <&scmi_devpd 8>; + }; + + funnel@230c0000 { + power-domains = <&scmi_devpd 8>; + }; + + hdlcd@7ff50000 { + clocks = <&scmi_clk 3>; + }; + + hdlcd@7ff60000 { + clocks = <&scmi_clk 3>; + }; + + /delete-node/ scpi; + + firmware { + scmi { + compatible = "arm,scmi"; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 0 0 &mailbox 0 1>; + shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 1 0 &mailbox 1 1>; + shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_sensors0: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + }; + }; + + thermal-zones { + pmic-thermal { + thermal-sensors = <&scmi_sensors0 0>; + }; + + soc-thermal { + thermal-sensors = <&scmi_sensors0 3>; + }; + + big-cluster-thermal { + thermal-sensors = <&scmi_sensors0 21>; + }; + + little-cluster-thermal { + thermal-sensors = <&scmi_sensors0 22>; + }; + + gpu0-thermal { + thermal-sensors = <&scmi_sensors0 23>; + }; + + gpu1-thermal { + thermal-sensors = <&scmi_sensors0 24>; + }; + }; + +}; + +&A53_0 { + clocks = <&scmi_dvfs 1>; +}; +&A53_1 { + clocks = <&scmi_dvfs 1>; +}; +&A53_2 { + clocks = <&scmi_dvfs 1>; +}; +&A53_3 { + clocks = <&scmi_dvfs 1>; +}; + +&cpu_debug0 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug1 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug2 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug3 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug4 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug5 { + power-domains = <&scmi_devpd 8>; +}; + +&etm0 { + power-domains = <&scmi_devpd 8>; +}; +&etm1 { + power-domains = <&scmi_devpd 8>; +}; +&etm2 { + power-domains = <&scmi_devpd 8>; +}; +&etm3 { + power-domains = <&scmi_devpd 8>; +}; +&etm4 { + power-domains = <&scmi_devpd 8>; +}; +&etm5 { + power-domains = <&scmi_devpd 8>; +}; + +&cti0 { + power-domains = <&scmi_devpd 8>; +}; +&cti1 { + power-domains = <&scmi_devpd 8>; +}; +&cti2 { + power-domains = <&scmi_devpd 8>; +}; +&cti3 { + power-domains = <&scmi_devpd 8>; +}; +&cti4 { + power-domains = <&scmi_devpd 8>; +}; +&cti5 { + power-domains = <&scmi_devpd 8>; +}; +&cti_sys0 { + power-domains = <&scmi_devpd 8>; +}; +&cti_sys1 { + power-domains = <&scmi_devpd 8>; +}; + +&gpu { + clocks = <&scmi_dvfs 2>; + power-domains = <&scmi_devpd 9>; +}; + +&mailbox { + compatible = "arm,mhu-doorbell", "arm,primecell"; + #mbox-cells = <2>; +}; + +&smmu_etr { + power-domains = <&scmi_devpd 8>; +}; + +&smmu_gpu { + power-domains = <&scmi_devpd 9>; +}; + +&sram { + /delete-node/ scp-sram@0; + /delete-node/ scp-sram@200; + + cpu_scp_lpri0: scp-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + cpu_scp_lpri1: scp-sram@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + + cpu_scp_hpri0: scp-sram@100 { + compatible = "arm,scmi-shmem"; + reg = <0x100 0x80>; + }; + + cpu_scp_hpri1: scp-sram@180 { + compatible = "arm,scmi-shmem"; + reg = <0x180 0x80>; + }; +}; diff --git a/dts/src/arm64/arm/juno.dts b/dts/src/arm64/arm/juno.dts index f00cffbd03..5e48a01a5b 100644 --- a/dts/src/arm64/arm/juno.dts +++ b/dts/src/arm64/arm/juno.dts @@ -9,6 +9,7 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/arm/coresight-cti-dt.h> #include "juno-base.dtsi" / { @@ -193,16 +194,20 @@ A57_L2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; }; A53_L2: l2-cache1 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; + cache-level = <2>; }; }; @@ -295,3 +300,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A57_0>; +}; + +&cti1 { + cpu = <&A57_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; diff --git a/dts/src/arm64/arm/rtsm_ve-aemv8a.dts b/dts/src/arm64/arm/rtsm_ve-aemv8a.dts index 3050f45bad..afdf954206 100644 --- a/dts/src/arm64/arm/rtsm_ve-aemv8a.dts +++ b/dts/src/arm64/arm/rtsm_ve-aemv8a.dts @@ -71,6 +71,8 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; @@ -133,17 +135,6 @@ }; bus@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/src/arm64/arm/rtsm_ve-motherboard-rs2.dtsi b/dts/src/arm64/arm/rtsm_ve-motherboard-rs2.dtsi index b917d9d3f1..ec2d5280a3 100644 --- a/dts/src/arm64/arm/rtsm_ve-motherboard-rs2.dtsi +++ b/dts/src/arm64/arm/rtsm_ve-motherboard-rs2.dtsi @@ -6,21 +6,28 @@ */ / { bus@8000000 { - motherboard-bus { + motherboard-bus@8000000 { arm,v2m-memory-map = "rs2"; iofpga-bus@300000000 { - virtio-p9@140000 { + virtio@140000 { compatible = "virtio,mmio"; reg = <0x140000 0x200>; interrupts = <43>; }; - virtio-net@150000 { + virtio@150000 { compatible = "virtio,mmio"; reg = <0x150000 0x200>; interrupts = <44>; }; + + virtio@200000 { + compatible = "virtio,mmio"; + reg = <0x200000 0x200>; + interrupts = <46>; + status = "disabled"; + }; }; }; }; diff --git a/dts/src/arm64/arm/rtsm_ve-motherboard.dtsi b/dts/src/arm64/arm/rtsm_ve-motherboard.dtsi index 4c4a381d2c..ba8beef3fe 100644 --- a/dts/src/arm64/arm/rtsm_ve-motherboard.dtsi +++ b/dts/src/arm64/arm/rtsm_ve-motherboard.dtsi @@ -77,13 +77,21 @@ }; bus@8000000 { - motherboard-bus { - arm,v2m-memory-map = "rs1"; + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x8000000 0 0x8000000 0x18000000>; + + motherboard-bus@8000000 { compatible = "arm,vexpress,v2m-p1", "simple-bus"; #address-cells = <2>; /* SMB chipselect number and offset */ #size-cells = <1>; - #interrupt-cells = <1>; - ranges; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; flash@0 { compatible = "arm,vexpress-flash", "cfi-flash"; @@ -102,7 +110,7 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 3 0 0x200000>; + ranges = <0 3 0 0x210000>; v2m_sysreg: sysreg@10000 { compatible = "arm,vexpress-sysreg"; @@ -130,7 +138,7 @@ clock-names = "apb_pclk"; }; - mmci@50000 { + mmc@50000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x050000 0x1000>; interrupts = <9>, <10>; @@ -190,7 +198,7 @@ clock-names = "uartclk", "apb_pclk"; }; - wdt@f0000 { + watchdog@f0000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0f0000 0x1000>; interrupts = <0>; @@ -214,7 +222,7 @@ clock-names = "timclken1", "timclken2", "apb_pclk"; }; - virtio-block@130000 { + virtio@130000 { compatible = "virtio,mmio"; reg = <0x130000 0x200>; interrupts = <42>; diff --git a/dts/src/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts b/dts/src/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts index d859914500..8db4243a49 100644 --- a/dts/src/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts +++ b/dts/src/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts @@ -13,7 +13,7 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> -#include "vexpress-v2m-rs1.dtsi" +#include "arm/arm/vexpress-v2m-rs1.dtsi" / { model = "V2F-1XV7 Cortex-A53x2 SMM"; @@ -57,6 +57,8 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; @@ -145,61 +147,6 @@ }; smb: bus@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + ranges = <0x8000000 0 0x8000000 0x18000000>; }; }; diff --git a/dts/src/arm64/arm/vexpress-v2m-rs1.dtsi b/dts/src/arm64/arm/vexpress-v2m-rs1.dtsi deleted file mode 100644 index 2ad9fd7c94..0000000000 --- a/dts/src/arm64/arm/vexpress-v2m-rs1.dtsi +++ /dev/null @@ -1,441 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * RS1 memory map ("ARM Cortex-A Series memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * original variant (vexpress-v2m.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m.dtsi! - */ - -/ { - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - led-1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - led-2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "disk-activity"; - }; - - led-3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - led-4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - led-5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - - led-6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - led-7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - led-8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - bus@8000000 { - motherboard-bus { - model = "V2M-P1"; - arm,hbi = <0x190>; - arm,vexpress,site = <0>; - arm,v2m-memory-map = "rs1"; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - - nor_flash: flash@0 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - psram@100000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <1 0x00000000 0x02000000>; - bank-width = <4>; - }; - - ethernet@202000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&v2m_fixed_3v3>; - vddvario-supply = <&v2m_fixed_3v3>; - }; - - usb@203000000 { - compatible = "nxp,usb-isp1761"; - reg = <2 0x03000000 0x20000>; - interrupts = <16>; - dr_mode = "peripheral"; - }; - - iofpga-bus@300000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysreg: sysreg@10000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10000 0x1000>; - - v2m_led_gpios: gpio@8 { - compatible = "arm,vexpress-sysreg,sys_led"; - reg = <0x008 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_mmc_gpios: gpio@48 { - compatible = "arm,vexpress-sysreg,sys_mci"; - reg = <0x048 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_flash_gpios: gpio@4c { - compatible = "arm,vexpress-sysreg,sys_flash"; - reg = <0x04c 4>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@30000 { - compatible = "arm,versatile-i2c"; - reg = <0x030000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@40000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <11>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - mmci@50000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <9>, <10>; - cd-gpios = <&v2m_mmc_gpios 0 0>; - wp-gpios = <&v2m_mmc_gpios 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@60000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@70000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: serial@90000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: serial@a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: serial@b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: serial@c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@160000 { - compatible = "arm,versatile-i2c"; - reg = <0x160000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dvi_bridge_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - }; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <4>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - compact-flash@1a0000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a0000 0x100 - 0x1a0100 0xf00>; - reg-shift = <2>; - }; - - clcd@1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&smbclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 800x600 16bpp @36MHz works fine */ - max-memory-bandwidth = <54000000>; - memory-region = <&vram>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&dvi_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - }; - }; - }; -}; |