diff options
Diffstat (limited to 'dts/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi')
-rw-r--r-- | dts/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/dts/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi b/dts/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi index 27afa46a25..1e7badb2a8 100644 --- a/dts/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi +++ b/dts/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi @@ -5,9 +5,11 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> / { aliases { + ethernet1 = ð1; usb0 = &usbotg1; usb1 = &usbotg2; }; @@ -33,6 +35,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + pps { compatible = "pps-gpio"; pinctrl-names = "default"; @@ -80,6 +88,22 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "rs485_term", "mipi_gpio4", "", "", + "", "", "pci_usb_sel", "dio0", + "", "dio1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", + "mipi_gpio1", "", "", "pci_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -106,6 +130,54 @@ status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + pcie@1,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + pcie@2,3 { + reg = <0x1800 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + eth1: pcie@5,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + }; +}; + /* off-board header */ &sai3 { pinctrl-names = "default"; @@ -198,6 +270,12 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 + >; + }; + pinctrl_pps: ppsgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 |