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-rw-r--r--dts/src/arm64/hisilicon/hi3660-hikey960.dts26
-rw-r--r--dts/src/arm64/hisilicon/hi3660.dtsi12
-rw-r--r--dts/src/arm64/hisilicon/hi3670.dtsi2
-rw-r--r--dts/src/arm64/hisilicon/hi3798cv200.dtsi4
-rw-r--r--dts/src/arm64/hisilicon/hi6220-hikey.dts24
-rw-r--r--dts/src/arm64/hisilicon/hi6220.dtsi34
-rw-r--r--dts/src/arm64/hisilicon/hikey-pinctrl.dtsi134
-rw-r--r--dts/src/arm64/hisilicon/hikey960-pinctrl.dtsi124
-rw-r--r--dts/src/arm64/hisilicon/hikey970-pinctrl.dtsi118
-rw-r--r--dts/src/arm64/hisilicon/hikey970-pmic.dtsi6
-rw-r--r--dts/src/arm64/hisilicon/hip05-d02.dts6
-rw-r--r--dts/src/arm64/hisilicon/hip05.dtsi8
-rw-r--r--dts/src/arm64/hisilicon/hip06.dtsi22
-rw-r--r--dts/src/arm64/hisilicon/hip07.dtsi48
14 files changed, 309 insertions, 259 deletions
diff --git a/dts/src/arm64/hisilicon/hi3660-hikey960.dts b/dts/src/arm64/hisilicon/hi3660-hikey960.dts
index f68580dc87..3f13a960f3 100644
--- a/dts/src/arm64/hisilicon/hi3660-hikey960.dts
+++ b/dts/src/arm64/hisilicon/hi3660-hikey960.dts
@@ -49,9 +49,9 @@
ramoops@32000000 {
compatible = "ramoops";
reg = <0x0 0x32000000 0x0 0x00100000>;
- record-size = <0x00020000>;
- console-size = <0x00020000>;
- ftrace-size = <0x00020000>;
+ record-size = <0x00020000>;
+ console-size = <0x00020000>;
+ ftrace-size = <0x00020000>;
};
};
@@ -63,9 +63,9 @@
compatible = "syscon-reboot-mode";
offset = <0x0>;
- mode-normal = <0x77665501>;
- mode-bootloader = <0x77665500>;
- mode-recovery = <0x77665502>;
+ mode-normal = <0x77665501>;
+ mode-bootloader = <0x77665500>;
+ mode-recovery = <0x77665502>;
};
};
@@ -74,7 +74,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>;
- power {
+ key-power {
wakeup-source;
gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
@@ -85,28 +85,28 @@
leds {
compatible = "gpio-leds";
- user_led1 {
+ led-user-1 {
label = "green:user1";
/* gpio_150_user_led1 */
gpios = <&gpio18 6 0>;
linux,default-trigger = "heartbeat";
};
- user_led2 {
+ led-user-2 {
label = "green:user2";
/* gpio_151_user_led2 */
gpios = <&gpio18 7 0>;
linux,default-trigger = "none";
};
- user_led3 {
+ led-user-3 {
label = "green:user3";
/* gpio_189_user_led3 */
gpios = <&gpio23 5 0>;
linux,default-trigger = "mmc0";
};
- user_led4 {
+ led-user-4 {
label = "green:user4";
/* gpio_190_user_led4 */
gpios = <&gpio23 6 0>;
@@ -114,7 +114,7 @@
linux,default-trigger = "none";
};
- wlan_active_led {
+ led-wlan {
label = "yellow:wlan";
/* gpio_205_wifi_active */
gpios = <&gpio25 5 0>;
@@ -122,7 +122,7 @@
default-state = "off";
};
- bt_active_led {
+ led-bt {
label = "blue:bt";
gpios = <&gpio25 7 0>;
/* gpio_207_user_led1 */
diff --git a/dts/src/arm64/hisilicon/hi3660.dtsi b/dts/src/arm64/hisilicon/hi3660.dtsi
index 6b3057a092..7e137a884a 100644
--- a/dts/src/arm64/hisilicon/hi3660.dtsi
+++ b/dts/src/arm64/hisilicon/hi3660.dtsi
@@ -203,10 +203,14 @@
A53_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
A73_L2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
};
@@ -479,7 +483,7 @@
reg = <0x0 0xfdf00000 0x0 0x1000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
dma-names = "rx", "tx";
- dmas = <&dma0 2 &dma0 3>;
+ dmas = <&dma0 2 &dma0 3>;
clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
<&crg_ctrl HI3660_CLK_GATE_UART1>;
clock-names = "uartclk", "apb_pclk";
@@ -493,7 +497,7 @@
reg = <0x0 0xfdf03000 0x0 0x1000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
dma-names = "rx", "tx";
- dmas = <&dma0 4 &dma0 5>;
+ dmas = <&dma0 4 &dma0 5>;
clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
<&crg_ctrl HI3660_PCLK>;
clock-names = "uartclk", "apb_pclk";
@@ -519,7 +523,7 @@
reg = <0x0 0xfdf01000 0x0 0x1000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
dma-names = "rx", "tx";
- dmas = <&dma0 6 &dma0 7>;
+ dmas = <&dma0 6 &dma0 7>;
clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
<&crg_ctrl HI3660_CLK_GATE_UART4>;
clock-names = "uartclk", "apb_pclk";
@@ -533,7 +537,7 @@
reg = <0x0 0xfdf05000 0x0 0x1000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
dma-names = "rx", "tx";
- dmas = <&dma0 8 &dma0 9>;
+ dmas = <&dma0 8 &dma0 9>;
clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
<&crg_ctrl HI3660_CLK_GATE_UART5>;
clock-names = "uartclk", "apb_pclk";
diff --git a/dts/src/arm64/hisilicon/hi3670.dtsi b/dts/src/arm64/hisilicon/hi3670.dtsi
index 3125c3869c..886b93c589 100644
--- a/dts/src/arm64/hisilicon/hi3670.dtsi
+++ b/dts/src/arm64/hisilicon/hi3670.dtsi
@@ -324,7 +324,7 @@
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>;
+ gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO3>;
diff --git a/dts/src/arm64/hisilicon/hi3798cv200.dtsi b/dts/src/arm64/hisilicon/hi3798cv200.dtsi
index a83b9d4f17..ed1b5a7a60 100644
--- a/dts/src/arm64/hisilicon/hi3798cv200.dtsi
+++ b/dts/src/arm64/hisilicon/hi3798cv200.dtsi
@@ -302,8 +302,8 @@
compatible = "snps,dw-mshc";
reg = <0x9820000 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&crg HISTB_SDIO0_CIU_CLK>,
- <&crg HISTB_SDIO0_BIU_CLK>;
+ clocks = <&crg HISTB_SDIO0_BIU_CLK>,
+ <&crg HISTB_SDIO0_CIU_CLK>;
clock-names = "biu", "ciu";
resets = <&crg 0x9c 4>;
reset-names = "reset";
diff --git a/dts/src/arm64/hisilicon/hi6220-hikey.dts b/dts/src/arm64/hisilicon/hi6220-hikey.dts
index 3df2afb2f6..f0672ec65b 100644
--- a/dts/src/arm64/hisilicon/hi6220-hikey.dts
+++ b/dts/src/arm64/hisilicon/hi6220-hikey.dts
@@ -54,9 +54,9 @@
ramoops@21f00000 {
compatible = "ramoops";
reg = <0x0 0x21f00000 0x0 0x00100000>;
- record-size = <0x00020000>;
- console-size = <0x00020000>;
- ftrace-size = <0x00020000>;
+ record-size = <0x00020000>;
+ console-size = <0x00020000>;
+ ftrace-size = <0x00020000>;
};
/* global autoconfigured region for contiguous allocations */
@@ -76,9 +76,9 @@
compatible = "syscon-reboot-mode";
offset = <0x0>;
- mode-normal = <0x77665501>;
- mode-bootloader = <0x77665500>;
- mode-recovery = <0x77665502>;
+ mode-normal = <0x77665501>;
+ mode-bootloader = <0x77665500>;
+ mode-recovery = <0x77665502>;
};
};
@@ -125,39 +125,39 @@
leds {
compatible = "gpio-leds";
- user_led1 {
+ led-user-1 {
label = "green:user1";
gpios = <&gpio4 0 0>; /* <&gpio_user_led_1>; */
linux,default-trigger = "heartbeat";
};
- user_led2 {
+ led-user-2 {
label = "green:user2";
gpios = <&gpio4 1 0>; /* <&gpio_user_led_2>; */
linux,default-trigger = "mmc0";
};
- user_led3 {
+ led-user-3 {
label = "green:user3";
gpios = <&gpio4 2 0>; /* <&gpio_user_led_3>; */
linux,default-trigger = "mmc1";
};
- user_led4 {
+ led-user-4 {
label = "green:user4";
gpios = <&gpio4 3 0>; /* <&gpio_user_led_4>; */
panic-indicator;
linux,default-trigger = "none";
};
- wlan_active_led {
+ led-wlan {
label = "yellow:wlan";
gpios = <&gpio3 5 0>; /* <&gpio_wlan_active_led>; */
linux,default-trigger = "phy0tx";
default-state = "off";
};
- bt_active_led {
+ led-bt {
label = "blue:bt";
gpios = <&gpio4 7 0>; /* <&gpio_bt_active_led>; */
linux,default-trigger = "hci0-power";
diff --git a/dts/src/arm64/hisilicon/hi6220.dtsi b/dts/src/arm64/hisilicon/hi6220.dtsi
index ae0a7cfeeb..be808bb254 100644
--- a/dts/src/arm64/hisilicon/hi6220.dtsi
+++ b/dts/src/arm64/hisilicon/hi6220.dtsi
@@ -186,10 +186,14 @@
CLUSTER0_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
CLUSTER1_L2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
};
@@ -405,7 +409,7 @@
compatible = "pinctrl-single";
reg = <0x0 0xf7010000 0x0 0x27c>;
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
#pinctrl-cells = <1>;
#gpio-range-cells = <3>;
pinctrl-single,register-width = <32>;
@@ -444,7 +448,7 @@
compatible = "pinconf-single";
reg = <0x0 0xf7010800 0x0 0x28c>;
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
};
@@ -453,7 +457,7 @@
compatible = "pinconf-single";
reg = <0x0 0xf8001800 0x0 0x78>;
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
};
@@ -857,7 +861,7 @@
#thermal-sensor-cells = <1>;
};
- i2s0: i2s@f7118000{
+ i2s0: i2s@f7118000 {
compatible = "hisilicon,hi6210-i2s";
reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
@@ -1028,17 +1032,17 @@
compatible = "hisilicon,hi6220-mali", "arm,mali-450";
reg = <0x0 0xf4080000 0x0 0x00040000>;
interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",
diff --git a/dts/src/arm64/hisilicon/hikey-pinctrl.dtsi b/dts/src/arm64/hisilicon/hikey-pinctrl.dtsi
index e7d22619a4..3e27624c31 100644
--- a/dts/src/arm64/hisilicon/hikey-pinctrl.dtsi
+++ b/dts/src/arm64/hisilicon/hikey-pinctrl.dtsi
@@ -17,13 +17,13 @@
&bl_pwm_pmx_func
>;
- boot_sel_pmx_func: boot_sel_pmx_func {
+ boot_sel_pmx_func: boot-sel-pins {
pinctrl-single,pins = <
0x0 MUX_M0 /* BOOT_SEL (IOMG000) */
>;
};
- emmc_pmx_func: emmc_pmx_func {
+ emmc_pmx_func: emmc-pins {
pinctrl-single,pins = <
0x100 MUX_M0 /* EMMC_CLK (IOMG064) */
0x104 MUX_M0 /* EMMC_CMD (IOMG065) */
@@ -38,7 +38,7 @@
>;
};
- sd_pmx_func: sd_pmx_func {
+ sd_pmx_func: sd-pins {
pinctrl-single,pins = <
0xc MUX_M0 /* SD_CLK (IOMG003) */
0x10 MUX_M0 /* SD_CMD (IOMG004) */
@@ -48,7 +48,7 @@
0x20 MUX_M0 /* SD_DATA3 (IOMG008) */
>;
};
- sd_pmx_idle: sd_pmx_idle {
+ sd_pmx_idle: sd-idle-pins {
pinctrl-single,pins = <
0xc MUX_M1 /* SD_CLK (IOMG003) */
0x10 MUX_M1 /* SD_CMD (IOMG004) */
@@ -59,7 +59,7 @@
>;
};
- sdio_pmx_func: sdio_pmx_func {
+ sdio_pmx_func: sdio-pins {
pinctrl-single,pins = <
0x128 MUX_M0 /* SDIO_CLK (IOMG074) */
0x12c MUX_M0 /* SDIO_CMD (IOMG075) */
@@ -69,7 +69,7 @@
0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */
>;
};
- sdio_pmx_idle: sdio_pmx_idle {
+ sdio_pmx_idle: sdio-idle-pins {
pinctrl-single,pins = <
0x128 MUX_M1 /* SDIO_CLK (IOMG074) */
0x12c MUX_M1 /* SDIO_CMD (IOMG075) */
@@ -80,7 +80,7 @@
>;
};
- isp_pmx_func: isp_pmx_func {
+ isp_pmx_func: isp-pins {
pinctrl-single,pins = <
0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */
0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */
@@ -101,19 +101,19 @@
>;
};
- hkadc_ssi_pmx_func: hkadc_ssi_pmx_func {
+ hkadc_ssi_pmx_func: hkadc-ssi-pins {
pinctrl-single,pins = <
0x68 MUX_M0 /* HKADC_SSI (IOMG026) */
>;
};
- codec_clk_pmx_func: codec_clk_pmx_func {
+ codec_clk_pmx_func: codec-clk-pins {
pinctrl-single,pins = <
0x6c MUX_M0 /* CODEC_CLK (IOMG027) */
>;
};
- codec_pmx_func: codec_pmx_func {
+ codec_pmx_func: codec-pins {
pinctrl-single,pins = <
0x70 MUX_M1 /* DMIC_CLK (IOMG028) */
0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */
@@ -122,7 +122,7 @@
>;
};
- fm_pmx_func: fm_pmx_func {
+ fm_pmx_func: fm-pins {
pinctrl-single,pins = <
0x80 MUX_M1 /* FM_XCLK (IOMG032) */
0x84 MUX_M1 /* FM_XFS (IOMG033) */
@@ -131,7 +131,7 @@
>;
};
- bt_pmx_func: bt_pmx_func {
+ bt_pmx_func: bt-pins {
pinctrl-single,pins = <
0x90 MUX_M0 /* BT_XCLK (IOMG036) */
0x94 MUX_M0 /* BT_XFS (IOMG037) */
@@ -140,26 +140,26 @@
>;
};
- pwm_in_pmx_func: pwm_in_pmx_func {
+ pwm_in_pmx_func: pwm-in-pins {
pinctrl-single,pins = <
0xb8 MUX_M1 /* PWM_IN (IOMG046) */
>;
};
- bl_pwm_pmx_func: bl_pwm_pmx_func {
+ bl_pwm_pmx_func: bl-pwm-pins {
pinctrl-single,pins = <
0xbc MUX_M1 /* BL_PWM (IOMG047) */
>;
};
- uart0_pmx_func: uart0_pmx_func {
+ uart0_pmx_func: uart0-pins {
pinctrl-single,pins = <
0xc0 MUX_M0 /* UART0_RXD (IOMG048) */
0xc4 MUX_M0 /* UART0_TXD (IOMG049) */
>;
};
- uart1_pmx_func: uart1_pmx_func {
+ uart1_pmx_func: uart1-pins {
pinctrl-single,pins = <
0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */
0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */
@@ -168,7 +168,7 @@
>;
};
- uart2_pmx_func: uart2_pmx_func {
+ uart2_pmx_func: uart2-pins {
pinctrl-single,pins = <
0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */
0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */
@@ -177,7 +177,7 @@
>;
};
- uart3_pmx_func: uart3_pmx_func {
+ uart3_pmx_func: uart3-pins {
pinctrl-single,pins = <
0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */
0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */
@@ -186,7 +186,7 @@
>;
};
- uart4_pmx_func: uart4_pmx_func {
+ uart4_pmx_func: uart4-pins {
pinctrl-single,pins = <
0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */
0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */
@@ -195,35 +195,35 @@
>;
};
- uart5_pmx_func: uart5_pmx_func {
+ uart5_pmx_func: uart5-pins {
pinctrl-single,pins = <
0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */
0x1cc MUX_M1 /* UART5_TXD (IOMG115) */
>;
};
- i2c0_pmx_func: i2c0_pmx_func {
+ i2c0_pmx_func: i2c0-pins {
pinctrl-single,pins = <
0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */
0xec MUX_M0 /* I2C0_SDA (IOMG059) */
>;
};
- i2c1_pmx_func: i2c1_pmx_func {
+ i2c1_pmx_func: i2c1-pins {
pinctrl-single,pins = <
0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */
0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */
>;
};
- i2c2_pmx_func: i2c2_pmx_func {
+ i2c2_pmx_func: i2c2-pins {
pinctrl-single,pins = <
0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */
0xfc MUX_M0 /* I2C2_SDA (IOMG063) */
>;
};
- spi0_pmx_func: spi0_pmx_func {
+ spi0_pmx_func: spi0-pins {
pinctrl-single,pins = <
0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */
0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */
@@ -244,7 +244,7 @@
&bl_pwm_cfg_func
>;
- boot_sel_cfg_func: boot_sel_cfg_func {
+ boot_sel_cfg_func: boot-sel-cfg-pins {
pinctrl-single,pins = <
0x0 0x0 /* BOOT_SEL (IOCFG000) */
>;
@@ -253,7 +253,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- hkadc_ssi_cfg_func: hkadc_ssi_cfg_func {
+ hkadc_ssi_cfg_func: hkadc-ssi-cfg-pins {
pinctrl-single,pins = <
0x6c 0x0 /* HKADC_SSI (IOCFG027) */
>;
@@ -262,7 +262,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- emmc_clk_cfg_func: emmc_clk_cfg_func {
+ emmc_clk_cfg_func: emmc-clk-cfg-pins {
pinctrl-single,pins = <
0x104 0x0 /* EMMC_CLK (IOCFG065) */
>;
@@ -271,7 +271,7 @@
pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
};
- emmc_cfg_func: emmc_cfg_func {
+ emmc_cfg_func: emmc-cfg-pins {
pinctrl-single,pins = <
0x108 0x0 /* EMMC_CMD (IOCFG066) */
0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */
@@ -288,7 +288,7 @@
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
};
- emmc_rst_cfg_func: emmc_rst_cfg_func {
+ emmc_rst_cfg_func: emmc-rst-cfg-pins {
pinctrl-single,pins = <
0x12c 0x0 /* EMMC_RST_N (IOCFG075) */
>;
@@ -297,7 +297,7 @@
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
};
- sd_clk_cfg_func: sd_clk_cfg_func {
+ sd_clk_cfg_func: sd-clk-cfg-pins {
pinctrl-single,pins = <
0xc 0x0 /* SD_CLK (IOCFG003) */
>;
@@ -305,7 +305,7 @@
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_10MA DRIVE_MASK>;
};
- sd_clk_cfg_idle: sd_clk_cfg_idle {
+ sd_clk_cfg_idle: sd-clk-cfg-idle-pins {
pinctrl-single,pins = <
0xc 0x0 /* SD_CLK (IOCFG003) */
>;
@@ -314,7 +314,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- sd_cfg_func: sd_cfg_func {
+ sd_cfg_func: sd-cfg-pins {
pinctrl-single,pins = <
0x10 0x0 /* SD_CMD (IOCFG004) */
0x14 0x0 /* SD_DATA0 (IOCFG005) */
@@ -326,7 +326,7 @@
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
};
- sd_cfg_idle: sd_cfg_idle {
+ sd_cfg_idle: sd-cfg-idle-pins {
pinctrl-single,pins = <
0x10 0x0 /* SD_CMD (IOCFG004) */
0x14 0x0 /* SD_DATA0 (IOCFG005) */
@@ -339,7 +339,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- sdio_clk_cfg_func: sdio_clk_cfg_func {
+ sdio_clk_cfg_func: sdio-clk-cfg-pins {
pinctrl-single,pins = <
0x134 0x0 /* SDIO_CLK (IOCFG077) */
>;
@@ -347,7 +347,7 @@
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
};
- sdio_clk_cfg_idle: sdio_clk_cfg_idle {
+ sdio_clk_cfg_idle: sdio-clk-cfg-idle-pins {
pinctrl-single,pins = <
0x134 0x0 /* SDIO_CLK (IOCFG077) */
>;
@@ -356,7 +356,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- sdio_cfg_func: sdio_cfg_func {
+ sdio_cfg_func: sdio-cfg-pins {
pinctrl-single,pins = <
0x138 0x0 /* SDIO_CMD (IOCFG078) */
0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
@@ -368,7 +368,7 @@
pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
};
- sdio_cfg_idle: sdio_cfg_idle {
+ sdio_cfg_idle: sdio-cfg-idle-pins {
pinctrl-single,pins = <
0x138 0x0 /* SDIO_CMD (IOCFG078) */
0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
@@ -381,7 +381,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- isp_cfg_func1: isp_cfg_func1 {
+ isp_cfg_func1: isp-cfg-func1-pins {
pinctrl-single,pins = <
0x28 0x0 /* ISP_PWDN0 (IOCFG010) */
0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */
@@ -403,7 +403,7 @@
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- isp_cfg_idle1: isp_cfg_idle1 {
+ isp_cfg_idle1: isp-cfg-idle1-pins {
pinctrl-single,pins = <
0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
@@ -413,7 +413,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- isp_cfg_func2: isp_cfg_func2 {
+ isp_cfg_func2: isp-cfg-func2-pins {
pinctrl-single,pins = <
0x54 0x0 /* ISP_STROBE1 (IOCFG021) */
>;
@@ -422,7 +422,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- codec_clk_cfg_func: codec_clk_cfg_func {
+ codec_clk_cfg_func: codec-clk-cfg-pins {
pinctrl-single,pins = <
0x70 0x0 /* CODEC_CLK (IOCFG028) */
>;
@@ -430,7 +430,7 @@
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
};
- codec_clk_cfg_idle: codec_clk_cfg_idle {
+ codec_clk_cfg_idle: codec-clk-cfg-idle-pins {
pinctrl-single,pins = <
0x70 0x0 /* CODEC_CLK (IOCFG028) */
>;
@@ -439,7 +439,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- codec_cfg_func1: codec_cfg_func1 {
+ codec_cfg_func1: codec-cfg-func1-pins {
pinctrl-single,pins = <
0x74 0x0 /* DMIC_CLK (IOCFG029) */
>;
@@ -448,7 +448,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- codec_cfg_func2: codec_cfg_func2 {
+ codec_cfg_func2: codec-cfg-func2-pins {
pinctrl-single,pins = <
0x78 0x0 /* CODEC_SYNC (IOCFG030) */
0x7c 0x0 /* CODEC_DI (IOCFG031) */
@@ -458,7 +458,7 @@
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
};
- codec_cfg_idle2: codec_cfg_idle2 {
+ codec_cfg_idle2: codec-cfg-idle2-pins {
pinctrl-single,pins = <
0x78 0x0 /* CODEC_SYNC (IOCFG030) */
0x7c 0x0 /* CODEC_DI (IOCFG031) */
@@ -469,7 +469,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- fm_cfg_func: fm_cfg_func {
+ fm_cfg_func: fm-cfg-pins {
pinctrl-single,pins = <
0x84 0x0 /* FM_XCLK (IOCFG033) */
0x88 0x0 /* FM_XFS (IOCFG034) */
@@ -481,7 +481,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- bt_cfg_func: bt_cfg_func {
+ bt_cfg_func: bt-cfg-pins {
pinctrl-single,pins = <
0x94 0x0 /* BT_XCLK (IOCFG037) */
0x98 0x0 /* BT_XFS (IOCFG038) */
@@ -492,7 +492,7 @@
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- bt_cfg_idle: bt_cfg_idle {
+ bt_cfg_idle: bt-cfg-idle-pins {
pinctrl-single,pins = <
0x94 0x0 /* BT_XCLK (IOCFG037) */
0x98 0x0 /* BT_XFS (IOCFG038) */
@@ -504,7 +504,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- pwm_in_cfg_func: pwm_in_cfg_func {
+ pwm_in_cfg_func: pwm-in-cfg-pins {
pinctrl-single,pins = <
0xbc 0x0 /* PWM_IN (IOCFG047) */
>;
@@ -513,7 +513,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- bl_pwm_cfg_func: bl_pwm_cfg_func {
+ bl_pwm_cfg_func: bl-pwm-cfg-pins {
pinctrl-single,pins = <
0xc0 0x0 /* BL_PWM (IOCFG048) */
>;
@@ -522,7 +522,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- uart0_cfg_func1: uart0_cfg_func1 {
+ uart0_cfg_func1: uart0-cfg-func1-pins {
pinctrl-single,pins = <
0xc4 0x0 /* UART0_RXD (IOCFG049) */
>;
@@ -531,7 +531,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- uart0_cfg_func2: uart0_cfg_func2 {
+ uart0_cfg_func2: uart0-cfg-func2-pins {
pinctrl-single,pins = <
0xc8 0x0 /* UART0_TXD (IOCFG050) */
>;
@@ -540,7 +540,7 @@
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
};
- uart1_cfg_func1: uart1_cfg_func1 {
+ uart1_cfg_func1: uart1-cfg-func1-pins {
pinctrl-single,pins = <
0xcc 0x0 /* UART1_CTS_N (IOCFG051) */
0xd4 0x0 /* UART1_RXD (IOCFG053) */
@@ -550,7 +550,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- uart1_cfg_func2: uart1_cfg_func2 {
+ uart1_cfg_func2: uart1-cfg-func2-pins {
pinctrl-single,pins = <
0xd0 0x0 /* UART1_RTS_N (IOCFG052) */
0xd8 0x0 /* UART1_TXD (IOCFG054) */
@@ -560,7 +560,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- uart2_cfg_func: uart2_cfg_func {
+ uart2_cfg_func: uart2-cfg-pins {
pinctrl-single,pins = <
0xdc 0x0 /* UART2_CTS_N (IOCFG055) */
0xe0 0x0 /* UART2_RTS_N (IOCFG056) */
@@ -572,7 +572,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- uart3_cfg_func: uart3_cfg_func {
+ uart3_cfg_func: uart3-cfg-pins {
pinctrl-single,pins = <
0x190 0x0 /* UART3_CTS_N (IOCFG100) */
0x194 0x0 /* UART3_RTS_N (IOCFG101) */
@@ -584,7 +584,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- uart4_cfg_func: uart4_cfg_func {
+ uart4_cfg_func: uart4-cfg-pins {
pinctrl-single,pins = <
0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */
0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */
@@ -596,7 +596,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- uart5_cfg_func: uart5_cfg_func {
+ uart5_cfg_func: uart5-cfg-pins {
pinctrl-single,pins = <
0x1d8 0x0 /* UART4_RXD (IOCFG118) */
0x1dc 0x0 /* UART4_TXD (IOCFG119) */
@@ -606,7 +606,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- i2c0_cfg_func: i2c0_cfg_func {
+ i2c0_cfg_func: i2c0-cfg-pins {
pinctrl-single,pins = <
0xec 0x0 /* I2C0_SCL (IOCFG059) */
0xf0 0x0 /* I2C0_SDA (IOCFG060) */
@@ -616,7 +616,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- i2c1_cfg_func: i2c1_cfg_func {
+ i2c1_cfg_func: i2c1-cfg-pins {
pinctrl-single,pins = <
0xf4 0x0 /* I2C1_SCL (IOCFG061) */
0xf8 0x0 /* I2C1_SDA (IOCFG062) */
@@ -626,7 +626,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- i2c2_cfg_func: i2c2_cfg_func {
+ i2c2_cfg_func: i2c2-cfg-pins {
pinctrl-single,pins = <
0xfc 0x0 /* I2C2_SCL (IOCFG063) */
0x100 0x0 /* I2C2_SDA (IOCFG064) */
@@ -636,7 +636,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- spi0_cfg_func: spi0_cfg_func {
+ spi0_cfg_func: spi0-cfg-pins {
pinctrl-single,pins = <
0x1b0 0x0 /* SPI0_DI (IOCFG108) */
0x1b4 0x0 /* SPI0_DO (IOCFG109) */
@@ -656,7 +656,7 @@
&rstout_n_cfg_func
>;
- rstout_n_cfg_func: rstout_n_cfg_func {
+ rstout_n_cfg_func: rstout-n-cfg-pins {
pinctrl-single,pins = <
0x0 0x0 /* RSTOUT_N (IOCFG000) */
>;
@@ -665,7 +665,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- pmu_peri_en_cfg_func: pmu_peri_en_cfg_func {
+ pmu_peri_en_cfg_func: pmu-peri-en-cfg-pins {
pinctrl-single,pins = <
0x4 0x0 /* PMU_PERI_EN (IOCFG001) */
>;
@@ -674,7 +674,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- sysclk0_en_cfg_func: sysclk0_en_cfg_func {
+ sysclk0_en_cfg_func: sysclk0-en-cfg-pins {
pinctrl-single,pins = <
0x8 0x0 /* SYSCLK0_EN (IOCFG002) */
>;
@@ -683,7 +683,7 @@
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
};
- jtag_tdo_cfg_func: jtag_tdo_cfg_func {
+ jtag_tdo_cfg_func: jtag-tdo-cfg-pins {
pinctrl-single,pins = <
0xc 0x0 /* JTAG_TDO (IOCFG003) */
>;
@@ -692,7 +692,7 @@
pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
};
- rf_reset_cfg_func: rf_reset_cfg_func {
+ rf_reset_cfg_func: rf-reset-cfg-pins {
pinctrl-single,pins = <
0x70 0x0 /* RF_RESET0 (IOCFG028) */
0x74 0x0 /* RF_RESET1 (IOCFG029) */
diff --git a/dts/src/arm64/hisilicon/hikey960-pinctrl.dtsi b/dts/src/arm64/hisilicon/hikey960-pinctrl.dtsi
index 920a3111c6..b801a48041 100644
--- a/dts/src/arm64/hisilicon/hikey960-pinctrl.dtsi
+++ b/dts/src/arm64/hisilicon/hikey960-pinctrl.dtsi
@@ -25,7 +25,7 @@
&range 0 7 0
&range 8 116 0>;
- pmu_pmx_func: pmu_pmx_func {
+ pmu_pmx_func: pmu-pins {
pinctrl-single,pins = <
0x008 MUX_M1 /* PMU1_SSI */
0x00c MUX_M1 /* PMU2_SSI */
@@ -34,19 +34,19 @@
>;
};
- csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func {
+ csi0_pwd_n_pmx_func: csi0-pwd-n-pins {
pinctrl-single,pins = <
0x044 MUX_M0 /* CSI0_PWD_N */
>;
};
- csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func {
+ csi1_pwd_n_pmx_func: csi1-pwd-n-pins {
pinctrl-single,pins = <
0x04c MUX_M0 /* CSI1_PWD_N */
>;
};
- isp0_pmx_func: isp0_pmx_func {
+ isp0_pmx_func: isp0-pins {
pinctrl-single,pins = <
0x058 MUX_M1 /* ISP_CLK0 */
0x064 MUX_M1 /* ISP_SCL0 */
@@ -54,7 +54,7 @@
>;
};
- isp1_pmx_func: isp1_pmx_func {
+ isp1_pmx_func: isp1-pins {
pinctrl-single,pins = <
0x05c MUX_M1 /* ISP_CLK1 */
0x06c MUX_M1 /* ISP_SCL1 */
@@ -62,47 +62,47 @@
>;
};
- pwr_key_pmx_func: pwr_key_pmx_func {
+ pwr_key_pmx_func: pwr-key-pins {
pinctrl-single,pins = <
0x080 MUX_M0 /* GPIO_034 */
>;
};
- i2c3_pmx_func: i2c3_pmx_func {
+ i2c3_pmx_func: i2c3-pins {
pinctrl-single,pins = <
0x02c MUX_M1 /* I2C3_SCL */
0x030 MUX_M1 /* I2C3_SDA */
>;
};
- i2c4_pmx_func: i2c4_pmx_func {
+ i2c4_pmx_func: i2c4-pins {
pinctrl-single,pins = <
0x090 MUX_M1 /* I2C4_SCL */
0x094 MUX_M1 /* I2C4_SDA */
>;
};
- pcie_perstn_pmx_func: pcie_perstn_pmx_func {
+ pcie_perstn_pmx_func: pcie-perstn-pins {
pinctrl-single,pins = <
0x15c MUX_M1 /* PCIE_PERST_N */
>;
};
- usbhub5734_pmx_func: usbhub5734_pmx_func {
+ usbhub5734_pmx_func: usbhub5734-pins {
pinctrl-single,pins = <
0x11c MUX_M0 /* GPIO_073 */
0x120 MUX_M0 /* GPIO_074 */
>;
};
- uart0_pmx_func: uart0_pmx_func {
+ uart0_pmx_func: uart0-pins {
pinctrl-single,pins = <
0x0cc MUX_M2 /* UART0_RXD */
0x0d0 MUX_M2 /* UART0_TXD */
>;
};
- uart1_pmx_func: uart1_pmx_func {
+ uart1_pmx_func: uart1-pins {
pinctrl-single,pins = <
0x0b0 MUX_M2 /* UART1_CTS_N */
0x0b4 MUX_M2 /* UART1_RTS_N */
@@ -111,7 +111,7 @@
>;
};
- uart2_pmx_func: uart2_pmx_func {
+ uart2_pmx_func: uart2-pins {
pinctrl-single,pins = <
0x0bc MUX_M2 /* UART2_CTS_N */
0x0c0 MUX_M2 /* UART2_RTS_N */
@@ -120,7 +120,7 @@
>;
};
- uart3_pmx_func: uart3_pmx_func {
+ uart3_pmx_func: uart3-pins {
pinctrl-single,pins = <
0x0dc MUX_M1 /* UART3_CTS_N */
0x0e0 MUX_M1 /* UART3_RTS_N */
@@ -129,7 +129,7 @@
>;
};
- uart4_pmx_func: uart4_pmx_func {
+ uart4_pmx_func: uart4-pins {
pinctrl-single,pins = <
0x0ec MUX_M1 /* UART4_CTS_N */
0x0f0 MUX_M1 /* UART4_RTS_N */
@@ -138,7 +138,7 @@
>;
};
- uart5_pmx_func: uart5_pmx_func {
+ uart5_pmx_func: uart5-pins {
pinctrl-single,pins = <
0x0c4 MUX_M3 /* UART5_CTS_N */
0x0c8 MUX_M3 /* UART5_RTS_N */
@@ -147,7 +147,7 @@
>;
};
- uart6_pmx_func: uart6_pmx_func {
+ uart6_pmx_func: uart6-pins {
pinctrl-single,pins = <
0x0cc MUX_M1 /* UART6_CTS_N */
0x0d0 MUX_M1 /* UART6_RTS_N */
@@ -156,13 +156,13 @@
>;
};
- cam0_rst_pmx_func: cam0_rst_pmx_func {
+ cam0_rst_pmx_func: cam0-rst-pins {
pinctrl-single,pins = <
0x0c8 MUX_M0 /* CAM0_RST */
>;
};
- cam1_rst_pmx_func: cam1_rst_pmx_func {
+ cam1_rst_pmx_func: cam1-rst-pins {
pinctrl-single,pins = <
0x124 MUX_M0 /* CAM1_RST */
>;
@@ -180,7 +180,7 @@
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 6 0>;
- sd_pmx_func: sd_pmx_func {
+ sd_pmx_func: sd-pins {
pinctrl-single,pins = <
0x000 MUX_M1 /* SD_CLK */
0x004 MUX_M1 /* SD_CMD */
@@ -203,14 +203,14 @@
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 12 0>;
- ufs_pmx_func: ufs_pmx_func {
+ ufs_pmx_func: ufs-pins {
pinctrl-single,pins = <
0x000 MUX_M1 /* UFS_REF_CLK */
0x004 MUX_M1 /* UFS_RST_N */
>;
};
- spi3_pmx_func: spi3_pmx_func {
+ spi3_pmx_func: spi3-pins {
pinctrl-single,pins = <
0x008 MUX_M1 /* SPI3_CLK */
0x00c MUX_M1 /* SPI3_DI */
@@ -231,7 +231,7 @@
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 6 0>;
- sdio_pmx_func: sdio_pmx_func {
+ sdio_pmx_func: sdio-pins {
pinctrl-single,pins = <
0x000 MUX_M1 /* SDIO_CLK */
0x004 MUX_M1 /* SDIO_CMD */
@@ -254,7 +254,7 @@
/* pin base in node, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 42 0>;
- i2s2_pmx_func: i2s2_pmx_func {
+ i2s2_pmx_func: i2s2-pins {
pinctrl-single,pins = <
0x044 MUX_M1 /* I2S2_DI */
0x048 MUX_M1 /* I2S2_DO */
@@ -263,42 +263,42 @@
>;
};
- slimbus_pmx_func: slimbus_pmx_func {
+ slimbus_pmx_func: slimbus-pins {
pinctrl-single,pins = <
0x02c MUX_M1 /* SLIMBUS_CLK */
0x030 MUX_M1 /* SLIMBUS_DATA */
>;
};
- i2c0_pmx_func: i2c0_pmx_func {
+ i2c0_pmx_func: i2c0-pins {
pinctrl-single,pins = <
0x014 MUX_M1 /* I2C0_SCL */
0x018 MUX_M1 /* I2C0_SDA */
>;
};
- i2c1_pmx_func: i2c1_pmx_func {
+ i2c1_pmx_func: i2c1-pins {
pinctrl-single,pins = <
0x01c MUX_M1 /* I2C1_SCL */
0x020 MUX_M1 /* I2C1_SDA */
>;
};
- i2c7_pmx_func: i2c7_pmx_func {
+ i2c7_pmx_func: i2c7-pins {
pinctrl-single,pins = <
0x024 MUX_M3 /* I2C7_SCL */
0x028 MUX_M3 /* I2C7_SDA */
>;
};
- pcie_pmx_func: pcie_pmx_func {
+ pcie_pmx_func: pcie-pins {
pinctrl-single,pins = <
0x084 MUX_M1 /* PCIE_CLKREQ_N */
0x088 MUX_M1 /* PCIE_WAKE_N */
>;
};
- spi2_pmx_func: spi2_pmx_func {
+ spi2_pmx_func: spi2-pins {
pinctrl-single,pins = <
0x08c MUX_M1 /* SPI2_CLK */
0x090 MUX_M1 /* SPI2_DI */
@@ -307,7 +307,7 @@
>;
};
- i2s0_pmx_func: i2s0_pmx_func {
+ i2s0_pmx_func: i2s0-pins {
pinctrl-single,pins = <
0x034 MUX_M1 /* I2S0_DI */
0x038 MUX_M1 /* I2S0_DO */
@@ -323,7 +323,7 @@
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
- pmu_cfg_func: pmu_cfg_func {
+ pmu_cfg_func: pmu-cfg-pins {
pinctrl-single,pins = <
0x010 0x0 /* PMU1_SSI */
0x014 0x0 /* PMU2_SSI */
@@ -347,7 +347,7 @@
>;
};
- i2c3_cfg_func: i2c3_cfg_func {
+ i2c3_cfg_func: i2c3-cfg-pins {
pinctrl-single,pins = <
0x038 0x0 /* I2C3_SCL */
0x03c 0x0 /* I2C3_SDA */
@@ -369,7 +369,7 @@
>;
};
- csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func {
+ csi0_pwd_n_cfg_func: csi0-pwd-n-cfg-pins {
pinctrl-single,pins = <
0x050 0x0 /* CSI0_PWD_N */
>;
@@ -390,7 +390,7 @@
>;
};
- csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func {
+ csi1_pwd_n_cfg_func: csi1-pwd-n-cfg-pins {
pinctrl-single,pins = <
0x058 0x0 /* CSI1_PWD_N */
>;
@@ -411,7 +411,7 @@
>;
};
- isp0_cfg_func: isp0_cfg_func {
+ isp0_cfg_func: isp0-cfg-pins {
pinctrl-single,pins = <
0x064 0x0 /* ISP_CLK0 */
0x070 0x0 /* ISP_SCL0 */
@@ -433,7 +433,7 @@
DRIVE7_04MA DRIVE6_MASK>;
};
- isp1_cfg_func: isp1_cfg_func {
+ isp1_cfg_func: isp1-cfg-pins {
pinctrl-single,pins = <
0x068 0x0 /* ISP_CLK1 */
0x078 0x0 /* ISP_SCL1 */
@@ -456,7 +456,7 @@
>;
};
- pwr_key_cfg_func: pwr_key_cfg_func {
+ pwr_key_cfg_func: pwr-key-cfg-pins {
pinctrl-single,pins = <
0x08c 0x0 /* GPIO_034 */
>;
@@ -477,7 +477,7 @@
>;
};
- uart1_cfg_func: uart1_cfg_func {
+ uart1_cfg_func: uart1-cfg-pins {
pinctrl-single,pins = <
0x0b4 0x0 /* UART1_RXD */
0x0b8 0x0 /* UART1_TXD */
@@ -501,7 +501,7 @@
>;
};
- uart2_cfg_func: uart2_cfg_func {
+ uart2_cfg_func: uart2-cfg-pins {
pinctrl-single,pins = <
0x0c8 0x0 /* UART2_CTS_N */
0x0cc 0x0 /* UART2_RTS_N */
@@ -525,7 +525,7 @@
>;
};
- uart5_cfg_func: uart5_cfg_func {
+ uart5_cfg_func: uart5-cfg-pins {
pinctrl-single,pins = <
0x0c8 0x0 /* UART5_RXD */
0x0cc 0x0 /* UART5_TXD */
@@ -549,7 +549,7 @@
>;
};
- cam0_rst_cfg_func: cam0_rst_cfg_func {
+ cam0_rst_cfg_func: cam0-rst-cfg-pins {
pinctrl-single,pins = <
0x0d4 0x0 /* CAM0_RST */
>;
@@ -570,7 +570,7 @@
>;
};
- uart0_cfg_func: uart0_cfg_func {
+ uart0_cfg_func: uart0-cfg-pins {
pinctrl-single,pins = <
0x0d8 0x0 /* UART0_RXD */
0x0dc 0x0 /* UART0_TXD */
@@ -592,7 +592,7 @@
>;
};
- uart6_cfg_func: uart6_cfg_func {
+ uart6_cfg_func: uart6-cfg-pins {
pinctrl-single,pins = <
0x0d8 0x0 /* UART6_CTS_N */
0x0dc 0x0 /* UART6_RTS_N */
@@ -616,7 +616,7 @@
>;
};
- uart3_cfg_func: uart3_cfg_func {
+ uart3_cfg_func: uart3-cfg-pins {
pinctrl-single,pins = <
0x0e8 0x0 /* UART3_CTS_N */
0x0ec 0x0 /* UART3_RTS_N */
@@ -640,7 +640,7 @@
>;
};
- uart4_cfg_func: uart4_cfg_func {
+ uart4_cfg_func: uart4-cfg-pins {
pinctrl-single,pins = <
0x0f8 0x0 /* UART4_CTS_N */
0x0fc 0x0 /* UART4_RTS_N */
@@ -664,7 +664,7 @@
>;
};
- cam1_rst_cfg_func: cam1_rst_cfg_func {
+ cam1_rst_cfg_func: cam1-rst-cfg-pins {
pinctrl-single,pins = <
0x130 0x0 /* CAM1_RST */
>;
@@ -692,7 +692,7 @@
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
- ufs_cfg_func: ufs_cfg_func {
+ ufs_cfg_func: ufs-cfg-pins {
pinctrl-single,pins = <
0x000 0x0 /* UFS_REF_CLK */
0x004 0x0 /* UFS_RST_N */
@@ -714,7 +714,7 @@
>;
};
- spi3_cfg_func: spi3_cfg_func {
+ spi3_cfg_func: spi3-cfg-pins {
pinctrl-single,pins = <
0x008 0x0 /* SPI3_CLK */
0x00c 0x0 /* SPI3_DI */
@@ -745,7 +745,7 @@
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
- sdio_clk_cfg_func: sdio_clk_cfg_func {
+ sdio_clk_cfg_func: sdio-clk-cfg-pins {
pinctrl-single,pins = <
0x000 0x0 /* SDIO_CLK */
>;
@@ -766,7 +766,7 @@
>;
};
- sdio_cfg_func: sdio_cfg_func {
+ sdio_cfg_func: sdio-cfg-pins {
pinctrl-single,pins = <
0x004 0x0 /* SDIO_CMD */
0x008 0x0 /* SDIO_DATA0 */
@@ -798,7 +798,7 @@
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
- sd_clk_cfg_func: sd_clk_cfg_func {
+ sd_clk_cfg_func: sd-clk-cfg-pins {
pinctrl-single,pins = <
0x000 0x0 /* SD_CLK */
>;
@@ -820,7 +820,7 @@
>;
};
- sd_cfg_func: sd_cfg_func {
+ sd_cfg_func: sd-cfg-pins {
pinctrl-single,pins = <
0x004 0x0 /* SD_CMD */
0x008 0x0 /* SD_DATA0 */
@@ -853,7 +853,7 @@
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
- i2c0_cfg_func: i2c0_cfg_func {
+ i2c0_cfg_func: i2c0-cfg-pins {
pinctrl-single,pins = <
0x01c 0x0 /* I2C0_SCL */
0x020 0x0 /* I2C0_SDA */
@@ -875,7 +875,7 @@
>;
};
- i2c1_cfg_func: i2c1_cfg_func {
+ i2c1_cfg_func: i2c1-cfg-pins {
pinctrl-single,pins = <
0x024 0x0 /* I2C1_SCL */
0x028 0x0 /* I2C1_SDA */
@@ -897,7 +897,7 @@
>;
};
- i2c7_cfg_func: i2c7_cfg_func {
+ i2c7_cfg_func: i2c7-cfg-pins {
pinctrl-single,pins = <
0x02c 0x0 /* I2C7_SCL */
0x030 0x0 /* I2C7_SDA */
@@ -919,7 +919,7 @@
>;
};
- slimbus_cfg_func: slimbus_cfg_func {
+ slimbus_cfg_func: slimbus-cfg-pins {
pinctrl-single,pins = <
0x034 0x0 /* SLIMBUS_CLK */
0x038 0x0 /* SLIMBUS_DATA */
@@ -941,7 +941,7 @@
>;
};
- i2s0_cfg_func: i2s0_cfg_func {
+ i2s0_cfg_func: i2s0-cfg-pins {
pinctrl-single,pins = <
0x040 0x0 /* I2S0_DI */
0x044 0x0 /* I2S0_DO */
@@ -965,7 +965,7 @@
>;
};
- i2s2_cfg_func: i2s2_cfg_func {
+ i2s2_cfg_func: i2s2-cfg-pins {
pinctrl-single,pins = <
0x050 0x0 /* I2S2_DI */
0x054 0x0 /* I2S2_DO */
@@ -989,7 +989,7 @@
>;
};
- pcie_cfg_func: pcie_cfg_func {
+ pcie_cfg_func: pcie-cfg-pins {
pinctrl-single,pins = <
0x094 0x0 /* PCIE_CLKREQ_N */
0x098 0x0 /* PCIE_WAKE_N */
@@ -1011,7 +1011,7 @@
>;
};
- spi2_cfg_func: spi2_cfg_func {
+ spi2_cfg_func: spi2-cfg-pins {
pinctrl-single,pins = <
0x09c 0x0 /* SPI2_CLK */
0x0a0 0x0 /* SPI2_DI */
@@ -1035,7 +1035,7 @@
>;
};
- usb_cfg_func: usb_cfg_func {
+ usb_cfg_func: usb-cfg-pins {
pinctrl-single,pins = <
0x0ac 0x0 /* GPIO_219 */
>;
diff --git a/dts/src/arm64/hisilicon/hikey970-pinctrl.dtsi b/dts/src/arm64/hisilicon/hikey970-pinctrl.dtsi
index 77bd8c3a83..8f7bf80e6e 100644
--- a/dts/src/arm64/hisilicon/hikey970-pinctrl.dtsi
+++ b/dts/src/arm64/hisilicon/hikey970-pinctrl.dtsi
@@ -21,14 +21,14 @@
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 82 0>;
- uart0_pmx_func: uart0_pmx_func {
+ uart0_pmx_func: uart0-pins {
pinctrl-single,pins = <
0x054 MUX_M2 /* UART0_RXD */
0x058 MUX_M2 /* UART0_TXD */
>;
};
- uart2_pmx_func: uart2_pmx_func {
+ uart2_pmx_func: uart2-pins {
pinctrl-single,pins = <
0x700 MUX_M2 /* UART2_CTS_N */
0x704 MUX_M2 /* UART2_RTS_N */
@@ -37,7 +37,7 @@
>;
};
- uart3_pmx_func: uart3_pmx_func {
+ uart3_pmx_func: uart3-pins {
pinctrl-single,pins = <
0x064 MUX_M1 /* UART3_CTS_N */
0x068 MUX_M1 /* UART3_RTS_N */
@@ -46,7 +46,7 @@
>;
};
- uart4_pmx_func: uart4_pmx_func {
+ uart4_pmx_func: uart4-pins {
pinctrl-single,pins = <
0x074 MUX_M1 /* UART4_CTS_N */
0x078 MUX_M1 /* UART4_RTS_N */
@@ -55,52 +55,52 @@
>;
};
- uart6_pmx_func: uart6_pmx_func {
+ uart6_pmx_func: uart6-pins {
pinctrl-single,pins = <
0x05c MUX_M1 /* UART6_RXD */
0x060 MUX_M1 /* UART6_TXD */
>;
};
- i2c3_pmx_func: i2c3_pmx_func {
+ i2c3_pmx_func: i2c3-pins {
pinctrl-single,pins = <
0x010 MUX_M1 /* I2C3_SCL */
0x014 MUX_M1 /* I2C3_SDA */
>;
};
- i2c4_pmx_func: i2c4_pmx_func {
+ i2c4_pmx_func: i2c4-pins {
pinctrl-single,pins = <
0x03c MUX_M1 /* I2C4_SCL */
0x040 MUX_M1 /* I2C4_SDA */
>;
};
- cam0_rst_pmx_func: cam0_rst_pmx_func {
+ cam0_rst_pmx_func: cam0-rst-pins {
pinctrl-single,pins = <
0x714 MUX_M0 /* CAM0_RST */
>;
};
- cam1_rst_pmx_func: cam1_rst_pmx_func {
+ cam1_rst_pmx_func: cam1-rst-pins {
pinctrl-single,pins = <
0x048 MUX_M0 /* CAM1_RST */
>;
};
- cam0_pwd_n_pmx_func: cam0_pwd_n_pmx_func {
+ cam0_pwd_n_pmx_func: cam0-pwd-n-pins {
pinctrl-single,pins = <
0x098 MUX_M0 /* CAM0_PWD_N */
>;
};
- cam1_pwd_n_pmx_func: cam1_pwd_n_pmx_func {
+ cam1_pwd_n_pmx_func: cam1-pwd-n-pins {
pinctrl-single,pins = <
0x044 MUX_M0 /* CAM1_PWD_N */
>;
};
- isp0_pmx_func: isp0_pmx_func {
+ isp0_pmx_func: isp0-pins {
pinctrl-single,pins = <
0x018 MUX_M1 /* ISP_CLK0 */
0x024 MUX_M1 /* ISP_SCL0 */
@@ -108,7 +108,7 @@
>;
};
- isp1_pmx_func: isp1_pmx_func {
+ isp1_pmx_func: isp1-pins {
pinctrl-single,pins = <
0x01c MUX_M1 /* ISP_CLK1 */
0x02c MUX_M1 /* ISP_SCL1 */
@@ -127,19 +127,19 @@
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 46 0>;
- pwr_key_pmx_func: pwr_key_pmx_func {
+ pwr_key_pmx_func: pwr-key-pins {
pinctrl-single,pins = <
0x064 MUX_M0 /* GPIO_203 */
>;
};
- pd_pmx_func: pd_pmx_func{
+ pd_pmx_func: pd-pins {
pinctrl-single,pins = <
0x080 MUX_M0 /* GPIO_221 */
>;
};
- i2s2_pmx_func: i2s2_pmx_func {
+ i2s2_pmx_func: i2s2-pins {
pinctrl-single,pins = <
0x050 MUX_M1 /* I2S2_DI */
0x054 MUX_M1 /* I2S2_DO */
@@ -148,7 +148,7 @@
>;
};
- spi0_pmx_func: spi0_pmx_func {
+ spi0_pmx_func: spi0-pins {
pinctrl-single,pins = <
0x094 MUX_M1 /* SPI0_CLK */
0x098 MUX_M1 /* SPI0_DI */
@@ -157,7 +157,7 @@
>;
};
- spi2_pmx_func: spi2_pmx_func {
+ spi2_pmx_func: spi2-pins {
pinctrl-single,pins = <
0x710 MUX_M1 /* SPI2_CLK */
0x714 MUX_M1 /* SPI2_DI */
@@ -166,7 +166,7 @@
>;
};
- spi3_pmx_func: spi3_pmx_func {
+ spi3_pmx_func: spi3-pins {
pinctrl-single,pins = <
0x72c MUX_M1 /* SPI3_CLK */
0x730 MUX_M1 /* SPI3_DI */
@@ -175,37 +175,37 @@
>;
};
- i2c0_pmx_func: i2c0_pmx_func {
+ i2c0_pmx_func: i2c0-pins {
pinctrl-single,pins = <
0x020 MUX_M1 /* I2C0_SCL */
0x024 MUX_M1 /* I2C0_SDA */
>;
};
- i2c1_pmx_func: i2c1_pmx_func {
+ i2c1_pmx_func: i2c1-pins {
pinctrl-single,pins = <
0x028 MUX_M1 /* I2C1_SCL */
0x02c MUX_M1 /* I2C1_SDA */
>;
};
- i2c2_pmx_func: i2c2_pmx_func {
+ i2c2_pmx_func: i2c2-pins {
pinctrl-single,pins = <
0x030 MUX_M1 /* I2C2_SCL */
0x034 MUX_M1 /* I2C2_SDA */
>;
};
- pcie_clkreq_pmx_func: pcie_clkreq_pmx_func {
+ pcie_clkreq_pmx_func: pcie-clkreq-pins {
pinctrl-single,pins = <
0x084 MUX_M1 /* PCIE0_CLKREQ_N */
>;
};
- gpio185_pmx_func: gpio185_pmx_func {
+ gpio185_pmx_func: gpio185-pins {
pinctrl-single,pins = <0x01C 0x1>;
};
- gpio185_pmx_idle: gpio185_pmx_idle {
+ gpio185_pmx_idle: gpio185-idle-pins {
pinctrl-single,pins = <0x01C 0x0>;
};
};
@@ -216,7 +216,7 @@
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
- uart0_cfg_func: uart0_cfg_func {
+ uart0_cfg_func: uart0-cfg-pins {
pinctrl-single,pins = <
0x058 0x0 /* UART0_RXD */
0x05c 0x0 /* UART0_TXD */
@@ -238,7 +238,7 @@
>;
};
- uart2_cfg_func: uart2_cfg_func {
+ uart2_cfg_func: uart2-cfg-pins {
pinctrl-single,pins = <
0x700 0x0 /* UART2_CTS_N */
0x704 0x0 /* UART2_RTS_N */
@@ -262,7 +262,7 @@
>;
};
- uart3_cfg_func: uart3_cfg_func {
+ uart3_cfg_func: uart3-cfg-pins {
pinctrl-single,pins = <
0x068 0x0 /* UART3_CTS_N */
0x06c 0x0 /* UART3_RTS_N */
@@ -286,7 +286,7 @@
>;
};
- uart4_cfg_func: uart4_cfg_func {
+ uart4_cfg_func: uart4-cfg-pins {
pinctrl-single,pins = <
0x078 0x0 /* UART4_CTS_N */
0x07c 0x0 /* UART4_RTS_N */
@@ -310,7 +310,7 @@
>;
};
- uart6_cfg_func: uart6_cfg_func {
+ uart6_cfg_func: uart6-cfg-pins {
pinctrl-single,pins = <
0x060 0x0 /* UART6_RXD */
0x064 0x0 /* UART6_TXD */
@@ -332,7 +332,7 @@
>;
};
- i2c3_cfg_func: i2c3_cfg_func {
+ i2c3_cfg_func: i2c3-cfg-pins {
pinctrl-single,pins = <
0x014 0x0 /* I2C3_SCL */
0x018 0x0 /* I2C3_SDA */
@@ -354,7 +354,7 @@
>;
};
- i2c4_cfg_func: i2c4_cfg_func {
+ i2c4_cfg_func: i2c4-cfg-pins {
pinctrl-single,pins = <
0x040 0x0 /* I2C4_SCL */
0x044 0x0 /* I2C4_SDA */
@@ -376,7 +376,7 @@
>;
};
- cam0_rst_cfg_func: cam0_rst_cfg_func {
+ cam0_rst_cfg_func: cam0-rst-cfg-pins {
pinctrl-single,pins = <
0x714 0x0 /* CAM0_RST */
>;
@@ -397,7 +397,7 @@
>;
};
- cam1_rst_cfg_func: cam1_rst_cfg_func {
+ cam1_rst_cfg_func: cam1-rst-cfg-pins {
pinctrl-single,pins = <
0x04C 0x0 /* CAM1_RST */
>;
@@ -418,7 +418,7 @@
>;
};
- cam0_pwd_n_cfg_func: cam0_pwd_n_cfg_func {
+ cam0_pwd_n_cfg_func: cam0-pwd-n-cfg-pins {
pinctrl-single,pins = <
0x09C 0x0 /* CAM0_PWD_N */
>;
@@ -439,7 +439,7 @@
>;
};
- cam1_pwd_n_cfg_func: cam1_pwd_n_cfg_func {
+ cam1_pwd_n_cfg_func: cam1-pwd-n-cfg-pins {
pinctrl-single,pins = <
0x048 0x0 /* CAM1_PWD_N */
>;
@@ -460,7 +460,7 @@
>;
};
- isp0_cfg_func: isp0_cfg_func {
+ isp0_cfg_func: isp0-cfg-pins {
pinctrl-single,pins = <
0x01C 0x0 /* ISP_CLK0 */
0x028 0x0 /* ISP_SCL0 */
@@ -483,7 +483,7 @@
>;
};
- isp1_cfg_func: isp1_cfg_func {
+ isp1_cfg_func: isp1-cfg-pins {
pinctrl-single,pins = <
0x020 0x0 /* ISP_CLK1 */
0x030 0x0 /* ISP_SCL1 */
@@ -517,7 +517,7 @@
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 10 0>;
- sdio_pmx_func: sdio_pmx_func {
+ sdio_pmx_func: sdio-pins {
pinctrl-single,pins = <
0x000 MUX_M1 /* SDIO_CLK */
0x004 MUX_M1 /* SDIO_CMD */
@@ -535,7 +535,7 @@
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
- sdio_clk_cfg_func: sdio_clk_cfg_func {
+ sdio_clk_cfg_func: sdio-clk-cfg-pins {
pinctrl-single,pins = <
0x000 0x0 /* SDIO_CLK */
>;
@@ -556,7 +556,7 @@
>;
};
- sdio_cfg_func: sdio_cfg_func {
+ sdio_cfg_func: sdio-cfg-pins {
pinctrl-single,pins = <
0x004 0x0 /* SDIO_CMD */
0x008 0x0 /* SDIO_DATA0 */
@@ -592,7 +592,7 @@
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 12 0>;
- sd_pmx_func: sd_pmx_func {
+ sd_pmx_func: sd-pins {
pinctrl-single,pins = <
0x000 MUX_M1 /* SD_CLK */
0x004 MUX_M1 /* SD_CMD */
@@ -610,7 +610,7 @@
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
- sd_clk_cfg_func: sd_clk_cfg_func {
+ sd_clk_cfg_func: sd-clk-cfg-pins {
pinctrl-single,pins = <
0x000 0x0 /* SD_CLK */
>;
@@ -632,7 +632,7 @@
>;
};
- sd_cfg_func: sd_cfg_func {
+ sd_cfg_func: sd-cfg-pins {
pinctrl-single,pins = <
0x004 0x0 /* SD_CMD */
0x008 0x0 /* SD_DATA0 */
@@ -665,7 +665,7 @@
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
- pwr_key_cfg_func: pwr_key_cfg_func {
+ pwr_key_cfg_func: pwr-key-cfg-pins {
pinctrl-single,pins = <
0x090 0x0 /* GPIO_203 */
>;
@@ -686,7 +686,7 @@
>;
};
- usb_cfg_func: usb_cfg_func {
+ usb_cfg_func: usb-cfg-pins {
pinctrl-single,pins = <
0x0AC 0x0 /* GPIO_221 */
>;
@@ -707,7 +707,7 @@
>;
};
- spi0_cfg_func: spi0_cfg_func {
+ spi0_cfg_func: spi0-cfg-pins {
pinctrl-single,pins = <
0x0c8 0x0 /* SPI0_DI */
0x0cc 0x0 /* SPI0_DO */
@@ -730,7 +730,7 @@
>;
};
- spi2_cfg_func: spi2_cfg_func {
+ spi2_cfg_func: spi2-cfg-pins {
pinctrl-single,pins = <
0x714 0x0 /* SPI2_DI */
0x718 0x0 /* SPI2_DO */
@@ -753,7 +753,7 @@
>;
};
- spi3_cfg_func: spi3_cfg_func {
+ spi3_cfg_func: spi3-cfg-pins {
pinctrl-single,pins = <
0x730 0x0 /* SPI3_DI */
0x734 0x0 /* SPI3_DO */
@@ -776,7 +776,7 @@
>;
};
- spi0_clk_cfg_func: spi0_clk_cfg_func {
+ spi0_clk_cfg_func: spi0-clk-cfg-pins {
pinctrl-single,pins = <
0x0c4 0x0 /* SPI0_CLK */
>;
@@ -797,7 +797,7 @@
>;
};
- spi2_clk_cfg_func: spi2_clk_cfg_func {
+ spi2_clk_cfg_func: spi2-clk-cfg-pins {
pinctrl-single,pins = <
0x710 0x0 /* SPI2_CLK */
>;
@@ -818,7 +818,7 @@
>;
};
- spi3_clk_cfg_func: spi3_clk_cfg_func {
+ spi3_clk_cfg_func: spi3-clk-cfg-pins {
pinctrl-single,pins = <
0x72c 0x0 /* SPI3_CLK */
>;
@@ -839,7 +839,7 @@
>;
};
- i2c0_cfg_func: i2c0_cfg_func {
+ i2c0_cfg_func: i2c0-cfg-pins {
pinctrl-single,pins = <
0x04c 0x0 /* I2C0_SCL */
0x050 0x0 /* I2C0_SDA */
@@ -861,7 +861,7 @@
>;
};
- i2c1_cfg_func: i2c1_cfg_func {
+ i2c1_cfg_func: i2c1-cfg-pins {
pinctrl-single,pins = <
0x054 0x0 /* I2C1_SCL */
0x058 0x0 /* I2C1_SDA */
@@ -883,7 +883,7 @@
>;
};
- i2c2_cfg_func: i2c2_cfg_func {
+ i2c2_cfg_func: i2c2-cfg-pins {
pinctrl-single,pins = <
0x05c 0x0 /* I2C2_SCL */
0x060 0x0 /* I2C2_SDA */
@@ -905,7 +905,7 @@
>;
};
- pcie_clkreq_cfg_func: pcie_clkreq_cfg_func {
+ pcie_clkreq_cfg_func: pcie-clkreq-cfg-pins {
pinctrl-single,pins = <
0x0b0 0x0
>;
@@ -925,7 +925,7 @@
DRIVE7_06MA DRIVE6_MASK
>;
};
- i2s2_cfg_func: i2s2_cfg_func {
+ i2s2_cfg_func: i2s2-cfg-pins {
pinctrl-single,pins = <
0x07c 0x0 /* I2S2_DI */
0x080 0x0 /* I2S2_DO */
@@ -949,7 +949,7 @@
>;
};
- gpio185_cfg_func: gpio185_cfg_func {
+ gpio185_cfg_func: gpio185-cfg-pins {
pinctrl-single,pins = <0x048 0>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
@@ -957,7 +957,7 @@
pinctrl-single,slew-rate = <0x0 0x80>;
};
- gpio185_cfg_idle: gpio185_cfg_idle {
+ gpio185_cfg_idle: gpio185-cfg-idle-pins {
pinctrl-single,pins = <0x048 0>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
diff --git a/dts/src/arm64/hisilicon/hikey970-pmic.dtsi b/dts/src/arm64/hisilicon/hikey970-pmic.dtsi
index 970047f2da..299c4ab630 100644
--- a/dts/src/arm64/hisilicon/hikey970-pmic.dtsi
+++ b/dts/src/arm64/hisilicon/hikey970-pmic.dtsi
@@ -10,10 +10,9 @@
/ {
spmi: spmi@fff24000 {
compatible = "hisilicon,kirin970-spmi-controller";
+ reg = <0x0 0xfff24000 0x0 0x1000>;
#address-cells = <2>;
#size-cells = <0>;
- status = "okay";
- reg = <0x0 0xfff24000 0x0 0x1000>;
hisilicon,spmi-channel = <2>;
pmic: pmic@0 {
@@ -25,9 +24,6 @@
gpios = <&gpio28 0 0>;
regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
ldo3: ldo3 { /* HDMI */
regulator-name = "ldo3";
regulator-min-microvolt = <1500000>;
diff --git a/dts/src/arm64/hisilicon/hip05-d02.dts b/dts/src/arm64/hisilicon/hip05-d02.dts
index 40f3e00ac8..c4eaebbb44 100644
--- a/dts/src/arm64/hisilicon/hip05-d02.dts
+++ b/dts/src/arm64/hisilicon/hip05-d02.dts
@@ -27,12 +27,10 @@
stdout-path = "serial0:115200n8";
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- pwrbutton {
+ pwr-button {
label = "Power Button";
gpios = <&porta 8 GPIO_ACTIVE_LOW>;
linux,code = <116>;
diff --git a/dts/src/arm64/hisilicon/hip05.dtsi b/dts/src/arm64/hisilicon/hip05.dtsi
index 7b2abd10d3..65ddc0698f 100644
--- a/dts/src/arm64/hisilicon/hip05.dtsi
+++ b/dts/src/arm64/hisilicon/hip05.dtsi
@@ -211,18 +211,26 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
};
diff --git a/dts/src/arm64/hisilicon/hip06.dtsi b/dts/src/arm64/hisilicon/hip06.dtsi
index 70d7732dd3..f46c33d107 100644
--- a/dts/src/arm64/hisilicon/hip06.dtsi
+++ b/dts/src/arm64/hisilicon/hip06.dtsi
@@ -211,18 +211,26 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
};
@@ -537,7 +545,7 @@
port@1 {
reg = <1>;
- serdes-syscon= <&serdes_ctrl>;
+ serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <1>;
port-mode-offset = <1>;
media-type = "fiber";
@@ -546,7 +554,7 @@
port@4 {
reg = <4>;
phy-handle = <&phy0>;
- serdes-syscon= <&serdes_ctrl>;
+ serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <4>;
port-mode-offset = <2>;
media-type = "copper";
@@ -555,14 +563,14 @@
port@5 {
reg = <5>;
phy-handle = <&phy1>;
- serdes-syscon= <&serdes_ctrl>;
+ serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <5>;
port-mode-offset = <3>;
media-type = "copper";
};
};
- eth0: ethernet-4{
+ eth0: ethernet-4 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <4>;
@@ -571,7 +579,7 @@
dma-coherent;
};
- eth1: ethernet-5{
+ eth1: ethernet-5 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <5>;
@@ -580,7 +588,7 @@
dma-coherent;
};
- eth2: ethernet-0{
+ eth2: ethernet-0 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <0>;
@@ -589,7 +597,7 @@
dma-coherent;
};
- eth3: ethernet-1{
+ eth3: ethernet-1 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <1>;
diff --git a/dts/src/arm64/hisilicon/hip07.dtsi b/dts/src/arm64/hisilicon/hip07.dtsi
index 6baf6a6864..81d907ef43 100644
--- a/dts/src/arm64/hisilicon/hip07.dtsi
+++ b/dts/src/arm64/hisilicon/hip07.dtsi
@@ -842,66 +842,98 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster4_l2: l2-cache4 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster5_l2: l2-cache5 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster6_l2: l2-cache6 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster7_l2: l2-cache7 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster8_l2: l2-cache8 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster9_l2: l2-cache9 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster10_l2: l2-cache10 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster11_l2: l2-cache11 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster12_l2: l2-cache12 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster13_l2: l2-cache13 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster14_l2: l2-cache14 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster15_l2: l2-cache15 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
};
@@ -1238,7 +1270,7 @@
};
};
- uart0: uart@602b0000 {
+ uart0: serial@602b0000 {
compatible = "arm,sbsa-uart";
reg = <0x0 0x602b0000 0x0 0x1000>;
interrupt-parent = <&mbigen_uart>;
@@ -1422,7 +1454,7 @@
port@1 {
reg = <1>;
- serdes-syscon= <&serdes_ctrl>;
+ serdes-syscon = <&serdes_ctrl>;
cpld-syscon = <&dsa_cpld 0x4>;
port-rst-offset = <1>;
port-mode-offset = <1>;
@@ -1433,7 +1465,7 @@
port@4 {
reg = <4>;
phy-handle = <&phy0>;
- serdes-syscon= <&serdes_ctrl>;
+ serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <4>;
port-mode-offset = <2>;
mc-mac-mask = [ff f0 00 00 00 00];
@@ -1443,7 +1475,7 @@
port@5 {
reg = <5>;
phy-handle = <&phy1>;
- serdes-syscon= <&serdes_ctrl>;
+ serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <5>;
port-mode-offset = <3>;
mc-mac-mask = [ff f0 00 00 00 00];
@@ -1451,7 +1483,7 @@
};
};
- eth0: ethernet@4{
+ eth0: ethernet@4 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <4>;
@@ -1460,7 +1492,7 @@
dma-coherent;
};
- eth1: ethernet@5{
+ eth1: ethernet@5 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <5>;
@@ -1469,7 +1501,7 @@
dma-coherent;
};
- eth2: ethernet@0{
+ eth2: ethernet@0 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <0>;
@@ -1478,7 +1510,7 @@
dma-coherent;
};
- eth3: ethernet@1{
+ eth3: ethernet@1 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <1>;
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-28 06:36:51 +0000