diff options
Diffstat (limited to 'dts/src/arm64/marvell/cn9130-crb.dtsi')
| -rw-r--r-- | dts/src/arm64/marvell/cn9130-crb.dtsi | 145 |
1 files changed, 142 insertions, 3 deletions
diff --git a/dts/src/arm64/marvell/cn9130-crb.dtsi b/dts/src/arm64/marvell/cn9130-crb.dtsi index 505ae69289..6fcc34f7b4 100644 --- a/dts/src/arm64/marvell/cn9130-crb.dtsi +++ b/dts/src/arm64/marvell/cn9130-crb.dtsi @@ -17,6 +17,8 @@ ethernet0 = &cp0_eth0; ethernet1 = &cp0_eth1; ethernet2 = &cp0_eth2; + gpio1 = &cp0_gpio1; + gpio2 = &cp0_gpio2; }; memory@0 { @@ -71,6 +73,17 @@ enable-active-high; regulator-always-on; }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&cp0_i2c1>; + mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>; + los-gpios = <&expander0 15 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + status = "okay"; + }; }; &uart0 { @@ -107,13 +120,21 @@ "mpp59", "mpp60", "mpp61"; marvell,function = "sdio"; }; - cp0_spi0_pins: cp0-spi-pins-0 { + cp0_spi1_pins: cp0-spi-pins-1 { marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; marvell,function = "spi1"; }; }; }; +&cp0_gpio1 { + status = "okay"; +}; + +&cp0_gpio2 { + status = "okay"; +}; + &cp0_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&cp0_i2c0_pins>; @@ -149,12 +170,12 @@ &cp0_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cp0_spi0_pins>; + pinctrl-0 = <&cp0_spi1_pins>; reg = <0x700680 0x50>, /* control */ <0x2000000 0x1000000>; /* CS0 */ status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "jedec,spi-nor"; @@ -185,6 +206,124 @@ phy0: ethernet-phy@0 { reg = <0>; }; + + switch6: ethernet-switch@6 { + /* Actual device is MV88E6393X */ + compatible = "marvell,mv88e6190"; + reg = <6>; + interrupt-parent = <&cp0_gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + dsa,member = <0 0>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-port@1 { + reg = <1>; + label = "p1"; + phy-handle = <&switch0phy1>; + }; + + ethernet-port@2 { + reg = <2>; + label = "p2"; + phy-handle = <&switch0phy2>; + }; + + ethernet-port@3 { + reg = <3>; + label = "p3"; + phy-handle = <&switch0phy3>; + }; + + ethernet-port@4 { + reg = <4>; + label = "p4"; + phy-handle = <&switch0phy4>; + }; + + ethernet-port@5 { + reg = <5>; + label = "p5"; + phy-handle = <&switch0phy5>; + }; + + ethernet-port@6 { + reg = <6>; + label = "p6"; + phy-handle = <&switch0phy6>; + }; + + ethernet-port@7 { + reg = <7>; + label = "p7"; + phy-handle = <&switch0phy7>; + }; + + ethernet-port@8 { + reg = <8>; + label = "p8"; + phy-handle = <&switch0phy8>; + }; + + ethernet-port@9 { + reg = <9>; + label = "p9"; + phy-mode = "10gbase-r"; + sfp = <&sfp>; + managed = "in-band-status"; + }; + + ethernet-port@a { + reg = <10>; + ethernet = <&cp0_eth0>; + phy-mode = "10gbase-r"; + managed = "in-band-status"; + }; + + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch0phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + switch0phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + switch0phy3: ethernet-phy@3 { + reg = <0x3>; + }; + + switch0phy4: ethernet-phy@4 { + reg = <0x4>; + }; + + switch0phy5: ethernet-phy@5 { + reg = <0x5>; + }; + + switch0phy6: ethernet-phy@6 { + reg = <0x6>; + }; + + switch0phy7: ethernet-phy@7 { + reg = <0x7>; + }; + + switch0phy8: ethernet-phy@8 { + reg = <0x8>; + }; + }; + }; }; &cp0_xmdio { |