diff options
Diffstat (limited to 'dts/src/arm64/marvell')
35 files changed, 1436 insertions, 352 deletions
diff --git a/dts/src/arm64/marvell/ac5-98dx25xx.dtsi b/dts/src/arm64/marvell/ac5-98dx25xx.dtsi new file mode 100644 index 0000000000..b5e042b8e9 --- /dev/null +++ b/dts/src/arm64/marvell/ac5-98dx25xx.dtsi @@ -0,0 +1,339 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For AC5. + * + * Copyright (C) 2021 Marvell + * Copyright (C) 2022 Allied Telesis Labs + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Marvell AC5 SoC"; + compatible = "marvell,ac5"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + internal-regs@7f000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + /* 16M internal register @ 0x7f00_0000 */ + ranges = <0x0 0x0 0x7f000000 0x1000000>; + dma-coherent; + + uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&cnm_clock>; + status = "okay"; + }; + + uart1: serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&cnm_clock>; + status = "disabled"; + }; + + uart2: serial@12200 { + compatible = "snps,dw-apb-uart"; + reg = <0x12200 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&cnm_clock>; + status = "disabled"; + }; + + uart3: serial@12300 { + compatible = "snps,dw-apb-uart"; + reg = <0x12300 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&cnm_clock>; + status = "disabled"; + }; + + mdio: mdio@22004 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x22004 0x4>; + clocks = <&cnm_clock>; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv78230-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&cnm_clock>; + clock-names = "core"; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <100000>; + + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-1 = <&i2c0_gpio>; + scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv78230-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&cnm_clock>; + clock-names = "core"; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <100000>; + + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_gpio>; + scl-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "disabled"; + }; + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl0 0 0 32>; + marvell,pwm-offset = <0x1f0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpio1: gpio@18140 { + reg = <0x18140 0x40>; + compatible = "marvell,orion-gpio"; + ngpios = <14>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl0 0 32 14>; + marvell,pwm-offset = <0x1f0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + /* + * Dedicated section for devices behind 32bit controllers so we + * can configure specific DMA mapping for them + */ + behind-32bit-controller@7f000000 { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>; + /* Host phy ram starts at 0x200M */ + dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>; + dma-coherent; + + eth0: ethernet@20000 { + compatible = "marvell,armada-ac5-neta"; + reg = <0x0 0x20000 0x0 0x4000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cnm_clock>; + phy-mode = "sgmii"; + status = "disabled"; + }; + + eth1: ethernet@24000 { + compatible = "marvell,armada-ac5-neta"; + reg = <0x0 0x24000 0x0 0x4000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cnm_clock>; + phy-mode = "sgmii"; + status = "disabled"; + }; + + usb0: usb@80000 { + compatible = "marvell,orion-ehci"; + reg = <0x0 0x80000 0x0 0x500>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + usb1: usb@a0000 { + compatible = "marvell,orion-ehci"; + reg = <0x0 0xa0000 0x0 0x500>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + pinctrl0: pinctrl@80020100 { + compatible = "marvell,ac5-pinctrl"; + reg = <0 0x80020100 0 0x20>; + + i2c0_pins: i2c0-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c0"; + }; + + i2c0_gpio: i2c0-gpio-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + + i2c1_pins: i2c1-pins { + marvell,pins = "mpp20", "mpp21"; + marvell,function = "i2c1"; + }; + + i2c1_gpio: i2c1-gpio-pins { + marvell,pins = "mpp20", "mpp21"; + marvell,function = "i2c1"; + }; + }; + + spi0: spi@805a0000 { + compatible = "marvell,armada-3700-spi"; + reg = <0x0 0x805a0000 0x0 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&spi_clock>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + status = "disabled"; + }; + + spi1: spi@805a8000 { + compatible = "marvell,armada-3700-spi"; + reg = <0x0 0x805a8000 0x0 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&spi_clock>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + status = "disabled"; + }; + + nand: nand-controller@805b0000 { + compatible = "marvell,ac5-nand-controller"; + reg = <0x0 0x805b0000 0x0 0x00000054>; + #address-cells = <0x1>; + #size-cells = <0x0>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&nand_clock>; + status = "disabled"; + }; + + gic: interrupt-controller@80600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ + <0x0 0x80660000 0x0 0x40000>; /* GICR */ + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + clocks { + cnm_clock: cnm-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <328000000>; + }; + + spi_clock: spi-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + nand_clock: nand-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + }; +}; diff --git a/dts/src/arm64/marvell/ac5-98dx35xx-rd.dts b/dts/src/arm64/marvell/ac5-98dx35xx-rd.dts new file mode 100644 index 0000000000..f0ebdb84ee --- /dev/null +++ b/dts/src/arm64/marvell/ac5-98dx35xx-rd.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For RD-AC5X. + * + * Copyright (C) 2021 Marvell + * Copyright (C) 2022 Allied Telesis Labs + */ +/* + * Device Tree file for Marvell Alleycat 5X development board + * This board file supports the B configuration of the board + */ + +/dts-v1/; + +#include "ac5-98dx35xx.dtsi" + +/ { + model = "Marvell RD-AC5X Board"; + compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5"; + + aliases { + serial0 = &uart0; + spiflash0 = &spiflash0; + gpio0 = &gpio0; + gpio1 = &gpio1; + ethernet0 = ð0; + ethernet1 = ð1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x2 0x00000000 0x0 0x40000000>; + }; + + usb1phy: usb-phy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +ð0 { + status = "okay"; + phy-handle = <&phy0>; +}; + +/* USB0 is a host USB */ +&usb0 { + status = "okay"; +}; + +/* USB1 is a peripheral USB */ +&usb1 { + status = "okay"; + phys = <&usb1phy>; + phy-names = "usb-phy"; + dr_mode = "peripheral"; +}; + +&spi0 { + status = "okay"; + + spiflash0: flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ + spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ + reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "spi_flash_part0"; + reg = <0x0 0x800000>; + }; + + parition@1 { + label = "spi_flash_part1"; + reg = <0x800000 0x700000>; + }; + + parition@2 { + label = "spi_flash_part2"; + reg = <0xF00000 0x100000>; + }; + }; +}; diff --git a/dts/src/arm64/marvell/ac5-98dx35xx.dtsi b/dts/src/arm64/marvell/ac5-98dx35xx.dtsi new file mode 100644 index 0000000000..2ab72f854b --- /dev/null +++ b/dts/src/arm64/marvell/ac5-98dx35xx.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For AC5X. + * + * Copyright (C) 2022 Allied Telesis Labs + */ + +#include "ac5-98dx25xx.dtsi" + +/ { + model = "Marvell AC5X SoC"; + compatible = "marvell,ac5x", "marvell,ac5"; +}; + +&cnm_clock { + clock-frequency = <325000000>; +}; diff --git a/dts/src/arm64/marvell/ac5x-rd-carrier-cn9131.dts b/dts/src/arm64/marvell/ac5x-rd-carrier-cn9131.dts new file mode 100644 index 0000000000..2a0b070000 --- /dev/null +++ b/dts/src/arm64/marvell/ac5x-rd-carrier-cn9131.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the AC5X RD Type 7 Com Express carrier board, + * Utilizing the CN913x COM Express CPU module board. + * This specific carrier board in this mode of operation (external) + * only maintains a PCIe link with the CPU module, + * which does not require any special DTS definitions. + * + * AC5X RD works here in external mode (switch selectable at the back of the + * board), and connect via an external cable a kit + * which would allow it to use an external CN9131 CPU COM Express module, + * mounted on top of an interposer kit. + * + * So in this case, once the switch is set to external mode as explained above, + * the AC5X RD becomes part of the carrier solution. + * + * When the board boots in the external CPU mode, the internal CPU is disabled, + * and only the switch portion of the SOC acts as a PCIe end-point, Hence there + * is no need to describe this internal (disabled CPU) in the device tree. + * + * There is no CPU booting in this mode on the carrier, only on the + * CN9131 COM Express CPU module. + * What runs the Linux is the CN9131 on the COM Express CPU module, + * And it accesses the switch end-point on the AC5X RD portion of the carrier + * via PCIe. + */ + +#include "cn9131-db-comexpress.dtsi" +#include "ac5x-rd-carrier.dtsi" + +/ { + model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module"; + compatible = "marvell,cn9131-ac5x-carrier", "marvell,rd-ac5x-carrier", + "marvell,cn9131-cpu-module", "marvell,cn9131", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x2 0x00000000>; + }; + +}; diff --git a/dts/src/arm64/marvell/ac5x-rd-carrier.dtsi b/dts/src/arm64/marvell/ac5x-rd-carrier.dtsi new file mode 100644 index 0000000000..f98629abb5 --- /dev/null +++ b/dts/src/arm64/marvell/ac5x-rd-carrier.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the AC5X RD Type 7 Com Express carrier board, + * This specific board in external mode (see below) only maintains + * a PCIe link with the COM Express CPU module, which does not + * require any special DTS definitions. + * + * AC5X RD can either work as you would expect, as a complete standalone + * box using the internal CPU, or you can move the switch on the back of + * the box to "external" mode, and connect via an external cable a kit + * which would allow it to use an external CPU COM Express module, + * mounted on top of an interposer kit. + * + * So in this case, once the switch is set to external mode as explained above, + * the AC5X RD becomes part of the carrier solution. + * This is a development/reference solution, not a full commercial solution, + * hence it was designed with the flexibility to be configured in different + * modes of operation. + * + * When the board boots in the external CPU mode, the internal CPU is disabled, + * and only the switch portion of the SOC acts as a PCIe end-point, Hence there + * is no need to describe this internal (disabled CPU) in the device tree. + * + * There is no CPU booting in this mode on the carrier, + * only on the COM Express CPU module. + */ + +/ { + model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board"; + compatible = "marvell,rd-ac5x-carrier"; + +}; diff --git a/dts/src/arm64/marvell/armada-3720-db.dts b/dts/src/arm64/marvell/armada-3720-db.dts index bd4e61d544..0cfb384920 100644 --- a/dts/src/arm64/marvell/armada-3720-db.dts +++ b/dts/src/arm64/marvell/armada-3720-db.dts @@ -18,7 +18,7 @@ / { model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3"; - compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710"; + compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3700"; chosen { stdout-path = "serial0:115200n8"; diff --git a/dts/src/arm64/marvell/armada-3720-eDPU.dts b/dts/src/arm64/marvell/armada-3720-eDPU.dts new file mode 100644 index 0000000000..d6d37a1f6f --- /dev/null +++ b/dts/src/arm64/marvell/armada-3720-eDPU.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "armada-3720-uDPU.dtsi" + +/ { + model = "Methode eDPU Board"; + compatible = "methode,edpu", "marvell,armada3720", "marvell,armada3710"; +}; + +ð0 { + phy-mode = "2500base-x"; +}; + +/* + * External MV88E6361 switch is only available on v2 of the board. + * U-Boot will enable the MDIO bus and switch nodes. + */ +&mdio { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&smi_pins>; + + /* Actual device is MV88E6361 */ + switch: switch@0 { + compatible = "marvell,mv88e6190"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + phy-mode = "2500base-x"; + managed = "in-band-status"; + ethernet = <ð0>; + }; + + port@9 { + reg = <9>; + label = "downlink"; + phy-mode = "2500base-x"; + managed = "in-band-status"; + }; + + port@a { + reg = <10>; + label = "uplink"; + phy-mode = "2500base-x"; + managed = "in-band-status"; + sfp = <&sfp_eth1>; + }; + }; + }; +}; diff --git a/dts/src/arm64/marvell/armada-3720-espressobin-emmc.dts b/dts/src/arm64/marvell/armada-3720-espressobin-emmc.dts index 5c4d8f3797..6715a19c14 100644 --- a/dts/src/arm64/marvell/armada-3720-espressobin-emmc.dts +++ b/dts/src/arm64/marvell/armada-3720-espressobin-emmc.dts @@ -18,7 +18,7 @@ / { model = "Globalscale Marvell ESPRESSOBin Board (eMMC)"; compatible = "globalscale,espressobin-emmc", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3710"; + "marvell,armada3720", "marvell,armada3700"; }; &sdhci0 { diff --git a/dts/src/arm64/marvell/armada-3720-espressobin-ultra.dts b/dts/src/arm64/marvell/armada-3720-espressobin-ultra.dts index 070725b81b..870bb380a4 100644 --- a/dts/src/arm64/marvell/armada-3720-espressobin-ultra.dts +++ b/dts/src/arm64/marvell/armada-3720-espressobin-ultra.dts @@ -12,8 +12,8 @@ / { model = "Globalscale Marvell ESPRESSOBin Ultra Board"; - compatible = "globalscale,espressobin-ultra", "marvell,armada3720", - "marvell,armada3710"; + compatible = "globalscale,espressobin-ultra", "globalscale,espressobin", + "marvell,armada3720", "marvell,armada3700"; aliases { /* ethernet1 is WAN port */ @@ -24,6 +24,8 @@ ethernet5 = &switch0port4; }; + /delete-node/ regulator; + reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; regulator-name = "usb3-vbus"; @@ -66,6 +68,7 @@ }; &sdhci1 { + /delete-property/ vqmmc-supply; status = "disabled"; }; @@ -123,32 +126,32 @@ reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>; - ports { - switch0port1: port@1 { + ethernet-ports { + switch0port1: ethernet-port@1 { reg = <1>; label = "lan0"; phy-handle = <&switch0phy0>; }; - switch0port2: port@2 { + switch0port2: ethernet-port@2 { reg = <2>; label = "lan1"; phy-handle = <&switch0phy1>; }; - switch0port3: port@3 { + switch0port3: ethernet-port@3 { reg = <3>; label = "lan2"; phy-handle = <&switch0phy2>; }; - switch0port4: port@4 { + switch0port4: ethernet-port@4 { reg = <4>; label = "lan3"; phy-handle = <&switch0phy3>; }; - switch0port5: port@5 { + switch0port5: ethernet-port@5 { reg = <5>; label = "wan"; phy-handle = <&extphy>; @@ -157,7 +160,7 @@ }; mdio { - switch0phy3: switch0phy3@14 { + switch0phy3: ethernet-phy@14 { reg = <0x14>; }; }; diff --git a/dts/src/arm64/marvell/armada-3720-espressobin-v7-emmc.dts b/dts/src/arm64/marvell/armada-3720-espressobin-v7-emmc.dts index 75401eab4d..2a8aa3901a 100644 --- a/dts/src/arm64/marvell/armada-3720-espressobin-v7-emmc.dts +++ b/dts/src/arm64/marvell/armada-3720-espressobin-v7-emmc.dts @@ -19,7 +19,7 @@ model = "Globalscale Marvell ESPRESSOBin Board V7 (eMMC)"; compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7", "globalscale,espressobin", "marvell,armada3720", - "marvell,armada3710"; + "marvell,armada3700"; aliases { /* ethernet1 is wan port */ diff --git a/dts/src/arm64/marvell/armada-3720-espressobin-v7.dts b/dts/src/arm64/marvell/armada-3720-espressobin-v7.dts index 48a7f50fb4..b03af87611 100644 --- a/dts/src/arm64/marvell/armada-3720-espressobin-v7.dts +++ b/dts/src/arm64/marvell/armada-3720-espressobin-v7.dts @@ -18,7 +18,7 @@ / { model = "Globalscale Marvell ESPRESSOBin Board V7"; compatible = "globalscale,espressobin-v7", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3710"; + "marvell,armada3720", "marvell,armada3700"; aliases { /* ethernet1 is wan port */ diff --git a/dts/src/arm64/marvell/armada-3720-espressobin.dts b/dts/src/arm64/marvell/armada-3720-espressobin.dts index 1542d836c0..c5a834b33b 100644 --- a/dts/src/arm64/marvell/armada-3720-espressobin.dts +++ b/dts/src/arm64/marvell/armada-3720-espressobin.dts @@ -16,5 +16,5 @@ / { model = "Globalscale Marvell ESPRESSOBin Board"; - compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710"; + compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3700"; }; diff --git a/dts/src/arm64/marvell/armada-3720-espressobin.dtsi b/dts/src/arm64/marvell/armada-3720-espressobin.dtsi index 5fc613d241..fed2dcecb3 100644 --- a/dts/src/arm64/marvell/armada-3720-espressobin.dtsi +++ b/dts/src/arm64/marvell/armada-3720-espressobin.dtsi @@ -13,7 +13,7 @@ / { aliases { ethernet0 = ð0; - /* for dsa slave device */ + /* for DSA user port device */ ethernet1 = &switch0port1; ethernet2 = &switch0port2; ethernet3 = &switch0port3; @@ -145,19 +145,17 @@ }; &mdio { - switch0: switch0@1 { + switch0: ethernet-switch@1 { compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; reg = <1>; dsa,member = <0 0>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - switch0port0: port@0 { + switch0port0: ethernet-port@0 { reg = <0>; label = "cpu"; ethernet = <ð0>; @@ -168,19 +166,19 @@ }; }; - switch0port1: port@1 { + switch0port1: ethernet-port@1 { reg = <1>; label = "wan"; phy-handle = <&switch0phy0>; }; - switch0port2: port@2 { + switch0port2: ethernet-port@2 { reg = <2>; label = "lan0"; phy-handle = <&switch0phy1>; }; - switch0port3: port@3 { + switch0port3: ethernet-port@3 { reg = <3>; label = "lan1"; phy-handle = <&switch0phy2>; @@ -192,13 +190,13 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy0: switch0phy0@11 { + switch0phy0: ethernet-phy@11 { reg = <0x11>; }; - switch0phy1: switch0phy1@12 { + switch0phy1: ethernet-phy@12 { reg = <0x12>; }; - switch0phy2: switch0phy2@13 { + switch0phy2: ethernet-phy@13 { reg = <0x13>; }; }; diff --git a/dts/src/arm64/marvell/armada-3720-gl-mv1000.dts b/dts/src/arm64/marvell/armada-3720-gl-mv1000.dts new file mode 100644 index 0000000000..63fbc83521 --- /dev/null +++ b/dts/src/arm64/marvell/armada-3720-gl-mv1000.dts @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "armada-372x.dtsi" + +/ { + model = "GL.iNet GL-MV1000"; + compatible = "glinet,gl-mv1000", "marvell,armada3720"; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; + + vcc_sd_reg1: regulator { + compatible = "regulator-gpio"; + regulator-name = "vcc_sd1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + gpios-states = <0>; + states = <1800000 0x1 + 3300000 0x0>; + enable-active-high; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; + }; + + switch { + label = "switch"; + linux,code = <BTN_0>; + gpios = <&gpiosb 22 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + vpn { + label = "green:vpn"; + gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; + }; + + wan { + label = "green:wan"; + gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; + }; + + led_power: power { + label = "green:power"; + gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <104000000>; + m25p,fast-read; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "firmware"; + reg = <0 0xf0000>; + }; + + partition@f0000 { + label = "u-boot-env"; + reg = <0xf0000 0x8000>; + }; + + factory: partition@f8000 { + label = "factory"; + reg = <0xf8000 0x8000>; + read-only; + }; + + partition@100000 { + label = "dtb"; + reg = <0x100000 0x10000>; + read-only; + }; + + partition@110000 { + label = "rescue"; + reg = <0x110000 0x1000000>; + }; + }; + }; +}; + +&sdhci1 { + wp-inverted; + bus-width = <4>; + cd-gpios = <&gpionb 17 GPIO_ACTIVE_LOW>; + marvell,pad-type = "sd"; + no-1-8-v; + vqmmc-supply = <&vcc_sd_reg1>; + status = "okay"; +}; + +&sdhci0 { + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + non-removable; + no-sd; + no-sdio; + marvell,pad-type = "fixed-1-8v"; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&mdio { + switch0: ethernet-switch@1 { + compatible = "marvell,mv88e6085"; + reg = <1>; + + dsa,member = <0 0>; + + ports: ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-port@0 { + reg = <0>; + label = "cpu"; + ethernet = <ð0>; + }; + + ethernet-port@1 { + reg = <1>; + label = "wan"; + phy-handle = <&switch0phy0>; + }; + + ethernet-port@2 { + reg = <2>; + label = "lan0"; + phy-handle = <&switch0phy1>; + + nvmem-cells = <&macaddr_factory_6>; + nvmem-cell-names = "mac-address"; + }; + + ethernet-port@3 { + reg = <3>; + label = "lan1"; + phy-handle = <&switch0phy2>; + + nvmem-cells = <&macaddr_factory_6>; + nvmem-cell-names = "mac-address"; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch0phy0: ethernet-phy@11 { + reg = <0x11>; + }; + switch0phy1: ethernet-phy@12 { + reg = <0x12>; + }; + switch0phy2: ethernet-phy@13 { + reg = <0x13>; + }; + }; + }; +}; + +ð0 { + nvmem-cells = <&macaddr_factory_0>; + nvmem-cell-names = "mac-address"; + phy-mode = "rgmii-id"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&factory { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_factory_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; diff --git a/dts/src/arm64/marvell/armada-3720-turris-mox.dts b/dts/src/arm64/marvell/armada-3720-turris-mox.dts index caf9c8529f..f1a9f22343 100644 --- a/dts/src/arm64/marvell/armada-3720-turris-mox.dts +++ b/dts/src/arm64/marvell/armada-3720-turris-mox.dts @@ -14,7 +14,7 @@ / { model = "CZ.NIC Turris Mox Board"; compatible = "cznic,turris-mox", "marvell,armada3720", - "marvell,armada3710"; + "marvell,armada3700"; aliases { spi0 = &spi0; @@ -35,7 +35,7 @@ leds { compatible = "gpio-leds"; - red { + led { label = "mox:red:activity"; gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; @@ -45,7 +45,7 @@ gpio-keys { compatible = "gpio-keys"; - reset { + key-reset { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; @@ -100,11 +100,11 @@ sfp: sfp { compatible = "sff,sfp"; i2c-bus = <&i2c0>; - los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; - rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; + los-gpios = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; + rate-select0-gpios = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; maximum-power-milliwatt = <3000>; /* enabled by U-Boot if SFP module is present */ @@ -125,9 +125,12 @@ /delete-property/ mrvl,i2c-fast-mode; status = "okay"; + /* MCP7940MT-I/MNY RTC */ rtc@6f { compatible = "microchip,mcp7940x"; reg = <0x6f>; + interrupt-parent = <&gpiosb>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO2_5 */ }; }; @@ -136,6 +139,7 @@ pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; status = "okay"; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; + slot-power-limit-milliwatt = <10000>; /* * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and @@ -300,9 +304,15 @@ reg = <1>; }; - /* switch nodes are enabled by U-Boot if modules are present */ + /* + * NOTE: switch nodes are enabled by U-Boot if modules are present + * DO NOT change this node name (switch0@10) even if it is not following + * conventions! Deployed U-Boot binaries are explicitly looking for + * this node in order to augment the device tree! + * Also do not touch the "ports" or "port@n" nodes. These are also ABI. + */ switch0@10 { - compatible = "marvell,mv88e6190"; + compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190"; reg = <0x10>; dsa,member = <0 0>; interrupt-parent = <&moxtet>; @@ -313,35 +323,35 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy1: switch0phy1@1 { + switch0phy1: ethernet-phy@1 { reg = <0x1>; }; - switch0phy2: switch0phy2@2 { + switch0phy2: ethernet-phy@2 { reg = <0x2>; }; - switch0phy3: switch0phy3@3 { + switch0phy3: ethernet-phy@3 { reg = <0x3>; }; - switch0phy4: switch0phy4@4 { + switch0phy4: ethernet-phy@4 { reg = <0x4>; }; - switch0phy5: switch0phy5@5 { + switch0phy5: ethernet-phy@5 { reg = <0x5>; }; - switch0phy6: switch0phy6@6 { + switch0phy6: ethernet-phy@6 { reg = <0x6>; }; - switch0phy7: switch0phy7@7 { + switch0phy7: ethernet-phy@7 { reg = <0x7>; }; - switch0phy8: switch0phy8@8 { + switch0phy8: ethernet-phy@8 { reg = <0x8>; }; }; @@ -426,8 +436,9 @@ }; }; + /* NOTE: this node name is ABI, don't change it! */ switch0@2 { - compatible = "marvell,mv88e6085"; + compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085"; reg = <0x2>; dsa,member = <0 0>; interrupt-parent = <&moxtet>; @@ -438,19 +449,19 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy1_topaz: switch0phy1@11 { + switch0phy1_topaz: ethernet-phy@11 { reg = <0x11>; }; - switch0phy2_topaz: switch0phy2@12 { + switch0phy2_topaz: ethernet-phy@12 { reg = <0x12>; }; - switch0phy3_topaz: switch0phy3@13 { + switch0phy3_topaz: ethernet-phy@13 { reg = <0x13>; }; - switch0phy4_topaz: switch0phy4@14 { + switch0phy4_topaz: ethernet-phy@14 { reg = <0x14>; }; }; @@ -493,8 +504,9 @@ }; }; + /* NOTE: this node name is ABI, don't change it! */ switch1@11 { - compatible = "marvell,mv88e6190"; + compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190"; reg = <0x11>; dsa,member = <0 1>; interrupt-parent = <&moxtet>; @@ -505,35 +517,35 @@ #address-cells = <1>; #size-cells = <0>; - switch1phy1: switch1phy1@1 { + switch1phy1: ethernet-phy@1 { reg = <0x1>; }; - switch1phy2: switch1phy2@2 { + switch1phy2: ethernet-phy@2 { reg = <0x2>; }; - switch1phy3: switch1phy3@3 { + switch1phy3: ethernet-phy@3 { reg = <0x3>; }; - switch1phy4: switch1phy4@4 { + switch1phy4: ethernet-phy@4 { reg = <0x4>; }; - switch1phy5: switch1phy5@5 { + switch1phy5: ethernet-phy@5 { reg = <0x5>; }; - switch1phy6: switch1phy6@6 { + switch1phy6: ethernet-phy@6 { reg = <0x6>; }; - switch1phy7: switch1phy7@7 { + switch1phy7: ethernet-phy@7 { reg = <0x7>; }; - switch1phy8: switch1phy8@8 { + switch1phy8: ethernet-phy@8 { reg = <0x8>; }; }; @@ -618,8 +630,9 @@ }; }; + /* NOTE: this node name is ABI, don't change it! */ switch1@2 { - compatible = "marvell,mv88e6085"; + compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085"; reg = <0x2>; dsa,member = <0 1>; interrupt-parent = <&moxtet>; @@ -630,19 +643,19 @@ #address-cells = <1>; #size-cells = <0>; - switch1phy1_topaz: switch1phy1@11 { + switch1phy1_topaz: ethernet-phy@11 { reg = <0x11>; }; - switch1phy2_topaz: switch1phy2@12 { + switch1phy2_topaz: ethernet-phy@12 { reg = <0x12>; }; - switch1phy3_topaz: switch1phy3@13 { + switch1phy3_topaz: ethernet-phy@13 { reg = <0x13>; }; - switch1phy4_topaz: switch1phy4@14 { + switch1phy4_topaz: ethernet-phy@14 { reg = <0x14>; }; }; @@ -685,8 +698,9 @@ }; }; + /* NOTE: this node name is ABI, don't change it! */ switch2@12 { - compatible = "marvell,mv88e6190"; + compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190"; reg = <0x12>; dsa,member = <0 2>; interrupt-parent = <&moxtet>; @@ -697,35 +711,35 @@ #address-cells = <1>; #size-cells = <0>; - switch2phy1: switch2phy1@1 { + switch2phy1: ethernet-phy@1 { reg = <0x1>; }; - switch2phy2: switch2phy2@2 { + switch2phy2: ethernet-phy@2 { reg = <0x2>; }; - switch2phy3: switch2phy3@3 { + switch2phy3: ethernet-phy@3 { reg = <0x3>; }; - switch2phy4: switch2phy4@4 { + switch2phy4: ethernet-phy@4 { reg = <0x4>; }; - switch2phy5: switch2phy5@5 { + switch2phy5: ethernet-phy@5 { reg = <0x5>; }; - switch2phy6: switch2phy6@6 { + switch2phy6: ethernet-phy@6 { reg = <0x6>; }; - switch2phy7: switch2phy7@7 { + switch2phy7: ethernet-phy@7 { reg = <0x7>; }; - switch2phy8: switch2phy8@8 { + switch2phy8: ethernet-phy@8 { reg = <0x8>; }; }; @@ -801,8 +815,9 @@ }; }; + /* NOTE: this node name is ABI, don't change it! */ switch2@2 { - compatible = "marvell,mv88e6085"; + compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085"; reg = <0x2>; dsa,member = <0 2>; interrupt-parent = <&moxtet>; @@ -813,19 +828,19 @@ #address-cells = <1>; #size-cells = <0>; - switch2phy1_topaz: switch2phy1@11 { + switch2phy1_topaz: ethernet-phy@11 { reg = <0x11>; }; - switch2phy2_topaz: switch2phy2@12 { + switch2phy2_topaz: ethernet-phy@12 { reg = <0x12>; }; - switch2phy3_topaz: switch2phy3@13 { + switch2phy3_topaz: ethernet-phy@13 { reg = <0x13>; }; - switch2phy4_topaz: switch2phy4@14 { + switch2phy4_topaz: ethernet-phy@14 { reg = <0x14>; }; }; diff --git a/dts/src/arm64/marvell/armada-3720-uDPU.dts b/dts/src/arm64/marvell/armada-3720-uDPU.dts index a35317d24d..c76eceabd3 100644 --- a/dts/src/arm64/marvell/armada-3720-uDPU.dts +++ b/dts/src/arm64/marvell/armada-3720-uDPU.dts @@ -1,125 +1,22 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device tree for the uDPU board. - * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3) - * Copyright (C) 2016 Marvell - * Copyright (C) 2019 Methode Electronics - * Copyright (C) 2019 Telus - * - * Vladimir Vid <vladimir.vid@sartura.hr> - */ /dts-v1/; -#include <dt-bindings/gpio/gpio.h> -#include "armada-372x.dtsi" +#include "armada-3720-uDPU.dtsi" / { model = "Methode uDPU Board"; - compatible = "methode,udpu", "marvell,armada3720"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x20000000>; - }; - - leds { - pinctrl-names = "default"; - compatible = "gpio-leds"; - - power1 { - label = "udpu:green:power"; - gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; - }; - - power2 { - label = "udpu:red:power"; - gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; - }; - - network1 { - label = "udpu:green:network"; - gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; - }; - - network2 { - label = "udpu:red:network"; - gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; - }; - - alarm1 { - label = "udpu:green:alarm"; - gpios = <&gpionb 15 GPIO_ACTIVE_LOW>; - }; - - alarm2 { - label = "udpu:red:alarm"; - gpios = <&gpionb 16 GPIO_ACTIVE_LOW>; - }; - }; + compatible = "methode,udpu", "marvell,armada3720", "marvell,armada3710"; sfp_eth0: sfp-eth0 { compatible = "sff,sfp"; i2c-bus = <&i2c0>; - los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>; + los-gpios = <&gpiosb 2 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&gpiosb 4 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&gpiosb 5 GPIO_ACTIVE_HIGH>; maximum-power-milliwatt = <3000>; }; - - sfp_eth1: sfp-eth1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; -}; - -&sdhci0 { - status = "okay"; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,pad-type = "fixed-1-8v"; - non-removable; - no-sd; - no-sdio; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_quad_pins>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <54000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "firmware"; - reg = <0x0 0x180000>; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x10000>; - }; - }; - }; }; &pinctrl_nb { @@ -127,11 +24,6 @@ groups = "i2c1"; function = "gpio"; }; - - i2c2_recovery_pins: i2c2-recovery-pins { - groups = "i2c2"; - function = "gpio"; - }; }; &i2c0 { @@ -144,50 +36,7 @@ sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; -&i2c1 { - status = "okay"; - pinctrl-names = "default", "recovery"; - pinctrl-0 = <&i2c2_pins>; - pinctrl-1 = <&i2c2_recovery_pins>; - /delete-property/mrvl,i2c-fast-mode; - scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - nct375@48 { - status = "okay"; - compatible = "ti,tmp75c"; - reg = <0x48>; - }; - - nct375@49 { - status = "okay"; - compatible = "ti,tmp75c"; - reg = <0x49>; - }; -}; - ð0 { phy-mode = "sgmii"; - status = "okay"; - managed = "in-band-status"; - phys = <&comphy1 0>; sfp = <&sfp_eth0>; }; - -ð1 { - phy-mode = "sgmii"; - status = "okay"; - managed = "in-band-status"; - phys = <&comphy0 1>; - sfp = <&sfp_eth1>; -}; - -&usb3 { - status = "okay"; - phys = <&usb2_utmi_otg_phy>; - phy-names = "usb2-utmi-otg-phy"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/dts/src/arm64/marvell/armada-3720-uDPU.dtsi b/dts/src/arm64/marvell/armada-3720-uDPU.dtsi new file mode 100644 index 0000000000..3a9b690718 --- /dev/null +++ b/dts/src/arm64/marvell/armada-3720-uDPU.dtsi @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree for the uDPU board. + * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3) + * Copyright (C) 2016 Marvell + * Copyright (C) 2019 Methode Electronics + * Copyright (C) 2019 Telus + * + * Vladimir Vid <vladimir.vid@sartura.hr> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "armada-372x.dtsi" + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-power1 { + label = "udpu:green:power"; + gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; + }; + + led-power2 { + label = "udpu:red:power"; + gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; + }; + + led-network1 { + label = "udpu:green:network"; + gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; + }; + + led-network2 { + label = "udpu:red:network"; + gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; + }; + + led-alarm1 { + label = "udpu:green:alarm"; + gpios = <&gpionb 15 GPIO_ACTIVE_LOW>; + }; + + led-alarm2 { + label = "udpu:red:alarm"; + gpios = <&gpionb 16 GPIO_ACTIVE_LOW>; + }; + }; + + sfp_eth1: sfp-eth1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpios = <&gpiosb 7 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&gpiosb 8 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&gpiosb 9 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&gpiosb 10 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; +}; + +&sdhci0 { + status = "okay"; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + marvell,pad-type = "fixed-1-8v"; + non-removable; + no-sd; + no-sdio; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi_quad_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <54000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "firmware"; + reg = <0x0 0x180000>; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x10000>; + }; + }; + }; +}; + +&pinctrl_nb { + i2c2_recovery_pins: i2c2-recovery-pins { + groups = "i2c2"; + function = "gpio"; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default", "recovery"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&i2c2_recovery_pins>; + /delete-property/mrvl,i2c-fast-mode; + scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + temp-sensor@48 { + compatible = "ti,tmp75c"; + reg = <0x48>; + }; + + temp-sensor@49 { + compatible = "ti,tmp75c"; + reg = <0x49>; + }; +}; + +ð0 { + status = "okay"; + managed = "in-band-status"; + phys = <&comphy1 0>; +}; + +ð1 { + phy-mode = "sgmii"; + status = "okay"; + managed = "in-band-status"; + phys = <&comphy0 1>; + sfp = <&sfp_eth1>; +}; + +&usb3 { + status = "okay"; + phys = <&usb2_utmi_otg_phy>; + phy-names = "usb2-utmi-otg-phy"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/src/arm64/marvell/armada-372x.dtsi b/dts/src/arm64/marvell/armada-372x.dtsi index 5ce55bdbb9..02ae1e1532 100644 --- a/dts/src/arm64/marvell/armada-372x.dtsi +++ b/dts/src/arm64/marvell/armada-372x.dtsi @@ -13,7 +13,7 @@ / { model = "Marvell Armada 3720 SoC"; - compatible = "marvell,armada3720", "marvell,armada3710"; + compatible = "marvell,armada3720", "marvell,armada3700"; cpus { cpu1: cpu@1 { diff --git a/dts/src/arm64/marvell/armada-37xx.dtsi b/dts/src/arm64/marvell/armada-37xx.dtsi index df152c7227..e300145ad1 100644 --- a/dts/src/arm64/marvell/armada-37xx.dtsi +++ b/dts/src/arm64/marvell/armada-37xx.dtsi @@ -35,6 +35,11 @@ reg = <0 0x4000000 0 0x200000>; no-map; }; + + tee@4400000 { + reg = <0 0x4400000 0 0x1000000>; + no-map; + }; }; cpus { diff --git a/dts/src/arm64/marvell/armada-7040-mochabin.dts b/dts/src/arm64/marvell/armada-7040-mochabin.dts index 39a8e5e99d..40b7ee7ead 100644 --- a/dts/src/arm64/marvell/armada-7040-mochabin.dts +++ b/dts/src/arm64/marvell/armada-7040-mochabin.dts @@ -34,20 +34,20 @@ sfp_eth0: sfp-eth0 { compatible = "sff,sfp"; i2c-bus = <&cp0_i2c1>; - los-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sfp_gpio 2 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>; }; /* SFP 1G */ sfp_eth2: sfp-eth2 { compatible = "sff,sfp"; i2c-bus = <&cp0_i2c0>; - los-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>; + los-gpios = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sfp_gpio 6 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>; }; }; @@ -149,7 +149,7 @@ }; /* SPI-NOR */ -&cp0_spi1{ +&cp0_spi1 { status = "okay"; pinctrl-names = "default"; @@ -301,10 +301,8 @@ }; /* 88E6141 Topaz switch */ - switch: switch@3 { + switch: ethernet-switch@3 { compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; reg = <3>; pinctrl-names = "default"; @@ -314,35 +312,35 @@ interrupt-parent = <&cp0_gpio1>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - swport1: port@1 { + swport1: ethernet-port@1 { reg = <1>; label = "lan0"; phy-handle = <&swphy1>; }; - swport2: port@2 { + swport2: ethernet-port@2 { reg = <2>; label = "lan1"; phy-handle = <&swphy2>; }; - swport3: port@3 { + swport3: ethernet-port@3 { reg = <3>; label = "lan2"; phy-handle = <&swphy3>; }; - swport4: port@4 { + swport4: ethernet-port@4 { reg = <4>; label = "lan3"; phy-handle = <&swphy4>; }; - port@5 { + ethernet-port@5 { reg = <5>; label = "cpu"; ethernet = <&cp0_eth1>; @@ -355,19 +353,19 @@ #address-cells = <1>; #size-cells = <0>; - swphy1: swphy1@17 { + swphy1: ethernet-phy@17 { reg = <17>; }; - swphy2: swphy2@18 { + swphy2: ethernet-phy@18 { reg = <18>; }; - swphy3: swphy3@19 { + swphy3: ethernet-phy@19 { reg = <19>; }; - swphy4: swphy4@20 { + swphy4: ethernet-phy@20 { reg = <20>; }; }; @@ -455,4 +453,5 @@ phys = <&cp0_comphy5 2>; phy-names = "cp0-pcie2-x1-phy"; reset-gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>; + ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x8000000>; }; diff --git a/dts/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts b/dts/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts index 871f84b4a6..67892f0d28 100644 --- a/dts/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts +++ b/dts/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts @@ -64,8 +64,8 @@ sfp_cp0_eth0: sfp-cp0-eth0 { compatible = "sff,sfp"; i2c-bus = <&cp0_i2c1>; - mod-def0-gpio = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>; maximum-power-milliwatt = <2000>; @@ -94,7 +94,7 @@ pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>; pinctrl-names = "default"; - button_0 { + button-0 { /* The rear button */ label = "Rear Button"; gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>; @@ -102,7 +102,7 @@ linux,code = <BTN_0>; }; - button_1 { + button-1 { /* The wps button */ label = "WPS Button"; gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>; @@ -497,42 +497,42 @@ reset-deassert-us = <10000>; }; - switch0: switch0@4 { + switch0: ethernet-switch@4 { compatible = "marvell,mv88e6085"; reg = <4>; pinctrl-names = "default"; pinctrl-0 = <&cp1_switch_reset_pins>; reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan2"; phy-handle = <&switch0phy0>; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan1"; phy-handle = <&switch0phy1>; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan4"; phy-handle = <&switch0phy2>; }; - port@4 { + ethernet-port@4 { reg = <4>; label = "lan3"; phy-handle = <&switch0phy3>; }; - port@5 { + ethernet-port@5 { reg = <5>; label = "cpu"; ethernet = <&cp1_eth2>; @@ -545,19 +545,19 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy0: switch0phy0@11 { + switch0phy0: ethernet-phy@11 { reg = <0x11>; }; - switch0phy1: switch0phy1@12 { + switch0phy1: ethernet-phy@12 { reg = <0x12>; }; - switch0phy2: switch0phy2@13 { + switch0phy2: ethernet-phy@13 { reg = <0x13>; }; - switch0phy3: switch0phy3@14 { + switch0phy3: ethernet-phy@14 { reg = <0x14>; }; }; diff --git a/dts/src/arm64/marvell/armada-8040-mcbin.dtsi b/dts/src/arm64/marvell/armada-8040-mcbin.dtsi index 779cf167c3..c864df9ec8 100644 --- a/dts/src/arm64/marvell/armada-8040-mcbin.dtsi +++ b/dts/src/arm64/marvell/armada-8040-mcbin.dtsi @@ -65,10 +65,10 @@ /* CON15,16 - CPM lane 4 */ compatible = "sff,sfp"; i2c-bus = <&sfpp0_i2c>; - los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; + los-gpios = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cp1_sfpp0_pins>; maximum-power-milliwatt = <2000>; @@ -78,10 +78,10 @@ /* CON17,18 - CPS lane 4 */ compatible = "sff,sfp"; i2c-bus = <&sfpp1_i2c>; - los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; + los-gpios = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>; maximum-power-milliwatt = <2000>; @@ -91,10 +91,10 @@ /* CON13,14 - CPS lane 5 */ compatible = "sff,sfp"; i2c-bus = <&sfp_1g_i2c>; - los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; + los-gpios = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; maximum-power-milliwatt = <2000>; @@ -135,7 +135,7 @@ pinctrl-0 = <&cp0_i2c1_pins>; status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/marvell/armada-8040-puzzle-m801.dts b/dts/src/arm64/marvell/armada-8040-puzzle-m801.dts index 74bed79e4f..42a60f3dd5 100644 --- a/dts/src/arm64/marvell/armada-8040-puzzle-m801.dts +++ b/dts/src/arm64/marvell/armada-8040-puzzle-m801.dts @@ -67,20 +67,20 @@ sfp_cp0_eth0: sfp-cp0-eth0 { compatible = "sff,sfp"; i2c-bus = <&sfpplus0_i2c>; - los-gpio = <&sfpplus_gpio 11 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&sfpplus_gpio 10 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&sfpplus_gpio 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&sfpplus_gpio 8 GPIO_ACTIVE_HIGH>; + los-gpios = <&sfpplus_gpio 11 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sfpplus_gpio 10 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&sfpplus_gpio 9 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&sfpplus_gpio 8 GPIO_ACTIVE_HIGH>; maximum-power-milliwatt = <3000>; }; sfp_cp1_eth0: sfp-cp1-eth0 { compatible = "sff,sfp"; i2c-bus = <&sfpplus1_i2c>; - los-gpio = <&sfpplus_gpio 3 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&sfpplus_gpio 2 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&sfpplus_gpio 1 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&sfpplus_gpio 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sfpplus_gpio 3 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sfpplus_gpio 2 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&sfpplus_gpio 1 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&sfpplus_gpio 0 GPIO_ACTIVE_HIGH>; maximum-power-milliwatt = <3000>; }; @@ -285,7 +285,7 @@ pinctrl-0 = <&cp0_i2c1_pins>; status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/marvell/armada-ap806-dual.dtsi b/dts/src/arm64/marvell/armada-ap806-dual.dtsi index fcab5173fe..3ed6fba1f4 100644 --- a/dts/src/arm64/marvell/armada-ap806-dual.dtsi +++ b/dts/src/arm64/marvell/armada-ap806-dual.dtsi @@ -51,6 +51,8 @@ cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; + cache-unified; }; }; diff --git a/dts/src/arm64/marvell/armada-ap806-quad.dtsi b/dts/src/arm64/marvell/armada-ap806-quad.dtsi index 3db427122f..cf6a96ddcf 100644 --- a/dts/src/arm64/marvell/armada-ap806-quad.dtsi +++ b/dts/src/arm64/marvell/armada-ap806-quad.dtsi @@ -81,6 +81,8 @@ cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; + cache-unified; }; l2_1: l2-cache1 { @@ -88,6 +90,8 @@ cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; + cache-unified; }; }; }; diff --git a/dts/src/arm64/marvell/armada-ap807-quad.dtsi b/dts/src/arm64/marvell/armada-ap807-quad.dtsi index 68782f161f..8848238f95 100644 --- a/dts/src/arm64/marvell/armada-ap807-quad.dtsi +++ b/dts/src/arm64/marvell/armada-ap807-quad.dtsi @@ -81,6 +81,8 @@ cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; + cache-unified; }; l2_1: l2-cache1 { @@ -88,6 +90,8 @@ cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; + cache-unified; }; }; }; diff --git a/dts/src/arm64/marvell/armada-ap80x.dtsi b/dts/src/arm64/marvell/armada-ap80x.dtsi index a06a0a889c..7ec7c789d8 100644 --- a/dts/src/arm64/marvell/armada-ap80x.dtsi +++ b/dts/src/arm64/marvell/armada-ap80x.dtsi @@ -41,6 +41,11 @@ reg = <0x0 0x4000000 0x0 0x200000>; no-map; }; + + tee@4400000 { + reg = <0 0x4400000 0 0x1000000>; + no-map; + }; }; AP_NAME { @@ -133,7 +138,6 @@ odmi: odmi@300000 { compatible = "marvell,odmi-controller"; - interrupt-controller; msi-controller; marvell,odmi-frames = <4>; reg = <0x300000 0x4000>, @@ -312,7 +316,7 @@ * first one that will have a critical trip point will be chosen. */ thermal-zones { - ap_thermal_ic: ap-thermal-ic { + ap_thermal_ic: ap-ic-thermal { polling-delay-passive = <0>; /* Interrupt driven */ polling-delay = <0>; /* Interrupt driven */ @@ -329,7 +333,7 @@ cooling-maps { }; }; - ap_thermal_cpu0: ap-thermal-cpu0 { + ap_thermal_cpu0: ap-cpu0-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -362,7 +366,7 @@ }; }; - ap_thermal_cpu1: ap-thermal-cpu1 { + ap_thermal_cpu1: ap-cpu1-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -395,7 +399,7 @@ }; }; - ap_thermal_cpu2: ap-thermal-cpu2 { + ap_thermal_cpu2: ap-cpu2-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -428,7 +432,7 @@ }; }; - ap_thermal_cpu3: ap-thermal-cpu3 { + ap_thermal_cpu3: ap-cpu3-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; diff --git a/dts/src/arm64/marvell/armada-ap810-ap0.dtsi b/dts/src/arm64/marvell/armada-ap810-ap0.dtsi index 8107d120a8..2f9ab6b4a2 100644 --- a/dts/src/arm64/marvell/armada-ap810-ap0.dtsi +++ b/dts/src/arm64/marvell/armada-ap810-ap0.dtsi @@ -54,7 +54,7 @@ <0x00d0000 0x1000>, /* GICH */ <0x00e0000 0x2000>; /* GICV */ - gic_its_ap0: interrupt-controller@3040000 { + gic_its_ap0: msi-controller@3040000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; diff --git a/dts/src/arm64/marvell/armada-cp11x.dtsi b/dts/src/arm64/marvell/armada-cp11x.dtsi index d6c0990a26..4ec1aae0a3 100644 --- a/dts/src/arm64/marvell/armada-cp11x.dtsi +++ b/dts/src/arm64/marvell/armada-cp11x.dtsi @@ -25,7 +25,7 @@ * The cooling maps are empty as there are no cooling devices. */ thermal-zones { - CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) { + CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) { polling-delay-passive = <0>; /* Interrupt driven */ polling-delay = <0>; /* Interrupt driven */ @@ -58,6 +58,8 @@ ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>; CP11X_LABEL(ethernet): ethernet@0 { + #address-cells = <1>; + #size-cells = <0>; compatible = "marvell,armada-7k-pp22"; reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>; clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>, @@ -69,7 +71,7 @@ status = "disabled"; dma-coherent; - CP11X_LABEL(eth0): eth0 { + CP11X_LABEL(eth0): ethernet-port@0 { interrupts = <39 IRQ_TYPE_LEVEL_HIGH>, <43 IRQ_TYPE_LEVEL_HIGH>, <47 IRQ_TYPE_LEVEL_HIGH>, @@ -83,12 +85,13 @@ interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4", "hif5", "hif6", "hif7", "hif8", "link"; - port-id = <0>; + reg = <0>; + port-id = <0>; /* For backward compatibility. */ gop-port-id = <0>; status = "disabled"; }; - CP11X_LABEL(eth1): eth1 { + CP11X_LABEL(eth1): ethernet-port@1 { interrupts = <40 IRQ_TYPE_LEVEL_HIGH>, <44 IRQ_TYPE_LEVEL_HIGH>, <48 IRQ_TYPE_LEVEL_HIGH>, @@ -102,12 +105,13 @@ interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4", "hif5", "hif6", "hif7", "hif8", "link"; - port-id = <1>; + reg = <1>; + port-id = <1>; /* For backward compatibility. */ gop-port-id = <2>; status = "disabled"; }; - CP11X_LABEL(eth2): eth2 { + CP11X_LABEL(eth2): ethernet-port@2 { interrupts = <41 IRQ_TYPE_LEVEL_HIGH>, <45 IRQ_TYPE_LEVEL_HIGH>, <49 IRQ_TYPE_LEVEL_HIGH>, @@ -121,7 +125,8 @@ interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4", "hif5", "hif6", "hif7", "hif8", "link"; - port-id = <2>; + reg = <2>; + port-id = <2>; /* For backward compatibility. */ gop-port-id = <3>; status = "disabled"; }; @@ -463,7 +468,7 @@ status = "disabled"; }; - CP11X_LABEL(nand_controller): nand@720000 { + CP11X_LABEL(nand_controller): nand-controller@720000 { /* * Due to the limitation of the pins available * this controller is only usable on the CPM diff --git a/dts/src/arm64/marvell/cn9130-crb.dtsi b/dts/src/arm64/marvell/cn9130-crb.dtsi index 1acd746284..6fcc34f7b4 100644 --- a/dts/src/arm64/marvell/cn9130-crb.dtsi +++ b/dts/src/arm64/marvell/cn9130-crb.dtsi @@ -78,9 +78,9 @@ compatible = "sff,sfp"; i2c-bus = <&cp0_i2c1>; mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>; - los-gpio = <&expander0 15 GPIO_ACTIVE_HIGH>; - tx-disable-gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>; + los-gpios = <&expander0 15 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>; maximum-power-milliwatt = <3000>; status = "okay"; }; @@ -120,7 +120,7 @@ "mpp59", "mpp60", "mpp61"; marvell,function = "sdio"; }; - cp0_spi0_pins: cp0-spi-pins-0 { + cp0_spi1_pins: cp0-spi-pins-1 { marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; marvell,function = "spi1"; }; @@ -170,7 +170,7 @@ &cp0_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cp0_spi0_pins>; + pinctrl-0 = <&cp0_spi1_pins>; reg = <0x700680 0x50>, /* control */ <0x2000000 0x1000000>; /* CS0 */ status = "okay"; @@ -207,11 +207,9 @@ reg = <0>; }; - switch6: switch0@6 { + switch6: ethernet-switch@6 { /* Actual device is MV88E6393X */ compatible = "marvell,mv88e6190"; - #address-cells = <1>; - #size-cells = <0>; reg = <6>; interrupt-parent = <&cp0_gpio1>; interrupts = <28 IRQ_TYPE_LEVEL_LOW>; @@ -220,59 +218,59 @@ dsa,member = <0 0>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@1 { + ethernet-port@1 { reg = <1>; label = "p1"; phy-handle = <&switch0phy1>; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "p2"; phy-handle = <&switch0phy2>; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "p3"; phy-handle = <&switch0phy3>; }; - port@4 { + ethernet-port@4 { reg = <4>; label = "p4"; phy-handle = <&switch0phy4>; }; - port@5 { + ethernet-port@5 { reg = <5>; label = "p5"; phy-handle = <&switch0phy5>; }; - port@6 { + ethernet-port@6 { reg = <6>; label = "p6"; phy-handle = <&switch0phy6>; }; - port@7 { + ethernet-port@7 { reg = <7>; label = "p7"; phy-handle = <&switch0phy7>; }; - port@8 { + ethernet-port@8 { reg = <8>; label = "p8"; phy-handle = <&switch0phy8>; }; - port@9 { + ethernet-port@9 { reg = <9>; label = "p9"; phy-mode = "10gbase-r"; @@ -280,10 +278,11 @@ managed = "in-band-status"; }; - port@a { + ethernet-port@a { reg = <10>; - label = "cpu"; ethernet = <&cp0_eth0>; + phy-mode = "10gbase-r"; + managed = "in-band-status"; }; }; @@ -292,35 +291,35 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy1: switch0phy1@1 { + switch0phy1: ethernet-phy@1 { reg = <0x1>; }; - switch0phy2: switch0phy2@2 { + switch0phy2: ethernet-phy@2 { reg = <0x2>; }; - switch0phy3: switch0phy3@3 { + switch0phy3: ethernet-phy@3 { reg = <0x3>; }; - switch0phy4: switch0phy4@4 { + switch0phy4: ethernet-phy@4 { reg = <0x4>; }; - switch0phy5: switch0phy5@5 { + switch0phy5: ethernet-phy@5 { reg = <0x5>; }; - switch0phy6: switch0phy6@6 { + switch0phy6: ethernet-phy@6 { reg = <0x6>; }; - switch0phy7: switch0phy7@7 { + switch0phy7: ethernet-phy@7 { reg = <0x7>; }; - switch0phy8: switch0phy8@8 { + switch0phy8: ethernet-phy@8 { reg = <0x8>; }; }; diff --git a/dts/src/arm64/marvell/cn9130-db-comexpress.dtsi b/dts/src/arm64/marvell/cn9130-db-comexpress.dtsi new file mode 100644 index 0000000000..028496ebc4 --- /dev/null +++ b/dts/src/arm64/marvell/cn9130-db-comexpress.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the CN9130-DB Com Express CPU module board. + */ + +#include "cn9130-db.dtsi" + +/ { + model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board"; + compatible = "marvell,cn9130-cpu-module", "marvell,cn9130", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; + +}; + +&ap0_reg_sd_vccq { + regulator-max-microvolt = <1800000>; + states = <1800000 0x1 1800000 0x0>; + /delete-property/ gpios; +}; + +&cp0_reg_usb3_vbus0 { + /delete-property/ gpio; +}; + +&cp0_reg_usb3_vbus1 { + /delete-property/ gpio; +}; + +&cp0_reg_sd_vcc { + status = "disabled"; +}; + +&cp0_reg_sd_vccq { + status = "disabled"; +}; + +&cp0_sdhci0 { + status = "disabled"; +}; + +&cp0_eth0 { + status = "disabled"; +}; + +&cp0_eth1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +&cp0_eth2 { + status = "disabled"; +}; + +&cp0_mdio { + status = "okay"; + pinctrl-0 = <&cp0_ge_mdio_pins>; + phy0: ethernet-phy@0 { + status = "okay"; + }; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible = "marvell,cp115-standalone-pinctrl"; + + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins = "mpp40", "mpp41"; + marvell,function = "ge"; + }; + }; +}; + +&cp0_sdhci0 { + status = "disabled"; +}; + +&cp0_spi1 { + status = "okay"; +}; + +&cp0_usb3_0 { + status = "okay"; + usb-phy = <&cp0_usb3_0_phy0>; + phy-names = "usb"; + /delete-property/ phys; +}; + +&cp0_usb3_1 { + status = "okay"; + usb-phy = <&cp0_usb3_0_phy1>; + phy-names = "usb"; + /delete-property/ phys; +}; diff --git a/dts/src/arm64/marvell/cn9130-db.dtsi b/dts/src/arm64/marvell/cn9130-db.dtsi index 7e20987253..6eb6a175de 100644 --- a/dts/src/arm64/marvell/cn9130-db.dtsi +++ b/dts/src/arm64/marvell/cn9130-db.dtsi @@ -90,10 +90,10 @@ cp0_sfp_eth0: sfp-eth@0 { compatible = "sff,sfp"; i2c-bus = <&cp0_sfpp0_i2c>; - los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>; + los-gpios = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>; /* * SFP cages are unconnected on early PCBs because of an the I2C * lanes not being connected. Prevent the port for being @@ -307,7 +307,7 @@ &cp0_spi1 { status = "disabled"; pinctrl-names = "default"; - pinctrl-0 = <&cp0_spi0_pins>; + pinctrl-0 = <&cp0_spi1_pins>; reg = <0x700680 0x50>; flash@0 { @@ -371,7 +371,7 @@ "mpp59", "mpp60", "mpp61"; marvell,function = "sdio"; }; - cp0_spi0_pins: cp0-spi-pins-0 { + cp0_spi1_pins: cp0-spi-pins-1 { marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; marvell,function = "spi1"; }; @@ -404,7 +404,7 @@ &cp0_usb3_1 { status = "okay"; usb-phy = <&cp0_usb3_0_phy1>; - phys = <&cp0_utmi1>; + phys = <&cp0_utmi1>; phy-names = "utmi"; dr_mode = "host"; }; diff --git a/dts/src/arm64/marvell/cn9131-db-comexpress.dtsi b/dts/src/arm64/marvell/cn9131-db-comexpress.dtsi new file mode 100644 index 0000000000..6f3914bcfd --- /dev/null +++ b/dts/src/arm64/marvell/cn9131-db-comexpress.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the CN9131-DB Com Express CPU module board. + */ + +#include "cn9131-db.dtsi" + +/ { + model = "Marvell Armada CN9131-DB COM EXPRESS type 7 CPU module board"; + compatible = "marvell,cn9131-cpu-module", "marvell,cn9131", "marvell,cn9130", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; + +}; + +&ap0_reg_sd_vccq { + regulator-max-microvolt = <1800000>; + states = <1800000 0x1 1800000 0x0>; + /delete-property/ gpios; +}; + +&cp0_reg_usb3_vbus0 { + /delete-property/ gpio; +}; + +&cp0_reg_usb3_vbus1 { + /delete-property/ gpio; +}; + +&cp1_reg_usb3_vbus0 { + /delete-property/ gpio; +}; + +&cp0_reg_sd_vcc { + status = "disabled"; +}; + +&cp0_reg_sd_vccq { + status = "disabled"; +}; + +&cp0_sdhci0 { + status = "disabled"; +}; + +&cp0_eth0 { + status = "disabled"; +}; + +&cp0_eth1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +&cp0_eth2 { + status = "disabled"; +}; + +&cp0_mdio { + status = "okay"; + pinctrl-0 = <&cp0_ge_mdio_pins>; + phy0: ethernet-phy@0 { + status = "okay"; + }; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible = "marvell,cp115-standalone-pinctrl"; + + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins = "mpp40", "mpp41"; + marvell,function = "ge"; + }; + }; +}; + +&cp0_sdhci0 { + status = "disabled"; +}; + +&cp0_spi1 { + status = "okay"; +}; + +&cp0_usb3_0 { + status = "okay"; + usb-phy = <&cp0_usb3_0_phy0>; + phy-names = "usb"; + /delete-property/ phys; +}; + +&cp0_usb3_1 { + status = "okay"; + usb-phy = <&cp0_usb3_0_phy1>; + phy-names = "usb"; + /delete-property/ phys; +}; + +&cp1_usb3_1 { + status = "okay"; + usb-phy = <&cp1_usb3_0_phy0>; + /* Generic PHY, providing serdes lanes */ + phys = <&cp1_comphy3 1>; + phy-names = "usb"; +}; diff --git a/dts/src/arm64/marvell/cn9131-db.dtsi b/dts/src/arm64/marvell/cn9131-db.dtsi index b7fc241a22..ff8422fae3 100644 --- a/dts/src/arm64/marvell/cn9131-db.dtsi +++ b/dts/src/arm64/marvell/cn9131-db.dtsi @@ -37,10 +37,10 @@ cp1_sfp_eth1: sfp-eth1 { compatible = "sff,sfp"; i2c-bus = <&cp1_i2c0>; - los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; + los-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cp1_sfp_pins>; /* diff --git a/dts/src/arm64/marvell/cn9132-db.dtsi b/dts/src/arm64/marvell/cn9132-db.dtsi index 3f1795fb4f..512a4fa286 100644 --- a/dts/src/arm64/marvell/cn9132-db.dtsi +++ b/dts/src/arm64/marvell/cn9132-db.dtsi @@ -57,10 +57,10 @@ cp2_sfp_eth0: sfp-eth0 { compatible = "sff,sfp"; i2c-bus = <&cp2_sfpp0_i2c>; - los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>; + los-gpios = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>; /* * SFP cages are unconnected on early PCBs because of an the I2C * lanes not being connected. Prevent the port for being |