diff options
Diffstat (limited to 'dts/src/arm64/microchip/sparx5_pcb125.dts')
| -rw-r--r-- | dts/src/arm64/microchip/sparx5_pcb125.dts | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/dts/src/arm64/microchip/sparx5_pcb125.dts b/dts/src/arm64/microchip/sparx5_pcb125.dts new file mode 100644 index 0000000000..dbf8c1d48a --- /dev/null +++ b/dts/src/arm64/microchip/sparx5_pcb125.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/ { + model = "Sparx5 PCB125 Reference Board"; + compatible = "microchip,sparx5-pcb125", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; + +&gpio { + emmc_pins: emmc-pins { + /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" + * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) + */ + pins = "GPIO_34", "GPIO_38", "GPIO_39", + "GPIO_40", "GPIO_41", "GPIO_42", + "GPIO_43", "GPIO_44", "GPIO_45", + "GPIO_46", "GPIO_47"; + drive-strength = <3>; + function = "emmc"; + }; +}; + +&sdhci0 { + status = "okay"; + bus-width = <8>; + non-removable; + pinctrl-0 = <&emmc_pins>; + max-frequency = <8000000>; + microchip,clock-delay = <10>; +}; + +&spi0 { + status = "okay"; + spi@0 { + compatible = "spi-mux"; + mux-controls = <&mux>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* CS0 */ + flash@9 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; + reg = <0x9>; /* SPI */ + }; + }; + spi@1 { + compatible = "spi-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* CS1 */ + flash@9 { + compatible = "spi-nand"; + pinctrl-0 = <&cs1_pins>; + pinctrl-names = "default"; + spi-max-frequency = <8000000>; + reg = <0x9>; /* SPI */ + }; + }; +}; + +&sgpio0 { + status = "okay"; + microchip,sgpio-port-ranges = <0 23>; +}; + +&i2c1 { + status = "okay"; +}; |