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-rw-r--r--dts/src/arm64/qcom/ipq9574.dtsi182
1 files changed, 162 insertions, 20 deletions
diff --git a/dts/src/arm64/qcom/ipq9574.dtsi b/dts/src/arm64/qcom/ipq9574.dtsi
index f120c7c523..51aba071c1 100644
--- a/dts/src/arm64/qcom/ipq9574.dtsi
+++ b/dts/src/arm64/qcom/ipq9574.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -42,6 +43,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
+ #cooling-cells = <2>;
};
CPU1: cpu@1 {
@@ -54,6 +56,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
+ #cooling-cells = <2>;
};
CPU2: cpu@2 {
@@ -66,6 +69,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
+ #cooling-cells = <2>;
};
CPU3: cpu@3 {
@@ -78,6 +82,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
+ #cooling-cells = <2>;
};
L2_0: l2-cache {
@@ -151,6 +156,22 @@
method = "smc";
};
+ rpm: remoteproc {
+ compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
+
+ glink-edge {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-ipq9574";
+ qcom,glink-channels = "rpm_requests";
+ };
+ };
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -179,18 +200,6 @@
};
};
- rpm-glink {
- compatible = "qcom,glink-rpm";
- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
- mboxes = <&apcs_glb 0>;
-
- rpm_requests: rpm-requests {
- compatible = "qcom,rpm-ipq9574";
- qcom,glink-channels = "rpm_requests";
- };
- };
-
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -401,6 +410,8 @@
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ assigned-clock-rates = <50000000>;
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx";
status = "disabled";
@@ -429,6 +440,8 @@
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+ assigned-clock-rates = <50000000>;
dmas = <&blsp_dma 16>, <&blsp_dma 17>;
dma-names = "tx", "rx";
status = "disabled";
@@ -457,6 +470,8 @@
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
+ assigned-clock-rates = <50000000>;
dmas = <&blsp_dma 18>, <&blsp_dma 19>;
dma-names = "tx", "rx";
status = "disabled";
@@ -486,6 +501,8 @@
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
+ assigned-clock-rates = <50000000>;
dmas = <&blsp_dma 20>, <&blsp_dma 21>;
dma-names = "tx", "rx";
status = "disabled";
@@ -505,6 +522,91 @@
status = "disabled";
};
+ usb_0_qusbphy: phy@7b000 {
+ compatible = "qcom,ipq9574-qusb2-phy";
+ reg = <0x0007b000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo_board_clk>;
+ clock-names = "cfg_ahb",
+ "ref";
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
+ };
+
+ usb_0_qmpphy: phy@7d000 {
+ compatible = "qcom,ipq9574-qmp-usb3-phy";
+ reg = <0x0007d000 0xa00>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
+ <&xo_board_clk>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>,
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "usb0_pipe_clk";
+
+ status = "disabled";
+ };
+
+ usb3: usb@8af8800 {
+ compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
+ reg = <0x08af8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_SNOC_USB_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_ANOC_USB_AXI_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <200000000>,
+ <24000000>;
+
+ interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event";
+
+ resets = <&gcc GCC_USB_BCR>;
+ status = "disabled";
+
+ usb_0_dwc3: usb@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x8a00000 0xcd00>;
+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "ref";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
@@ -727,18 +829,28 @@
thermal-sensors = <&tsens 10>;
trips {
- cpu-critical {
+ cpu0_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
- cpu-passive {
+ cpu0_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu1-thermal {
@@ -747,18 +859,28 @@
thermal-sensors = <&tsens 11>;
trips {
- cpu-critical {
+ cpu1_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
- cpu-passive {
+ cpu1_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu2-thermal {
@@ -767,18 +889,28 @@
thermal-sensors = <&tsens 12>;
trips {
- cpu-critical {
+ cpu2_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
- cpu-passive {
+ cpu2_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu3-thermal {
@@ -787,18 +919,28 @@
thermal-sensors = <&tsens 13>;
trips {
- cpu-critical {
+ cpu3_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
- cpu-passive {
+ cpu3_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
wcss-phyb-thermal {
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-19 22:12:34 +0000