diff options
Diffstat (limited to 'dts/src/arm64/qcom/sc7280-chrome-common.dtsi')
| -rw-r--r-- | dts/src/arm64/qcom/sc7280-chrome-common.dtsi | 111 |
1 files changed, 83 insertions, 28 deletions
diff --git a/dts/src/arm64/qcom/sc7280-chrome-common.dtsi b/dts/src/arm64/qcom/sc7280-chrome-common.dtsi index 9f4a9c263c..c4d00a81da 100644 --- a/dts/src/arm64/qcom/sc7280-chrome-common.dtsi +++ b/dts/src/arm64/qcom/sc7280-chrome-common.dtsi @@ -17,6 +17,9 @@ * required by the setup for Chrome boards. */ +/delete-node/ &cdsp_mem; +/delete-node/ &gpu_zap_mem; +/delete-node/ &gpu_zap_shader; /delete-node/ &hyp_mem; /delete-node/ &xbl_mem; /delete-node/ &reserved_xbl_uefi_log; @@ -24,11 +27,6 @@ / { reserved-memory { - adsp_mem: memory@86700000 { - reg = <0x0 0x86700000 0x0 0x2800000>; - no-map; - }; - camera_mem: memory@8ad00000 { reg = <0x0 0x8ad00000 0x0 0x500000>; no-map; @@ -38,22 +36,27 @@ reg = <0x0 0x8b200000 0x0 0x500000>; no-map; }; + }; +}; - mpss_mem: memory@8b800000 { - reg = <0x0 0x8b800000 0x0 0xf600000>; - no-map; - }; +&lpass_aon { + status = "okay"; +}; - wpss_mem: memory@9ae00000 { - reg = <0x0 0x9ae00000 0x0 0x1900000>; - no-map; - }; +&lpass_core { + status = "okay"; +}; - mba_mem: memory@9c700000 { - reg = <0x0 0x9c700000 0x0 0x200000>; - no-map; - }; - }; +&lpass_hm { + status = "okay"; +}; + +&lpasscc { + status = "okay"; +}; + +&pdc_reset { + status = "okay"; }; /* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */ @@ -70,8 +73,9 @@ */ &qspi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; + pinctrl-1 = <&qspi_sleep>; spi_flash: flash@0 { compatible = "jedec,spi-nor"; @@ -83,15 +87,66 @@ }; }; -/* Modem setup is different on Chrome setups than typical Qualcomm setup */ -&remoteproc_mpss { +/* Currently not used */ +&remoteproc_cdsp { + /delete-property/ memory-region; +}; + +&remoteproc_wpss { + compatible = "qcom,sc7280-wpss-pil"; + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, + <&gcc GCC_WPSS_AHB_CLK>, + <&gcc GCC_WPSS_RSCP_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ahb_bdg", + "ahb", + "rscp", + "xo"; + + resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, + <&pdc_reset PDC_WPSS_SYNC_RESET>; + reset-names = "restart", "pdc_sync"; + + qcom,halt-regs = <&tcsr_1 0x17000>; + + firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt"; + status = "okay"; - compatible = "qcom,sc7280-mss-pil"; - iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; - memory-region = <&mba_mem>, <&mpss_mem>; }; -/* Increase the size from 2.5MB to 8MB */ -&rmtfs_mem { - reg = <0x0 0x9c900000 0x0 0x800000>; +&scm { + /* TF-A firmware maps memory cached so mark dma-coherent to match. */ + dma-coherent; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + + wifi-firmware { + iommus = <&apps_smmu 0x1c02 0x1>; + }; +}; + +/* PINCTRL - chrome-common pinctrl */ + +&tlmm { + qspi_sleep: qspi-sleep-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + + /* + * When we're not actively transferring we want pins as GPIOs + * with output disabled so that the quad SPI IP block stops + * driving them. We rely on the normal pulls configured in + * the active state and don't redefine them here. Also note + * that we don't need the reverse (output-enable) in the + * normal mode since the "output-enable" only matters for + * GPIO function. + */ + function = "gpio"; + output-disable; + }; }; |