summaryrefslogtreecommitdiffstats
path: root/dts/src/arm64/qcom/sc7280.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'dts/src/arm64/qcom/sc7280.dtsi')
-rw-r--r--dts/src/arm64/qcom/sc7280.dtsi634
1 files changed, 460 insertions, 174 deletions
diff --git a/dts/src/arm64/qcom/sc7280.dtsi b/dts/src/arm64/qcom/sc7280.dtsi
index dac3b69e31..212580316d 100644
--- a/dts/src/arm64/qcom/sc7280.dtsi
+++ b/dts/src/arm64/qcom/sc7280.dtsi
@@ -22,6 +22,7 @@
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/sound/qcom,lpass.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -828,6 +829,7 @@
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
+ power-domains = <&rpmhpd SC7280_CX>;
};
ipcc: mailbox@408000 {
@@ -2043,7 +2045,9 @@
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
- <&gcc GCC_DDRSS_PCIE_SF_CLK>;
+ <&gcc GCC_DDRSS_PCIE_SF_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
clock-names = "pipe",
"pipe_mux",
@@ -2055,7 +2059,9 @@
"bus_slave",
"slave_q2a",
"tbu",
- "ddrss_sf_tbu";
+ "ddrss_sf_tbu",
+ "aggre0",
+ "aggre1";
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
@@ -2155,12 +2161,17 @@
};
tcsr_mutex: hwlock@1f40000 {
- compatible = "qcom,tcsr-mutex", "syscon";
- reg = <0 0x01f40000 0 0x40000>;
+ compatible = "qcom,tcsr-mutex";
+ reg = <0 0x01f40000 0 0x20000>;
#hwlock-cells = <1>;
};
- tcsr: syscon@1fc0000 {
+ tcsr_1: syscon@1f60000 {
+ compatible = "qcom,sc7280-tcsr", "syscon";
+ reg = <0 0x01f60000 0 0x20000>;
+ };
+
+ tcsr_2: syscon@1fc0000 {
compatible = "qcom,sc7280-tcsr", "syscon";
reg = <0 0x01fc0000 0 0x30000>;
};
@@ -2168,14 +2179,121 @@
lpasscc: lpasscc@3000000 {
compatible = "qcom,sc7280-lpasscc";
reg = <0 0x03000000 0 0x40>,
- <0 0x03c04000 0 0x4>,
- <0 0x03389000 0 0x24>;
- reg-names = "qdsp6ss", "top_cc", "cc";
+ <0 0x03c04000 0 0x4>;
+ reg-names = "qdsp6ss", "top_cc";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
};
+ lpass_rx_macro: codec@3200000 {
+ compatible = "qcom,sc7280-lpass-rx-macro";
+ reg = <0 0x03200000 0 0x1000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
+
+ clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
+ <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
+ <&lpass_va_macro>;
+ clock-names = "mclk", "npl", "fsgen";
+
+ power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
+ <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
+ power-domain-names = "macro", "dcodec";
+
+ #clock-cells = <0>;
+ #sound-dai-cells = <1>;
+
+ status = "disabled";
+ };
+
+ swr0: soundwire@3210000 {
+ compatible = "qcom,soundwire-v1.6.0";
+ reg = <0 0x03210000 0 0x2000>;
+
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lpass_rx_macro>;
+ clock-names = "iface";
+
+ qcom,din-ports = <0>;
+ qcom,dout-ports = <5>;
+
+ resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
+ reset-names = "swr_audio_cgcr";
+
+ qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
+ qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
+ qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
+
+ #sound-dai-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ lpass_tx_macro: codec@3220000 {
+ compatible = "qcom,sc7280-lpass-tx-macro";
+ reg = <0 0x03220000 0 0x1000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
+
+ clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
+ <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
+ <&lpass_va_macro>;
+ clock-names = "mclk", "npl", "fsgen";
+
+ power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
+ <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
+ power-domain-names = "macro", "dcodec";
+
+ #clock-cells = <0>;
+ #sound-dai-cells = <1>;
+
+ status = "disabled";
+ };
+
+ swr1: soundwire@3230000 {
+ compatible = "qcom,soundwire-v1.6.0";
+ reg = <0 0x03230000 0 0x2000>;
+
+ interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lpass_tx_macro>;
+ clock-names = "iface";
+
+ qcom,din-ports = <3>;
+ qcom,dout-ports = <0>;
+
+ resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>;
+ reset-names = "swr_audio_cgcr";
+
+ qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
+ qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
+ qcom,port-offset = <1>;
+
+ #sound-dai-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
lpass_audiocc: clock-controller@3300000 {
compatible = "qcom,sc7280-lpassaudiocc";
reg = <0 0x03300000 0 0x30000>;
@@ -2185,6 +2303,27 @@
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ lpass_va_macro: codec@3370000 {
+ compatible = "qcom,sc7280-lpass-va-macro";
+ reg = <0 0x03370000 0 0x1000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
+
+ clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>;
+ clock-names = "mclk";
+
+ power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
+ <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
+ power-domain-names = "macro", "dcodec";
+
+ #clock-cells = <0>;
+ #sound-dai-cells = <1>;
+
+ status = "disabled";
};
lpass_aon: clock-controller@3380000 {
@@ -2192,13 +2331,13 @@
reg = <0 0x03380000 0 0x30000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
- <&lpasscore LPASS_CORE_CC_CORE_CLK>;
+ <&lpass_core LPASS_CORE_CC_CORE_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
#clock-cells = <1>;
#power-domain-cells = <1>;
};
- lpasscore: clock-controller@3900000 {
+ lpass_core: clock-controller@3900000 {
compatible = "qcom,sc7280-lpasscorecc";
reg = <0 0x03900000 0 0x50000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
@@ -2208,6 +2347,67 @@
#power-domain-cells = <1>;
};
+ lpass_cpu: audio@3987000 {
+ compatible = "qcom,sc7280-lpass-cpu";
+
+ reg = <0 0x03987000 0 0x68000>,
+ <0 0x03b00000 0 0x29000>,
+ <0 0x03260000 0 0xc000>,
+ <0 0x03280000 0 0x29000>,
+ <0 0x03340000 0 0x29000>,
+ <0 0x0336c000 0 0x3000>;
+ reg-names = "lpass-hdmiif",
+ "lpass-lpaif",
+ "lpass-rxtx-cdc-dma-lpm",
+ "lpass-rxtx-lpaif",
+ "lpass-va-lpaif",
+ "lpass-va-cdc-dma-lpm";
+
+ iommus = <&apps_smmu 0x1820 0>,
+ <&apps_smmu 0x1821 0>,
+ <&apps_smmu 0x1832 0>;
+
+ power-domains = <&rpmhpd SC7280_LCX>;
+ power-domain-names = "lcx";
+ required-opps = <&rpmhpd_opp_nom>;
+
+ clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>,
+ <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>,
+ <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>,
+ <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>,
+ <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>,
+ <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>,
+ <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>,
+ <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>,
+ <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>,
+ <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>;
+ clock-names = "aon_cc_audio_hm_h",
+ "audio_cc_ext_mclk0",
+ "core_cc_sysnoc_mport_core",
+ "core_cc_ext_if0_ibit",
+ "core_cc_ext_if1_ibit",
+ "audio_cc_codec_mem",
+ "audio_cc_codec_mem0",
+ "audio_cc_codec_mem1",
+ "audio_cc_codec_mem2",
+ "aon_cc_va_mem0";
+
+ #sound-dai-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpass-irq-lpaif",
+ "lpass-irq-hdmi",
+ "lpass-irq-vaif",
+ "lpass-irq-rxtxif";
+
+ status = "disabled";
+ };
+
lpass_hm: clock-controller@3c00000 {
compatible = "qcom,sc7280-lpasshm";
reg = <0 0x3c00000 0 0x28>;
@@ -2352,11 +2552,19 @@
opp-supported-hw = <0x03>;
};
- opp-550000000 {
+ /* Only applicable for SKUs which has 550Mhz as Fmax */
+ opp-550000000-0 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <8368000>;
+ opp-supported-hw = <0x01>;
+ };
+
+ opp-550000000-1 {
opp-hz = /bits/ 64 <550000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <6832000>;
- opp-supported-hw = <0x03>;
+ opp-supported-hw = <0x02>;
};
opp-608000000 {
@@ -2522,9 +2730,9 @@
<&pdc_reset PDC_MODEM_SYNC_RESET>;
reset-names = "mss_restart", "pdc_reset";
- qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
- qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>;
- qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;
+ qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>;
+ qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>;
+ qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>;
status = "disabled";
@@ -3181,6 +3389,7 @@
"dm_hs_phy_irq";
power-domains = <&gcc GCC_USB30_SEC_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
resets = <&gcc GCC_USB30_SEC_BCR>;
@@ -3259,7 +3468,7 @@
<&pdc_reset PDC_WPSS_SYNC_RESET>;
reset-names = "restart", "pdc_sync";
- qcom,halt-regs = <&tcsr_mutex 0x37000>;
+ qcom,halt-regs = <&tcsr_1 0x17000>;
status = "disabled";
@@ -3275,6 +3484,82 @@
};
};
+ pmu@9091000 {
+ compatible = "qcom,sc7280-llcc-bwmon";
+ reg = <0 0x9091000 0 0x1000>;
+
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
+
+ operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+ llcc_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <800000>;
+ };
+ opp-1 {
+ opp-peak-kBps = <1804000>;
+ };
+ opp-2 {
+ opp-peak-kBps = <2188000>;
+ };
+ opp-3 {
+ opp-peak-kBps = <3072000>;
+ };
+ opp-4 {
+ opp-peak-kBps = <4068000>;
+ };
+ opp-5 {
+ opp-peak-kBps = <6220000>;
+ };
+ opp-6 {
+ opp-peak-kBps = <6832000>;
+ };
+ opp-7 {
+ opp-peak-kBps = <8532000>;
+ };
+ };
+ };
+
+ pmu@90b6400 {
+ compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon";
+ reg = <0 0x090b6400 0 0x600>;
+
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <2400000>;
+ };
+ opp-1 {
+ opp-peak-kBps = <4800000>;
+ };
+ opp-2 {
+ opp-peak-kBps = <7456000>;
+ };
+ opp-3 {
+ opp-peak-kBps = <9600000>;
+ };
+ opp-4 {
+ opp-peak-kBps = <12896000>;
+ };
+ opp-5 {
+ opp-peak-kBps = <14928000>;
+ };
+ opp-6 {
+ opp-peak-kBps = <17056000>;
+ };
+ };
+ };
+
dc_noc: interconnect@90e0000 {
reg = <0 0x090e0000 0 0x5080>;
compatible = "qcom,sc7280-dc-noc";
@@ -3367,6 +3652,7 @@
"ss_phy_irq";
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
resets = <&gcc GCC_USB30_PRIM_BCR>;
@@ -3972,791 +4258,791 @@
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
- dp_hot_plug_det: dp-hot-plug-det {
+ dp_hot_plug_det: dp-hot-plug-det-pins {
pins = "gpio47";
function = "dp_hot";
};
- edp_hot_plug_det: edp-hot-plug-det {
+ edp_hot_plug_det: edp-hot-plug-det-pins {
pins = "gpio60";
function = "edp_hot";
};
- mi2s0_data0: mi2s0-data0 {
+ mi2s0_data0: mi2s0-data0-pins {
pins = "gpio98";
function = "mi2s0_data0";
};
- mi2s0_data1: mi2s0-data1 {
+ mi2s0_data1: mi2s0-data1-pins {
pins = "gpio99";
function = "mi2s0_data1";
};
- mi2s0_mclk: mi2s0-mclk {
+ mi2s0_mclk: mi2s0-mclk-pins {
pins = "gpio96";
function = "pri_mi2s";
};
- mi2s0_sclk: mi2s0-sclk {
+ mi2s0_sclk: mi2s0-sclk-pins {
pins = "gpio97";
function = "mi2s0_sck";
};
- mi2s0_ws: mi2s0-ws {
+ mi2s0_ws: mi2s0-ws-pins {
pins = "gpio100";
function = "mi2s0_ws";
};
- mi2s1_data0: mi2s1-data0 {
+ mi2s1_data0: mi2s1-data0-pins {
pins = "gpio107";
function = "mi2s1_data0";
};
- mi2s1_sclk: mi2s1-sclk {
+ mi2s1_sclk: mi2s1-sclk-pins {
pins = "gpio106";
function = "mi2s1_sck";
};
- mi2s1_ws: mi2s1-ws {
+ mi2s1_ws: mi2s1-ws-pins {
pins = "gpio108";
function = "mi2s1_ws";
};
- pcie1_clkreq_n: pcie1-clkreq-n {
+ pcie1_clkreq_n: pcie1-clkreq-n-pins {
pins = "gpio79";
function = "pcie1_clkreqn";
};
- qspi_clk: qspi-clk {
+ qspi_clk: qspi-clk-pins {
pins = "gpio14";
function = "qspi_clk";
};
- qspi_cs0: qspi-cs0 {
+ qspi_cs0: qspi-cs0-pins {
pins = "gpio15";
function = "qspi_cs";
};
- qspi_cs1: qspi-cs1 {
+ qspi_cs1: qspi-cs1-pins {
pins = "gpio19";
function = "qspi_cs";
};
- qspi_data01: qspi-data01 {
+ qspi_data01: qspi-data01-pins {
pins = "gpio12", "gpio13";
function = "qspi_data";
};
- qspi_data12: qspi-data12 {
+ qspi_data12: qspi-data12-pins {
pins = "gpio16", "gpio17";
function = "qspi_data";
};
- qup_i2c0_data_clk: qup-i2c0-data-clk {
+ qup_i2c0_data_clk: qup-i2c0-data-clk-pins {
pins = "gpio0", "gpio1";
function = "qup00";
};
- qup_i2c1_data_clk: qup-i2c1-data-clk {
+ qup_i2c1_data_clk: qup-i2c1-data-clk-pins {
pins = "gpio4", "gpio5";
function = "qup01";
};
- qup_i2c2_data_clk: qup-i2c2-data-clk {
+ qup_i2c2_data_clk: qup-i2c2-data-clk-pins {
pins = "gpio8", "gpio9";
function = "qup02";
};
- qup_i2c3_data_clk: qup-i2c3-data-clk {
+ qup_i2c3_data_clk: qup-i2c3-data-clk-pins {
pins = "gpio12", "gpio13";
function = "qup03";
};
- qup_i2c4_data_clk: qup-i2c4-data-clk {
+ qup_i2c4_data_clk: qup-i2c4-data-clk-pins {
pins = "gpio16", "gpio17";
function = "qup04";
};
- qup_i2c5_data_clk: qup-i2c5-data-clk {
+ qup_i2c5_data_clk: qup-i2c5-data-clk-pins {
pins = "gpio20", "gpio21";
function = "qup05";
};
- qup_i2c6_data_clk: qup-i2c6-data-clk {
+ qup_i2c6_data_clk: qup-i2c6-data-clk-pins {
pins = "gpio24", "gpio25";
function = "qup06";
};
- qup_i2c7_data_clk: qup-i2c7-data-clk {
+ qup_i2c7_data_clk: qup-i2c7-data-clk-pins {
pins = "gpio28", "gpio29";
function = "qup07";
};
- qup_i2c8_data_clk: qup-i2c8-data-clk {
+ qup_i2c8_data_clk: qup-i2c8-data-clk-pins {
pins = "gpio32", "gpio33";
function = "qup10";
};
- qup_i2c9_data_clk: qup-i2c9-data-clk {
+ qup_i2c9_data_clk: qup-i2c9-data-clk-pins {
pins = "gpio36", "gpio37";
function = "qup11";
};
- qup_i2c10_data_clk: qup-i2c10-data-clk {
+ qup_i2c10_data_clk: qup-i2c10-data-clk-pins {
pins = "gpio40", "gpio41";
function = "qup12";
};
- qup_i2c11_data_clk: qup-i2c11-data-clk {
+ qup_i2c11_data_clk: qup-i2c11-data-clk-pins {
pins = "gpio44", "gpio45";
function = "qup13";
};
- qup_i2c12_data_clk: qup-i2c12-data-clk {
+ qup_i2c12_data_clk: qup-i2c12-data-clk-pins {
pins = "gpio48", "gpio49";
function = "qup14";
};
- qup_i2c13_data_clk: qup-i2c13-data-clk {
+ qup_i2c13_data_clk: qup-i2c13-data-clk-pins {
pins = "gpio52", "gpio53";
function = "qup15";
};
- qup_i2c14_data_clk: qup-i2c14-data-clk {
+ qup_i2c14_data_clk: qup-i2c14-data-clk-pins {
pins = "gpio56", "gpio57";
function = "qup16";
};
- qup_i2c15_data_clk: qup-i2c15-data-clk {
+ qup_i2c15_data_clk: qup-i2c15-data-clk-pins {
pins = "gpio60", "gpio61";
function = "qup17";
};
- qup_spi0_data_clk: qup-spi0-data-clk {
+ qup_spi0_data_clk: qup-spi0-data-clk-pins {
pins = "gpio0", "gpio1", "gpio2";
function = "qup00";
};
- qup_spi0_cs: qup-spi0-cs {
+ qup_spi0_cs: qup-spi0-cs-pins {
pins = "gpio3";
function = "qup00";
};
- qup_spi0_cs_gpio: qup-spi0-cs-gpio {
+ qup_spi0_cs_gpio: qup-spi0-cs-gpio-pins {
pins = "gpio3";
function = "gpio";
};
- qup_spi1_data_clk: qup-spi1-data-clk {
+ qup_spi1_data_clk: qup-spi1-data-clk-pins {
pins = "gpio4", "gpio5", "gpio6";
function = "qup01";
};
- qup_spi1_cs: qup-spi1-cs {
+ qup_spi1_cs: qup-spi1-cs-pins {
pins = "gpio7";
function = "qup01";
};
- qup_spi1_cs_gpio: qup-spi1-cs-gpio {
+ qup_spi1_cs_gpio: qup-spi1-cs-gpio-pins {
pins = "gpio7";
function = "gpio";
};
- qup_spi2_data_clk: qup-spi2-data-clk {
+ qup_spi2_data_clk: qup-spi2-data-clk-pins {
pins = "gpio8", "gpio9", "gpio10";
function = "qup02";
};
- qup_spi2_cs: qup-spi2-cs {
+ qup_spi2_cs: qup-spi2-cs-pins {
pins = "gpio11";
function = "qup02";
};
- qup_spi2_cs_gpio: qup-spi2-cs-gpio {
+ qup_spi2_cs_gpio: qup-spi2-cs-gpio-pins {
pins = "gpio11";
function = "gpio";
};
- qup_spi3_data_clk: qup-spi3-data-clk {
+ qup_spi3_data_clk: qup-spi3-data-clk-pins {
pins = "gpio12", "gpio13", "gpio14";
function = "qup03";
};
- qup_spi3_cs: qup-spi3-cs {
+ qup_spi3_cs: qup-spi3-cs-pins {
pins = "gpio15";
function = "qup03";
};
- qup_spi3_cs_gpio: qup-spi3-cs-gpio {
+ qup_spi3_cs_gpio: qup-spi3-cs-gpio-pins {
pins = "gpio15";
function = "gpio";
};
- qup_spi4_data_clk: qup-spi4-data-clk {
+ qup_spi4_data_clk: qup-spi4-data-clk-pins {
pins = "gpio16", "gpio17", "gpio18";
function = "qup04";
};
- qup_spi4_cs: qup-spi4-cs {
+ qup_spi4_cs: qup-spi4-cs-pins {
pins = "gpio19";
function = "qup04";
};
- qup_spi4_cs_gpio: qup-spi4-cs-gpio {
+ qup_spi4_cs_gpio: qup-spi4-cs-gpio-pins {
pins = "gpio19";
function = "gpio";
};
- qup_spi5_data_clk: qup-spi5-data-clk {
+ qup_spi5_data_clk: qup-spi5-data-clk-pins {
pins = "gpio20", "gpio21", "gpio22";
function = "qup05";
};
- qup_spi5_cs: qup-spi5-cs {
+ qup_spi5_cs: qup-spi5-cs-pins {
pins = "gpio23";
function = "qup05";
};
- qup_spi5_cs_gpio: qup-spi5-cs-gpio {
+ qup_spi5_cs_gpio: qup-spi5-cs-gpio-pins {
pins = "gpio23";
function = "gpio";
};
- qup_spi6_data_clk: qup-spi6-data-clk {
+ qup_spi6_data_clk: qup-spi6-data-clk-pins {
pins = "gpio24", "gpio25", "gpio26";
function = "qup06";
};
- qup_spi6_cs: qup-spi6-cs {
+ qup_spi6_cs: qup-spi6-cs-pins {
pins = "gpio27";
function = "qup06";
};
- qup_spi6_cs_gpio: qup-spi6-cs-gpio {
+ qup_spi6_cs_gpio: qup-spi6-cs-gpio-pins {
pins = "gpio27";
function = "gpio";
};
- qup_spi7_data_clk: qup-spi7-data-clk {
+ qup_spi7_data_clk: qup-spi7-data-clk-pins {
pins = "gpio28", "gpio29", "gpio30";
function = "qup07";
};
- qup_spi7_cs: qup-spi7-cs {
+ qup_spi7_cs: qup-spi7-cs-pins {
pins = "gpio31";
function = "qup07";
};
- qup_spi7_cs_gpio: qup-spi7-cs-gpio {
+ qup_spi7_cs_gpio: qup-spi7-cs-gpio-pins {
pins = "gpio31";
function = "gpio";
};
- qup_spi8_data_clk: qup-spi8-data-clk {
+ qup_spi8_data_clk: qup-spi8-data-clk-pins {
pins = "gpio32", "gpio33", "gpio34";
function = "qup10";
};
- qup_spi8_cs: qup-spi8-cs {
+ qup_spi8_cs: qup-spi8-cs-pins {
pins = "gpio35";
function = "qup10";
};
- qup_spi8_cs_gpio: qup-spi8-cs-gpio {
+ qup_spi8_cs_gpio: qup-spi8-cs-gpio-pins {
pins = "gpio35";
function = "gpio";
};
- qup_spi9_data_clk: qup-spi9-data-clk {
+ qup_spi9_data_clk: qup-spi9-data-clk-pins {
pins = "gpio36", "gpio37", "gpio38";
function = "qup11";
};
- qup_spi9_cs: qup-spi9-cs {
+ qup_spi9_cs: qup-spi9-cs-pins {
pins = "gpio39";
function = "qup11";
};
- qup_spi9_cs_gpio: qup-spi9-cs-gpio {
+ qup_spi9_cs_gpio: qup-spi9-cs-gpio-pins {
pins = "gpio39";
function = "gpio";
};
- qup_spi10_data_clk: qup-spi10-data-clk {
+ qup_spi10_data_clk: qup-spi10-data-clk-pins {
pins = "gpio40", "gpio41", "gpio42";
function = "qup12";
};
- qup_spi10_cs: qup-spi10-cs {
+ qup_spi10_cs: qup-spi10-cs-pins {
pins = "gpio43";
function = "qup12";
};
- qup_spi10_cs_gpio: qup-spi10-cs-gpio {
+ qup_spi10_cs_gpio: qup-spi10-cs-gpio-pins {
pins = "gpio43";
function = "gpio";
};
- qup_spi11_data_clk: qup-spi11-data-clk {
+ qup_spi11_data_clk: qup-spi11-data-clk-pins {
pins = "gpio44", "gpio45", "gpio46";
function = "qup13";
};
- qup_spi11_cs: qup-spi11-cs {
+ qup_spi11_cs: qup-spi11-cs-pins {
pins = "gpio47";
function = "qup13";
};
- qup_spi11_cs_gpio: qup-spi11-cs-gpio {
+ qup_spi11_cs_gpio: qup-spi11-cs-gpio-pins {
pins = "gpio47";
function = "gpio";
};
- qup_spi12_data_clk: qup-spi12-data-clk {
+ qup_spi12_data_clk: qup-spi12-data-clk-pins {
pins = "gpio48", "gpio49", "gpio50";
function = "qup14";
};
- qup_spi12_cs: qup-spi12-cs {
+ qup_spi12_cs: qup-spi12-cs-pins {
pins = "gpio51";
function = "qup14";
};
- qup_spi12_cs_gpio: qup-spi12-cs-gpio {
+ qup_spi12_cs_gpio: qup-spi12-cs-gpio-pins {
pins = "gpio51";
function = "gpio";
};
- qup_spi13_data_clk: qup-spi13-data-clk {
+ qup_spi13_data_clk: qup-spi13-data-clk-pins {
pins = "gpio52", "gpio53", "gpio54";
function = "qup15";
};
- qup_spi13_cs: qup-spi13-cs {
+ qup_spi13_cs: qup-spi13-cs-pins {
pins = "gpio55";
function = "qup15";
};
- qup_spi13_cs_gpio: qup-spi13-cs-gpio {
+ qup_spi13_cs_gpio: qup-spi13-cs-gpio-pins {
pins = "gpio55";
function = "gpio";
};
- qup_spi14_data_clk: qup-spi14-data-clk {
+ qup_spi14_data_clk: qup-spi14-data-clk-pins {
pins = "gpio56", "gpio57", "gpio58";
function = "qup16";
};
- qup_spi14_cs: qup-spi14-cs {
+ qup_spi14_cs: qup-spi14-cs-pins {
pins = "gpio59";
function = "qup16";
};
- qup_spi14_cs_gpio: qup-spi14-cs-gpio {
+ qup_spi14_cs_gpio: qup-spi14-cs-gpio-pins {
pins = "gpio59";
function = "gpio";
};
- qup_spi15_data_clk: qup-spi15-data-clk {
+ qup_spi15_data_clk: qup-spi15-data-clk-pins {
pins = "gpio60", "gpio61", "gpio62";
function = "qup17";
};
- qup_spi15_cs: qup-spi15-cs {
+ qup_spi15_cs: qup-spi15-cs-pins {
pins = "gpio63";
function = "qup17";
};
- qup_spi15_cs_gpio: qup-spi15-cs-gpio {
+ qup_spi15_cs_gpio: qup-spi15-cs-gpio-pins {
pins = "gpio63";
function = "gpio";
};
- qup_uart0_cts: qup-uart0-cts {
+ qup_uart0_cts: qup-uart0-cts-pins {
pins = "gpio0";
function = "qup00";
};
- qup_uart0_rts: qup-uart0-rts {
+ qup_uart0_rts: qup-uart0-rts-pins {
pins = "gpio1";
function = "qup00";
};
- qup_uart0_tx: qup-uart0-tx {
+ qup_uart0_tx: qup-uart0-tx-pins {
pins = "gpio2";
function = "qup00";
};
- qup_uart0_rx: qup-uart0-rx {
+ qup_uart0_rx: qup-uart0-rx-pins {
pins = "gpio3";
function = "qup00";
};
- qup_uart1_cts: qup-uart1-cts {
+ qup_uart1_cts: qup-uart1-cts-pins {
pins = "gpio4";
function = "qup01";
};
- qup_uart1_rts: qup-uart1-rts {
+ qup_uart1_rts: qup-uart1-rts-pins {
pins = "gpio5";
function = "qup01";
};
- qup_uart1_tx: qup-uart1-tx {
+ qup_uart1_tx: qup-uart1-tx-pins {
pins = "gpio6";
function = "qup01";
};
- qup_uart1_rx: qup-uart1-rx {
+ qup_uart1_rx: qup-uart1-rx-pins {
pins = "gpio7";
function = "qup01";
};
- qup_uart2_cts: qup-uart2-cts {
+ qup_uart2_cts: qup-uart2-cts-pins {
pins = "gpio8";
function = "qup02";
};
- qup_uart2_rts: qup-uart2-rts {
+ qup_uart2_rts: qup-uart2-rts-pins {
pins = "gpio9";
function = "qup02";
};
- qup_uart2_tx: qup-uart2-tx {
+ qup_uart2_tx: qup-uart2-tx-pins {
pins = "gpio10";
function = "qup02";
};
- qup_uart2_rx: qup-uart2-rx {
+ qup_uart2_rx: qup-uart2-rx-pins {
pins = "gpio11";
function = "qup02";
};
- qup_uart3_cts: qup-uart3-cts {
+ qup_uart3_cts: qup-uart3-cts-pins {
pins = "gpio12";
function = "qup03";
};
- qup_uart3_rts: qup-uart3-rts {
+ qup_uart3_rts: qup-uart3-rts-pins {
pins = "gpio13";
function = "qup03";
};
- qup_uart3_tx: qup-uart3-tx {
+ qup_uart3_tx: qup-uart3-tx-pins {
pins = "gpio14";
function = "qup03";
};
- qup_uart3_rx: qup-uart3-rx {
+ qup_uart3_rx: qup-uart3-rx-pins {
pins = "gpio15";
function = "qup03";
};
- qup_uart4_cts: qup-uart4-cts {
+ qup_uart4_cts: qup-uart4-cts-pins {
pins = "gpio16";
function = "qup04";
};
- qup_uart4_rts: qup-uart4-rts {
+ qup_uart4_rts: qup-uart4-rts-pins {
pins = "gpio17";
function = "qup04";
};
- qup_uart4_tx: qup-uart4-tx {
+ qup_uart4_tx: qup-uart4-tx-pins {
pins = "gpio18";
function = "qup04";
};
- qup_uart4_rx: qup-uart4-rx {
+ qup_uart4_rx: qup-uart4-rx-pins {
pins = "gpio19";
function = "qup04";
};
- qup_uart5_cts: qup-uart5-cts {
+ qup_uart5_cts: qup-uart5-cts-pins {
pins = "gpio20";
function = "qup05";
};
- qup_uart5_rts: qup-uart5-rts {
+ qup_uart5_rts: qup-uart5-rts-pins {
pins = "gpio21";
function = "qup05";
};
- qup_uart5_tx: qup-uart5-tx {
+ qup_uart5_tx: qup-uart5-tx-pins {
pins = "gpio22";
function = "qup05";
};
- qup_uart5_rx: qup-uart5-rx {
+ qup_uart5_rx: qup-uart5-rx-pins {
pins = "gpio23";
function = "qup05";
};
- qup_uart6_cts: qup-uart6-cts {
+ qup_uart6_cts: qup-uart6-cts-pins {
pins = "gpio24";
function = "qup06";
};
- qup_uart6_rts: qup-uart6-rts {
+ qup_uart6_rts: qup-uart6-rts-pins {
pins = "gpio25";
function = "qup06";
};
- qup_uart6_tx: qup-uart6-tx {
+ qup_uart6_tx: qup-uart6-tx-pins {
pins = "gpio26";
function = "qup06";
};
- qup_uart6_rx: qup-uart6-rx {
+ qup_uart6_rx: qup-uart6-rx-pins {
pins = "gpio27";
function = "qup06";
};
- qup_uart7_cts: qup-uart7-cts {
+ qup_uart7_cts: qup-uart7-cts-pins {
pins = "gpio28";
function = "qup07";
};
- qup_uart7_rts: qup-uart7-rts {
+ qup_uart7_rts: qup-uart7-rts-pins {
pins = "gpio29";
function = "qup07";
};
- qup_uart7_tx: qup-uart7-tx {
+ qup_uart7_tx: qup-uart7-tx-pins {
pins = "gpio30";
function = "qup07";
};
- qup_uart7_rx: qup-uart7-rx {
+ qup_uart7_rx: qup-uart7-rx-pins {
pins = "gpio31";
function = "qup07";
};
- qup_uart8_cts: qup-uart8-cts {
+ qup_uart8_cts: qup-uart8-cts-pins {
pins = "gpio32";
function = "qup10";
};
- qup_uart8_rts: qup-uart8-rts {
+ qup_uart8_rts: qup-uart8-rts-pins {
pins = "gpio33";
function = "qup10";
};
- qup_uart8_tx: qup-uart8-tx {
+ qup_uart8_tx: qup-uart8-tx-pins {
pins = "gpio34";
function = "qup10";
};
- qup_uart8_rx: qup-uart8-rx {
+ qup_uart8_rx: qup-uart8-rx-pins {
pins = "gpio35";
function = "qup10";
};
- qup_uart9_cts: qup-uart9-cts {
+ qup_uart9_cts: qup-uart9-cts-pins {
pins = "gpio36";
function = "qup11";
};
- qup_uart9_rts: qup-uart9-rts {
+ qup_uart9_rts: qup-uart9-rts-pins {
pins = "gpio37";
function = "qup11";
};
- qup_uart9_tx: qup-uart9-tx {
+ qup_uart9_tx: qup-uart9-tx-pins {
pins = "gpio38";
function = "qup11";
};
- qup_uart9_rx: qup-uart9-rx {
+ qup_uart9_rx: qup-uart9-rx-pins {
pins = "gpio39";
function = "qup11";
};
- qup_uart10_cts: qup-uart10-cts {
+ qup_uart10_cts: qup-uart10-cts-pins {
pins = "gpio40";
function = "qup12";
};
- qup_uart10_rts: qup-uart10-rts {
+ qup_uart10_rts: qup-uart10-rts-pins {
pins = "gpio41";
function = "qup12";
};
- qup_uart10_tx: qup-uart10-tx {
+ qup_uart10_tx: qup-uart10-tx-pins {
pins = "gpio42";
function = "qup12";
};
- qup_uart10_rx: qup-uart10-rx {
+ qup_uart10_rx: qup-uart10-rx-pins {
pins = "gpio43";
function = "qup12";
};
- qup_uart11_cts: qup-uart11-cts {
+ qup_uart11_cts: qup-uart11-cts-pins {
pins = "gpio44";
function = "qup13";
};
- qup_uart11_rts: qup-uart11-rts {
+ qup_uart11_rts: qup-uart11-rts-pins {
pins = "gpio45";
function = "qup13";
};
- qup_uart11_tx: qup-uart11-tx {
+ qup_uart11_tx: qup-uart11-tx-pins {
pins = "gpio46";
function = "qup13";
};
- qup_uart11_rx: qup-uart11-rx {
+ qup_uart11_rx: qup-uart11-rx-pins {
pins = "gpio47";
function = "qup13";
};
- qup_uart12_cts: qup-uart12-cts {
+ qup_uart12_cts: qup-uart12-cts-pins {
pins = "gpio48";
function = "qup14";
};
- qup_uart12_rts: qup-uart12-rts {
+ qup_uart12_rts: qup-uart12-rts-pins {
pins = "gpio49";
function = "qup14";
};
- qup_uart12_tx: qup-uart12-tx {
+ qup_uart12_tx: qup-uart12-tx-pins {
pins = "gpio50";
function = "qup14";
};
- qup_uart12_rx: qup-uart12-rx {
+ qup_uart12_rx: qup-uart12-rx-pins {
pins = "gpio51";
function = "qup14";
};
- qup_uart13_cts: qup-uart13-cts {
+ qup_uart13_cts: qup-uart13-cts-pins {
pins = "gpio52";
function = "qup15";
};
- qup_uart13_rts: qup-uart13-rts {
+ qup_uart13_rts: qup-uart13-rts-pins {
pins = "gpio53";
function = "qup15";
};
- qup_uart13_tx: qup-uart13-tx {
+ qup_uart13_tx: qup-uart13-tx-pins {
pins = "gpio54";
function = "qup15";
};
- qup_uart13_rx: qup-uart13-rx {
+ qup_uart13_rx: qup-uart13-rx-pins {
pins = "gpio55";
function = "qup15";
};
- qup_uart14_cts: qup-uart14-cts {
+ qup_uart14_cts: qup-uart14-cts-pins {
pins = "gpio56";
function = "qup16";
};
- qup_uart14_rts: qup-uart14-rts {
+ qup_uart14_rts: qup-uart14-rts-pins {
pins = "gpio57";
function = "qup16";
};
- qup_uart14_tx: qup-uart14-tx {
+ qup_uart14_tx: qup-uart14-tx-pins {
pins = "gpio58";
function = "qup16";
};
- qup_uart14_rx: qup-uart14-rx {
+ qup_uart14_rx: qup-uart14-rx-pins {
pins = "gpio59";
function = "qup16";
};
- qup_uart15_cts: qup-uart15-cts {
+ qup_uart15_cts: qup-uart15-cts-pins {
pins = "gpio60";
function = "qup17";
};
- qup_uart15_rts: qup-uart15-rts {
+ qup_uart15_rts: qup-uart15-rts-pins {
pins = "gpio61";
function = "qup17";
};
- qup_uart15_tx: qup-uart15-tx {
+ qup_uart15_tx: qup-uart15-tx-pins {
pins = "gpio62";
function = "qup17";
};
- qup_uart15_rx: qup-uart15-rx {
+ qup_uart15_rx: qup-uart15-rx-pins {
pins = "gpio63";
function = "qup17";
};
- sdc1_clk: sdc1-clk {
+ sdc1_clk: sdc1-clk-pins {
pins = "sdc1_clk";
};
- sdc1_cmd: sdc1-cmd {
+ sdc1_cmd: sdc1-cmd-pins {
pins = "sdc1_cmd";
};
- sdc1_data: sdc1-data {
+ sdc1_data: sdc1-data-pins {
pins = "sdc1_data";
};
- sdc1_rclk: sdc1-rclk {
+ sdc1_rclk: sdc1-rclk-pins {
pins = "sdc1_rclk";
};
- sdc1_clk_sleep: sdc1-clk-sleep {
+ sdc1_clk_sleep: sdc1-clk-sleep-pins {
pins = "sdc1_clk";
drive-strength = <2>;
bias-bus-hold;
};
- sdc1_cmd_sleep: sdc1-cmd-sleep {
+ sdc1_cmd_sleep: sdc1-cmd-sleep-pins {
pins = "sdc1_cmd";
drive-strength = <2>;
bias-bus-hold;
};
- sdc1_data_sleep: sdc1-data-sleep {
+ sdc1_data_sleep: sdc1-data-sleep-pins {
pins = "sdc1_data";
drive-strength = <2>;
bias-bus-hold;
};
- sdc1_rclk_sleep: sdc1-rclk-sleep {
+ sdc1_rclk_sleep: sdc1-rclk-sleep-pins {
pins = "sdc1_rclk";
drive-strength = <2>;
bias-bus-hold;
};
- sdc2_clk: sdc2-clk {
+ sdc2_clk: sdc2-clk-pins {
pins = "sdc2_clk";
};
- sdc2_cmd: sdc2-cmd {
+ sdc2_cmd: sdc2-cmd-pins {
pins = "sdc2_cmd";
};
- sdc2_data: sdc2-data {
+ sdc2_data: sdc2-data-pins {
pins = "sdc2_data";
};
- sdc2_clk_sleep: sdc2-clk-sleep {
+ sdc2_clk_sleep: sdc2-clk-sleep-pins {
pins = "sdc2_clk";
drive-strength = <2>;
bias-bus-hold;
};
- sdc2_cmd_sleep: sdc2-cmd-sleep {
+ sdc2_cmd_sleep: sdc2-cmd-sleep-pins {
pins = "sdc2_cmd";
drive-strength = <2>;
bias-bus-hold;
};
- sdc2_data_sleep: sdc2-data-sleep {
+ sdc2_data_sleep: sdc2-data-sleep-pins {
pins = "sdc2_data";
drive-strength = <2>;
bias-bus-hold;
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 09:52:44 +0000