diff options
Diffstat (limited to 'dts/src/arm64/renesas/r8a77960.dtsi')
-rw-r--r-- | dts/src/arm64/renesas/r8a77960.dtsi | 216 |
1 files changed, 156 insertions, 60 deletions
diff --git a/dts/src/arm64/renesas/r8a77960.dtsi b/dts/src/arm64/renesas/r8a77960.dtsi index 31282367d3..a631ead171 100644 --- a/dts/src/arm64/renesas/r8a77960.dtsi +++ b/dts/src/arm64/renesas/r8a77960.dtsi @@ -9,24 +9,11 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7796-sysc.h> -#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4 - / { compatible = "renesas,r8a7796"; #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. @@ -57,36 +44,35 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; }; opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; + opp-suspend; }; opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1700000000 { opp-hz = /bits/ 64 <1700000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; @@ -96,7 +82,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; @@ -333,6 +319,7 @@ compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -459,7 +446,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7796"; reg = <0 0xe6060000 0 0x50c>; }; @@ -585,6 +572,71 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a7796", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a7796", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a7796", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a7796", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a7796", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; @@ -997,7 +1049,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -1005,7 +1057,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -1013,7 +1065,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -1021,7 +1073,7 @@ #iommu-cells = <1>; }; - ipmmu_ir: mmu@ff8b0000 { + ipmmu_ir: iommu@ff8b0000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xff8b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 3>; @@ -1029,7 +1081,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xe67b0000 0 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, @@ -1038,7 +1090,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -1046,7 +1098,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 5>; @@ -1054,7 +1106,7 @@ #iommu-cells = <1>; }; - ipmmu_pv1: mmu@fd950000 { + ipmmu_pv1: iommu@fd950000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xfd950000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -1062,7 +1114,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 7>; @@ -1070,7 +1122,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 8>; @@ -1078,7 +1130,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 9>; @@ -1123,9 +1175,12 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; @@ -1170,6 +1225,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A7796_CLK_CANFD>, <&can_clk>; @@ -1810,7 +1866,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; @@ -1821,12 +1877,12 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -1845,7 +1901,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7796_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", @@ -2133,7 +2189,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { @@ -2215,6 +2271,18 @@ }; }; + mlp: mlp@ec520000 { + compatible = "renesas,r8a7796-mlp", + "renesas,rcar-gen3-mlp"; + reg = <0 0xec520000 0 0x800>; + interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 802>; + status = "disabled"; + }; + audma0: dma-controller@ec700000 { compatible = "renesas,dmac-r8a7796", "renesas,rcar-dmac"; @@ -2394,12 +2462,13 @@ status = "disabled"; }; - sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a7796", "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 314>; + clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 314>; @@ -2407,12 +2476,13 @@ status = "disabled"; }; - sdhi1: sd@ee120000 { + sdhi1: mmc@ee120000 { compatible = "renesas,sdhi-r8a7796", "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 313>; + clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 313>; @@ -2420,12 +2490,13 @@ status = "disabled"; }; - sdhi2: sd@ee140000 { + sdhi2: mmc@ee140000 { compatible = "renesas,sdhi-r8a7796", "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 312>; + clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 312>; @@ -2433,12 +2504,13 @@ status = "disabled"; }; - sdhi3: sd@ee160000 { + sdhi3: mmc@ee160000 { compatible = "renesas,sdhi-r8a7796", "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 311>; + clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>; + clock-names = "core", "clkh"; max-frequency = <200000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 311>; @@ -2446,6 +2518,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a7796-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -2475,8 +2563,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; @@ -2487,6 +2575,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2502,8 +2592,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; @@ -2514,6 +2604,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2694,6 +2786,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; @@ -2749,6 +2845,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; @@ -2844,8 +2944,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; @@ -2882,8 +2980,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; @@ -2895,7 +2991,7 @@ }; thermal-zones { - sensor_thermal1: sensor-thermal1 { + sensor1_thermal: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -2910,7 +3006,7 @@ }; }; - sensor_thermal2: sensor-thermal2 { + sensor2_thermal: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -2925,7 +3021,7 @@ }; }; - sensor_thermal3: sensor-thermal3 { + sensor3_thermal: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; |