diff options
Diffstat (limited to 'dts/src/arm64/renesas')
24 files changed, 294 insertions, 20 deletions
diff --git a/dts/src/arm64/renesas/beacon-renesom-baseboard.dtsi b/dts/src/arm64/renesas/beacon-renesom-baseboard.dtsi index d8046fedf9..e3c8b2fe14 100644 --- a/dts/src/arm64/renesas/beacon-renesom-baseboard.dtsi +++ b/dts/src/arm64/renesas/beacon-renesom-baseboard.dtsi @@ -271,12 +271,12 @@ &ehci0 { dr_mode = "otg"; status = "okay"; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>; }; &ehci1 { status = "okay"; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>; }; &hdmi0 { diff --git a/dts/src/arm64/renesas/beacon-renesom-som.dtsi b/dts/src/arm64/renesas/beacon-renesom-som.dtsi index 8d3a4d6ee8..090dc9c4f5 100644 --- a/dts/src/arm64/renesas/beacon-renesom-som.dtsi +++ b/dts/src/arm64/renesas/beacon-renesom-som.dtsi @@ -53,6 +53,8 @@ phy-handle = <&phy0>; rx-internal-delay-ps = <1800>; tx-internal-delay-ps = <2000>; + clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>; + clock-names = "fck", "refclk"; status = "okay"; phy0: ethernet-phy@0 { @@ -319,8 +321,10 @@ status = "okay"; }; -&usb_extal_clk { - clock-frequency = <50000000>; +&usb2_clksel { + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&versaclock5 3>, <&usb3s0_clk>; + status = "okay"; }; &usb3s0_clk { diff --git a/dts/src/arm64/renesas/r8a774a1.dtsi b/dts/src/arm64/renesas/r8a774a1.dtsi index 46f8dbf689..78c121a89f 100644 --- a/dts/src/arm64/renesas/r8a774a1.dtsi +++ b/dts/src/arm64/renesas/r8a774a1.dtsi @@ -76,6 +76,7 @@ opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <820000>; clock-latency-ns = <300000>; + opp-suspend; }; }; @@ -1127,6 +1128,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/dts/src/arm64/renesas/r8a774b1.dtsi b/dts/src/arm64/renesas/r8a774b1.dtsi index d16a4be5ef..28c612ce49 100644 --- a/dts/src/arm64/renesas/r8a774b1.dtsi +++ b/dts/src/arm64/renesas/r8a774b1.dtsi @@ -1001,6 +1001,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/dts/src/arm64/renesas/r8a774c0.dtsi b/dts/src/arm64/renesas/r8a774c0.dtsi index 1aef34447a..a5d4dce847 100644 --- a/dts/src/arm64/renesas/r8a774c0.dtsi +++ b/dts/src/arm64/renesas/r8a774c0.dtsi @@ -957,6 +957,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/dts/src/arm64/renesas/r8a774e1.dtsi b/dts/src/arm64/renesas/r8a774e1.dtsi index 1f51237ab0..379a130027 100644 --- a/dts/src/arm64/renesas/r8a774e1.dtsi +++ b/dts/src/arm64/renesas/r8a774e1.dtsi @@ -1230,6 +1230,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/dts/src/arm64/renesas/r8a77951.dtsi b/dts/src/arm64/renesas/r8a77951.dtsi index 85d66d1546..2e4c18b8ee 100644 --- a/dts/src/arm64/renesas/r8a77951.dtsi +++ b/dts/src/arm64/renesas/r8a77951.dtsi @@ -1312,6 +1312,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/dts/src/arm64/renesas/r8a77960.dtsi b/dts/src/arm64/renesas/r8a77960.dtsi index 12476e354d..2bd8169735 100644 --- a/dts/src/arm64/renesas/r8a77960.dtsi +++ b/dts/src/arm64/renesas/r8a77960.dtsi @@ -63,18 +63,19 @@ opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; }; opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; + opp-suspend; }; opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; @@ -1188,6 +1189,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/dts/src/arm64/renesas/r8a77961.dtsi b/dts/src/arm64/renesas/r8a77961.dtsi index d980476842..91b501e012 100644 --- a/dts/src/arm64/renesas/r8a77961.dtsi +++ b/dts/src/arm64/renesas/r8a77961.dtsi @@ -52,18 +52,19 @@ opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; }; opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; + opp-suspend; }; opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; @@ -559,10 +560,19 @@ }; intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a77961", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; - /* placeholder */ + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; tmu0: timer@e61e0000 { @@ -1144,6 +1154,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/dts/src/arm64/renesas/r8a77965.dtsi b/dts/src/arm64/renesas/r8a77965.dtsi index dcb9df861d..ad69da362a 100644 --- a/dts/src/arm64/renesas/r8a77965.dtsi +++ b/dts/src/arm64/renesas/r8a77965.dtsi @@ -1050,6 +1050,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/dts/src/arm64/renesas/r8a77970-eagle.dts b/dts/src/arm64/renesas/r8a77970-eagle.dts index 874a7fc273..5c84681703 100644 --- a/dts/src/arm64/renesas/r8a77970-eagle.dts +++ b/dts/src/arm64/renesas/r8a77970-eagle.dts @@ -73,6 +73,12 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + x1_clk: x1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; }; &avb { @@ -104,6 +110,8 @@ }; &du { + clocks = <&cpg CPG_MOD 724>, <&x1_clk>; + clock-names = "du.0", "dclkin.0"; status = "okay"; }; diff --git a/dts/src/arm64/renesas/r8a77970-v3msk.dts b/dts/src/arm64/renesas/r8a77970-v3msk.dts index 7417cf5fea..2426e53312 100644 --- a/dts/src/arm64/renesas/r8a77970-v3msk.dts +++ b/dts/src/arm64/renesas/r8a77970-v3msk.dts @@ -59,7 +59,7 @@ memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; + reg = <0x0 0x48000000 0x0 0x78000000>; }; osc5_clk: osc5-clock { diff --git a/dts/src/arm64/renesas/r8a77970.dtsi b/dts/src/arm64/renesas/r8a77970.dtsi index e8f6352c36..517892cf62 100644 --- a/dts/src/arm64/renesas/r8a77970.dtsi +++ b/dts/src/arm64/renesas/r8a77970.dtsi @@ -612,6 +612,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/dts/src/arm64/renesas/r8a77980-condor.dts b/dts/src/arm64/renesas/r8a77980-condor.dts index 04d47c0c9b..7bde0a549c 100644 --- a/dts/src/arm64/renesas/r8a77980-condor.dts +++ b/dts/src/arm64/renesas/r8a77980-condor.dts @@ -210,7 +210,7 @@ &mmc0 { pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins_uhs>; + pinctrl-1 = <&mmc_pins>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <&d3_3v>; @@ -255,12 +255,6 @@ mmc_pins: mmc { groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; function = "mmc"; - power-source = <3300>; - }; - - mmc_pins_uhs: mmc_uhs { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; power-source = <1800>; }; diff --git a/dts/src/arm64/renesas/r8a77980.dtsi b/dts/src/arm64/renesas/r8a77980.dtsi index 7b51d464de..6347d15e66 100644 --- a/dts/src/arm64/renesas/r8a77980.dtsi +++ b/dts/src/arm64/renesas/r8a77980.dtsi @@ -664,6 +664,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/dts/src/arm64/renesas/r8a77990.dtsi b/dts/src/arm64/renesas/r8a77990.dtsi index 0eaea58f42..4d0304bc97 100644 --- a/dts/src/arm64/renesas/r8a77990.dtsi +++ b/dts/src/arm64/renesas/r8a77990.dtsi @@ -1000,6 +1000,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/dts/src/arm64/renesas/r8a77995.dtsi b/dts/src/arm64/renesas/r8a77995.dtsi index 2319271c88..84dba37193 100644 --- a/dts/src/arm64/renesas/r8a77995.dtsi +++ b/dts/src/arm64/renesas/r8a77995.dtsi @@ -760,6 +760,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/dts/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi b/dts/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi index 14d3db5d6c..f791c76f1b 100644 --- a/dts/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi +++ b/dts/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi @@ -6,6 +6,27 @@ */ &i2c0 { + pca9654_a: gpio@21 { + compatible = "onnn,pca9654"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9654_b: gpio@22 { + compatible = "onnn,pca9654"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9654_c: gpio@23 { + compatible = "onnn,pca9654"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + eeprom@52 { compatible = "rohm,br24g01", "atmel,24c01"; label = "csi-dsi-sub-board-id"; diff --git a/dts/src/arm64/renesas/r8a779a0.dtsi b/dts/src/arm64/renesas/r8a779a0.dtsi index 70b3604e56..78ca75f619 100644 --- a/dts/src/arm64/renesas/r8a779a0.dtsi +++ b/dts/src/arm64/renesas/r8a779a0.dtsi @@ -618,6 +618,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 211>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 211>; phy-mode = "rgmii"; @@ -665,6 +666,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 212>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 212>; phy-mode = "rgmii"; @@ -712,6 +714,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 213>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 213>; phy-mode = "rgmii"; @@ -759,6 +762,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 214>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 214>; phy-mode = "rgmii"; @@ -806,6 +810,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 215>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 215>; phy-mode = "rgmii"; @@ -853,6 +858,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 216>; phy-mode = "rgmii"; @@ -1096,7 +1102,6 @@ <0x0 0xf1060000 0 0x110000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; }; fcpvd0: fcp@fea10000 { diff --git a/dts/src/arm64/renesas/r9a07g044.dtsi b/dts/src/arm64/renesas/r9a07g044.dtsi new file mode 100644 index 0000000000..734c8adece --- /dev/null +++ b/dts/src/arm64/renesas/r9a07g044.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r9a07g044-cpg.h> + +/ { + compatible = "renesas,r9a07g044"; + #address-cells = <2>; + #size-cells = <2>; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_CLK_SCIF0>; + status = "disabled"; + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g044-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g044-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + status = "disabled"; + }; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x11900000 0 0x40000>, + <0x0 0x11940000 0 0x60000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/dts/src/arm64/renesas/r9a07g044l1.dtsi b/dts/src/arm64/renesas/r9a07g044l1.dtsi new file mode 100644 index 0000000000..9d89d45903 --- /dev/null +++ b/dts/src/arm64/renesas/r9a07g044l1.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L R9A07G044L1 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044.dtsi" + +/ { + compatible = "renesas,r9a07g044l1", "renesas,r9a07g044"; + + cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + }; + + timer { + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/dts/src/arm64/renesas/r9a07g044l2-smarc.dts b/dts/src/arm64/renesas/r9a07g044l2-smarc.dts new file mode 100644 index 0000000000..d3f72ec62f --- /dev/null +++ b/dts/src/arm64/renesas/r9a07g044l2-smarc.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L SMARC EVK board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044l2.dtsi" +#include "rzg2l-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g044l2"; + compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; +}; diff --git a/dts/src/arm64/renesas/r9a07g044l2.dtsi b/dts/src/arm64/renesas/r9a07g044l2.dtsi new file mode 100644 index 0000000000..91dc10b2cd --- /dev/null +++ b/dts/src/arm64/renesas/r9a07g044l2.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L R9A07G044L2 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044.dtsi" + +/ { + compatible = "renesas,r9a07g044l2", "renesas,r9a07g044"; +}; diff --git a/dts/src/arm64/renesas/rzg2l-smarc.dtsi b/dts/src/arm64/renesas/rzg2l-smarc.dtsi new file mode 100644 index 0000000000..adcd4f5051 --- /dev/null +++ b/dts/src/arm64/renesas/rzg2l-smarc.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L SMARC EVK common parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +&scif0 { + status = "okay"; +}; |