diff options
Diffstat (limited to 'dts/src/arm64/rockchip/rk3308.dtsi')
| -rw-r--r-- | dts/src/arm64/rockchip/rk3308.dtsi | 61 |
1 files changed, 53 insertions, 8 deletions
diff --git a/dts/src/arm64/rockchip/rk3308.dtsi b/dts/src/arm64/rockchip/rk3308.dtsi index a185901aba..cfc0a87b51 100644 --- a/dts/src/arm64/rockchip/rk3308.dtsi +++ b/dts/src/arm64/rockchip/rk3308.dtsi @@ -20,6 +20,11 @@ #size-cells = <2>; aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -96,10 +101,12 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; - cpu0_opp_table: cpu0-opp-table { + cpu0_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -731,13 +738,25 @@ status = "disabled"; }; + sfc: spi@ff4c0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xff4c0000 0x0 0x4000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; + pinctrl-names = "default"; + status = "disabled"; + }; + cru: clock-controller@ff500000 { compatible = "rockchip,rk3308-cru"; reg = <0x0 0xff500000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - rockchip,grf = <&grf>; - assigned-clocks = <&cru SCLK_RTC32K>; assigned-clock-rates = <32768>; }; @@ -779,7 +798,7 @@ #size-cells = <2>; ranges; - gpio0: gpio0@ff220000 { + gpio0: gpio@ff220000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff220000 0x0 0x100>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; @@ -790,7 +809,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@ff230000 { + gpio1: gpio@ff230000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff230000 0x0 0x100>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; @@ -801,7 +820,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@ff240000 { + gpio2: gpio@ff240000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff240000 0x0 0x100>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; @@ -812,7 +831,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@ff250000 { + gpio3: gpio@ff250000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff250000 0x0 0x100>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; @@ -823,7 +842,7 @@ #interrupt-cells = <2>; }; - gpio4: gpio4@ff260000 { + gpio4: gpio@ff260000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff260000 0x0 0x100>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; @@ -1004,6 +1023,32 @@ }; }; + sfc { + sfc_bus4: sfc-bus4 { + rockchip,pins = + <3 RK_PA0 3 &pcfg_pull_none>, + <3 RK_PA1 3 &pcfg_pull_none>, + <3 RK_PA2 3 &pcfg_pull_none>, + <3 RK_PA3 3 &pcfg_pull_none>; + }; + + sfc_bus2: sfc-bus2 { + rockchip,pins = + <3 RK_PA0 3 &pcfg_pull_none>, + <3 RK_PA1 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = + <3 RK_PA4 3 &pcfg_pull_none>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = + <3 RK_PA5 3 &pcfg_pull_none>; + }; + }; + gmac { rmii_pins: rmii-pins { rockchip,pins = |