diff options
Diffstat (limited to 'dts/src/arm64/rockchip/rk3568-bpi-r2-pro.dts')
| -rw-r--r-- | dts/src/arm64/rockchip/rk3568-bpi-r2-pro.dts | 129 |
1 files changed, 123 insertions, 6 deletions
diff --git a/dts/src/arm64/rockchip/rk3568-bpi-r2-pro.dts b/dts/src/arm64/rockchip/rk3568-bpi-r2-pro.dts index 93d383b8be..c282f6e799 100644 --- a/dts/src/arm64/rockchip/rk3568-bpi-r2-pro.dts +++ b/dts/src/arm64/rockchip/rk3568-bpi-r2-pro.dts @@ -46,7 +46,7 @@ }; }; - dc_12v: dc-12v { + dc_12v: dc-12v-regulator { compatible = "regulator-fixed"; regulator-name = "dc_12v"; regulator-always-on; @@ -66,7 +66,7 @@ }; }; - vcc3v3_sys: vcc3v3-sys { + vcc3v3_sys: vcc3v3-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; regulator-always-on; @@ -76,7 +76,7 @@ vin-supply = <&dc_12v>; }; - vcc5v0_sys: vcc5v0-sys { + vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; regulator-always-on; @@ -86,7 +86,67 @@ vin-supply = <&dc_12v>; }; - vcc5v0_usb: vcc5v0_usb { + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* pi6c pcie clock generator feeds both ports */ + vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_enable_h>; + startup-delay-us = <50000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + + /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ + vcc3v3_ngff: vcc3v3-ngff-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_ngff"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ngffpcie_enable_h>; + startup-delay-us = <50000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usb"; regulator-always-on; @@ -96,7 +156,7 @@ vin-supply = <&dc_12v>; }; - vcc5v0_usb_host: vcc5v0-usb-host { + vcc5v0_usb_host: vcc5v0-usb-host-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; @@ -108,7 +168,7 @@ vin-supply = <&vcc5v0_usb>; }; - vcc5v0_usb_otg: vcc5v0-usb-otg { + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; @@ -513,6 +573,32 @@ }; }; +&pcie30phy { + data-lanes = <1 2>; + phy-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pcie3x1 { + /* M.2 slot */ + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&ngffpcie_reset_h>; + reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_ngff>; + status = "okay"; +}; + +&pcie3x2 { + /* mPCIe slot */ + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_reset_h>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + &pinctrl { leds { blue_led_pin: blue-led-pin { @@ -529,6 +615,24 @@ }; }; + pcie { + minipcie_enable_h: minipcie-enable-h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; + }; + + ngffpcie_enable_h: ngffpcie-enable-h { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; + }; + + minipcie_reset_h: minipcie-reset-h { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; + }; + + ngffpcie_reset_h: ngffpcie-reset-h { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; + }; + }; + pmic { pmic_int: pmic_int { rockchip,pins = @@ -708,6 +812,19 @@ status = "okay"; }; +&usb2phy1 { + /* USB for PCIe/M2 */ + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; + &vop { assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; |