diff options
Diffstat (limited to 'dts/src/arm64/ti/k3-j721e.dtsi')
| -rw-r--r-- | dts/src/arm64/ti/k3-j721e.dtsi | 32 |
1 files changed, 10 insertions, 22 deletions
diff --git a/dts/src/arm64/ti/k3-j721e.dtsi b/dts/src/arm64/ti/k3-j721e.dtsi index 0e23886c9f..5a72c518ce 100644 --- a/dts/src/arm64/ti/k3-j721e.dtsi +++ b/dts/src/arm64/ti/k3-j721e.dtsi @@ -1,15 +1,16 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721E SoC Family * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/k3.h> #include <dt-bindings/soc/ti,sci_pm_domain.h> +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 J721E SoC"; compatible = "ti,j721e"; @@ -17,25 +18,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - serial9 = &main_uart7; - serial10 = &main_uart8; - serial11 = &main_uart9; - ethernet0 = &cpsw_port1; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - mmc2 = &main_sdhci2; - }; - chosen { }; cpus { @@ -86,6 +68,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -95,6 +78,7 @@ msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; firmware { @@ -129,11 +113,13 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ + <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ @@ -181,6 +167,8 @@ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ }; }; + + #include "k3-j721e-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ |