diff options
Diffstat (limited to 'dts/src/arm64/xilinx/zynqmp-clk-ccf.dtsi')
| -rw-r--r-- | dts/src/arm64/xilinx/zynqmp-clk-ccf.dtsi | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/dts/src/arm64/xilinx/zynqmp-clk-ccf.dtsi b/dts/src/arm64/xilinx/zynqmp-clk-ccf.dtsi index cf52952247..1e0b1bca7c 100644 --- a/dts/src/arm64/xilinx/zynqmp-clk-ccf.dtsi +++ b/dts/src/arm64/xilinx/zynqmp-clk-ccf.dtsi @@ -2,7 +2,7 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -40,6 +40,17 @@ }; }; +&zynqmp_firmware { + zynqmp_clk: clock-controller { + #clock-cells = <1>; + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + }; +}; + &can0 { clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; }; |