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-rw-r--r--dts/src/mips/brcm/bcm7125.dtsi7
-rw-r--r--dts/src/mips/brcm/bcm7346.dtsi62
-rw-r--r--dts/src/mips/brcm/bcm7358.dtsi17
-rw-r--r--dts/src/mips/brcm/bcm7360.dtsi62
-rw-r--r--dts/src/mips/brcm/bcm7362.dtsi62
-rw-r--r--dts/src/mips/brcm/bcm7420.dtsi7
-rw-r--r--dts/src/mips/brcm/bcm7425.dtsi89
-rw-r--r--dts/src/mips/brcm/bcm7435.dtsi89
-rw-r--r--dts/src/mips/brcm/bcm97125cbmb.dts4
-rw-r--r--dts/src/mips/brcm/bcm97346dbsmb.dts8
-rw-r--r--dts/src/mips/brcm/bcm97358svmb.dts8
-rw-r--r--dts/src/mips/brcm/bcm97360svmb.dts8
-rw-r--r--dts/src/mips/brcm/bcm97362svmb.dts8
-rw-r--r--dts/src/mips/brcm/bcm97420c.dts4
-rw-r--r--dts/src/mips/brcm/bcm97425svmb.dts8
-rw-r--r--dts/src/mips/brcm/bcm97435svmb.dts8
-rw-r--r--dts/src/mips/img/boston.dts2
-rw-r--r--dts/src/mips/ingenic/ci20.dts8
-rw-r--r--dts/src/mips/mscc/ocelot.dtsi117
-rw-r--r--dts/src/mips/mscc/ocelot_pcb123.dts27
20 files changed, 600 insertions, 5 deletions
diff --git a/dts/src/mips/brcm/bcm7125.dtsi b/dts/src/mips/brcm/bcm7125.dtsi
index 2f9ef565e5..5bf77b6fcc 100644
--- a/dts/src/mips/brcm/bcm7125.dtsi
+++ b/dts/src/mips/brcm/bcm7125.dtsi
@@ -198,6 +198,13 @@
status = "disabled";
};
+ watchdog: watchdog@4067e8 {
+ clocks = <&upg_clk>;
+ compatible = "brcm,bcm7038-wdt";
+ reg = <0x4067e8 0x14>;
+ status = "disabled";
+ };
+
upg_gio: gpio@406700 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406700 0x80>;
diff --git a/dts/src/mips/brcm/bcm7346.dtsi b/dts/src/mips/brcm/bcm7346.dtsi
index 02e426fe60..2afa0dada5 100644
--- a/dts/src/mips/brcm/bcm7346.dtsi
+++ b/dts/src/mips/brcm/bcm7346.dtsi
@@ -233,6 +233,13 @@
status = "disabled";
};
+ watchdog: watchdog@4067e8 {
+ clocks = <&upg_clk>;
+ compatible = "brcm,bcm7038-wdt";
+ reg = <0x4067e8 0x14>;
+ status = "disabled";
+ };
+
aon_pm_l2_intc: interrupt-controller@408440 {
compatible = "brcm,l2-intc";
reg = <0x408440 0x30>;
@@ -243,6 +250,17 @@
brcm,irq-can-wake;
};
+ aon_ctrl: syscon@408000 {
+ compatible = "brcm,brcmstb-aon-ctrl";
+ reg = <0x408000 0x100>, <0x408200 0x200>;
+ reg-names = "aon-ctrl", "aon-sram";
+ };
+
+ timers: timer@4067c0 {
+ compatible = "brcm,brcmstb-timers";
+ reg = <0x4067c0 0x40>;
+ };
+
upg_gio: gpio@406700 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406700 0x60>;
@@ -483,5 +501,49 @@
interrupt-names = "mspi_done";
status = "disabled";
};
+
+ waketimer: waketimer@408e80 {
+ compatible = "brcm,brcmstb-waketimer";
+ reg = <0x408e80 0x14>;
+ interrupts = <0x3>;
+ interrupt-parent = <&aon_pm_l2_intc>;
+ interrupt-names = "timer";
+ clocks = <&upg_clk>;
+ status = "disabled";
+ };
+ };
+
+ memory_controllers {
+ compatible = "simple-bus";
+ ranges = <0x0 0x103b0000 0xa000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory-controller@0 {
+ compatible = "brcm,brcmstb-memc", "simple-bus";
+ ranges = <0x0 0x0 0xa000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memc-arb@1000 {
+ compatible = "brcm,brcmstb-memc-arb";
+ reg = <0x1000 0x248>;
+ };
+
+ memc-ddr@2000 {
+ compatible = "brcm,brcmstb-memc-ddr";
+ reg = <0x2000 0x300>;
+ };
+
+ ddr-phy@6000 {
+ compatible = "brcm,brcmstb-ddr-phy";
+ reg = <0x6000 0xc8>;
+ };
+
+ shimphy@8000 {
+ compatible = "brcm,brcmstb-ddr-shimphy";
+ reg = <0x8000 0x13c>;
+ };
+ };
};
};
diff --git a/dts/src/mips/brcm/bcm7358.dtsi b/dts/src/mips/brcm/bcm7358.dtsi
index 1089d6ebc8..6375fc77f3 100644
--- a/dts/src/mips/brcm/bcm7358.dtsi
+++ b/dts/src/mips/brcm/bcm7358.dtsi
@@ -217,6 +217,13 @@
status = "disabled";
};
+ watchdog: watchdog@4066a8 {
+ clocks = <&upg_clk>;
+ compatible = "brcm,bcm7038-wdt";
+ reg = <0x4066a8 0x14>;
+ status = "disabled";
+ };
+
aon_pm_l2_intc: interrupt-controller@408240 {
compatible = "brcm,l2-intc";
reg = <0x408240 0x30>;
@@ -362,5 +369,15 @@
interrupt-names = "mspi_done";
status = "disabled";
};
+
+ waketimer: waketimer@408e80 {
+ compatible = "brcm,brcmstb-waketimer";
+ reg = <0x408e80 0x14>;
+ interrupts = <0x3>;
+ interrupt-parent = <&aon_pm_l2_intc>;
+ interrupt-names = "timer";
+ clocks = <&upg_clk>;
+ status = "disabled";
+ };
};
};
diff --git a/dts/src/mips/brcm/bcm7360.dtsi b/dts/src/mips/brcm/bcm7360.dtsi
index 4b87ebec40..a57cacea91 100644
--- a/dts/src/mips/brcm/bcm7360.dtsi
+++ b/dts/src/mips/brcm/bcm7360.dtsi
@@ -209,6 +209,13 @@
status = "disabled";
};
+ watchdog: watchdog@4066a8 {
+ clocks = <&upg_clk>;
+ compatible = "brcm,bcm7038-wdt";
+ reg = <0x4066a8 0x14>;
+ status = "disabled";
+ };
+
aon_pm_l2_intc: interrupt-controller@408440 {
compatible = "brcm,l2-intc";
reg = <0x408440 0x30>;
@@ -219,6 +226,17 @@
brcm,irq-can-wake;
};
+ aon_ctrl: syscon@408000 {
+ compatible = "brcm,brcmstb-aon-ctrl";
+ reg = <0x408000 0x100>, <0x408200 0x200>;
+ reg-names = "aon-ctrl", "aon-sram";
+ };
+
+ timers: timer@406680 {
+ compatible = "brcm,brcmstb-timers";
+ reg = <0x406680 0x40>;
+ };
+
upg_gio: gpio@406500 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406500 0xa0>;
@@ -402,5 +420,49 @@
interrupt-names = "mspi_done";
status = "disabled";
};
+
+ waketimer: waketimer@408e80 {
+ compatible = "brcm,brcmstb-waketimer";
+ reg = <0x408e80 0x14>;
+ interrupts = <0x3>;
+ interrupt-parent = <&aon_pm_l2_intc>;
+ interrupt-names = "timer";
+ clocks = <&upg_clk>;
+ status = "disabled";
+ };
+ };
+
+ memory_controllers {
+ compatible = "simple-bus";
+ ranges = <0x0 0x103b0000 0xa000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory-controller@0 {
+ compatible = "brcm,brcmstb-memc", "simple-bus";
+ ranges = <0x0 0x0 0xa000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memc-arb@1000 {
+ compatible = "brcm,brcmstb-memc-arb";
+ reg = <0x1000 0x248>;
+ };
+
+ memc-ddr@2000 {
+ compatible = "brcm,brcmstb-memc-ddr";
+ reg = <0x2000 0x300>;
+ };
+
+ ddr-phy@6000 {
+ compatible = "brcm,brcmstb-ddr-phy";
+ reg = <0x6000 0xc8>;
+ };
+
+ shimphy@8000 {
+ compatible = "brcm,brcmstb-ddr-shimphy";
+ reg = <0x8000 0x13c>;
+ };
+ };
};
};
diff --git a/dts/src/mips/brcm/bcm7362.dtsi b/dts/src/mips/brcm/bcm7362.dtsi
index ca657df34b..728b9e9f84 100644
--- a/dts/src/mips/brcm/bcm7362.dtsi
+++ b/dts/src/mips/brcm/bcm7362.dtsi
@@ -205,6 +205,13 @@
status = "disabled";
};
+ watchdog: watchdog@4066a8 {
+ clocks = <&upg_clk>;
+ compatible = "brcm,bcm7038-wdt";
+ reg = <0x4066a8 0x14>;
+ status = "disabled";
+ };
+
aon_pm_l2_intc: interrupt-controller@408440 {
compatible = "brcm,l2-intc";
reg = <0x408440 0x30>;
@@ -215,6 +222,17 @@
brcm,irq-can-wake;
};
+ aon_ctrl: syscon@408000 {
+ compatible = "brcm,brcmstb-aon-ctrl";
+ reg = <0x408000 0x100>, <0x408200 0x200>;
+ reg-names = "aon-ctrl", "aon-sram";
+ };
+
+ timers: timer@406680 {
+ compatible = "brcm,brcmstb-timers";
+ reg = <0x406680 0x40>;
+ };
+
upg_gio: gpio@406500 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406500 0xa0>;
@@ -398,5 +416,49 @@
interrupt-names = "mspi_done";
status = "disabled";
};
+
+ waketimer: waketimer@408e80 {
+ compatible = "brcm,brcmstb-waketimer";
+ reg = <0x408e80 0x14>;
+ interrupts = <0x3>;
+ interrupt-parent = <&aon_pm_l2_intc>;
+ interrupt-names = "timer";
+ clocks = <&upg_clk>;
+ status = "disabled";
+ };
+ };
+
+ memory_controllers {
+ compatible = "simple-bus";
+ ranges = <0x0 0x103b0000 0xa000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory-controller@0 {
+ compatible = "brcm,brcmstb-memc", "simple-bus";
+ ranges = <0x0 0x0 0xa000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memc-arb@1000 {
+ compatible = "brcm,brcmstb-memc-arb";
+ reg = <0x1000 0x248>;
+ };
+
+ memc-ddr@2000 {
+ compatible = "brcm,brcmstb-memc-ddr";
+ reg = <0x2000 0x300>;
+ };
+
+ ddr-phy@6000 {
+ compatible = "brcm,brcmstb-ddr-phy";
+ reg = <0x6000 0xc8>;
+ };
+
+ shimphy@8000 {
+ compatible = "brcm,brcmstb-ddr-shimphy";
+ reg = <0x8000 0x13c>;
+ };
+ };
};
};
diff --git a/dts/src/mips/brcm/bcm7420.dtsi b/dts/src/mips/brcm/bcm7420.dtsi
index d262e11bc3..9540c27f12 100644
--- a/dts/src/mips/brcm/bcm7420.dtsi
+++ b/dts/src/mips/brcm/bcm7420.dtsi
@@ -214,6 +214,13 @@
status = "disabled";
};
+ watchdog: watchdog@4067e8 {
+ clocks = <&upg_clk>;
+ compatible = "brcm,bcm7038-wdt";
+ reg = <0x4067e8 0x14>;
+ status = "disabled";
+ };
+
upg_gio: gpio@406700 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406700 0x80>;
diff --git a/dts/src/mips/brcm/bcm7425.dtsi b/dts/src/mips/brcm/bcm7425.dtsi
index e4fb9b6e6d..410e61ebaf 100644
--- a/dts/src/mips/brcm/bcm7425.dtsi
+++ b/dts/src/mips/brcm/bcm7425.dtsi
@@ -232,6 +232,13 @@
status = "disabled";
};
+ watchdog: watchdog@4067e8 {
+ clocks = <&upg_clk>;
+ compatible = "brcm,bcm7038-wdt";
+ reg = <0x4067e8 0x14>;
+ status = "disabled";
+ };
+
aon_pm_l2_intc: interrupt-controller@408440 {
compatible = "brcm,l2-intc";
reg = <0x408440 0x30>;
@@ -242,6 +249,17 @@
brcm,irq-can-wake;
};
+ aon_ctrl: syscon@408000 {
+ compatible = "brcm,brcmstb-aon-ctrl";
+ reg = <0x408000 0x100>, <0x408200 0x200>;
+ reg-names = "aon-ctrl", "aon-sram";
+ };
+
+ timers: timer@4067c0 {
+ compatible = "brcm,brcmstb-timers";
+ reg = <0x4067c0 0x40>;
+ };
+
upg_gio: gpio@406700 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406700 0x80>;
@@ -494,5 +512,76 @@
interrupt-names = "mspi_done";
status = "disabled";
};
+
+ waketimer: waketimer@409580 {
+ compatible = "brcm,brcmstb-waketimer";
+ reg = <0x409580 0x14>;
+ interrupts = <0x3>;
+ interrupt-parent = <&aon_pm_l2_intc>;
+ interrupt-names = "timer";
+ clocks = <&upg_clk>;
+ status = "disabled";
+ };
+ };
+
+ memory_controllers {
+ compatible = "simple-bus";
+ ranges = <0x0 0x103b0000 0x1a000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory-controller@0 {
+ compatible = "brcm,brcmstb-memc", "simple-bus";
+ ranges = <0x0 0x0 0xa000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memc-arb@1000 {
+ compatible = "brcm,brcmstb-memc-arb";
+ reg = <0x1000 0x248>;
+ };
+
+ memc-ddr@2000 {
+ compatible = "brcm,brcmstb-memc-ddr";
+ reg = <0x2000 0x300>;
+ };
+
+ ddr-phy@6000 {
+ compatible = "brcm,brcmstb-ddr-phy";
+ reg = <0x6000 0xc8>;
+ };
+
+ shimphy@8000 {
+ compatible = "brcm,brcmstb-ddr-shimphy";
+ reg = <0x8000 0x13c>;
+ };
+ };
+
+ memory-controller@1 {
+ compatible = "brcm,brcmstb-memc", "simple-bus";
+ ranges = <0x0 0x10000 0xa000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memc-arb@1000 {
+ compatible = "brcm,brcmstb-memc-arb";
+ reg = <0x1000 0x248>;
+ };
+
+ memc-ddr@2000 {
+ compatible = "brcm,brcmstb-memc-ddr";
+ reg = <0x2000 0x300>;
+ };
+
+ ddr-phy@6000 {
+ compatible = "brcm,brcmstb-ddr-phy";
+ reg = <0x6000 0xc8>;
+ };
+
+ shimphy@8000 {
+ compatible = "brcm,brcmstb-ddr-shimphy";
+ reg = <0x8000 0x13c>;
+ };
+ };
};
};
diff --git a/dts/src/mips/brcm/bcm7435.dtsi b/dts/src/mips/brcm/bcm7435.dtsi
index 1484e8990e..8398b7f68b 100644
--- a/dts/src/mips/brcm/bcm7435.dtsi
+++ b/dts/src/mips/brcm/bcm7435.dtsi
@@ -247,6 +247,13 @@
status = "disabled";
};
+ watchdog: watchdog@4067e8 {
+ clocks = <&upg_clk>;
+ compatible = "brcm,bcm7038-wdt";
+ reg = <0x4067e8 0x14>;
+ status = "disabled";
+ };
+
aon_pm_l2_intc: interrupt-controller@408440 {
compatible = "brcm,l2-intc";
reg = <0x408440 0x30>;
@@ -257,6 +264,17 @@
brcm,irq-can-wake;
};
+ aon_ctrl: syscon@408000 {
+ compatible = "brcm,brcmstb-aon-ctrl";
+ reg = <0x408000 0x100>, <0x408200 0x200>;
+ reg-names = "aon-ctrl", "aon-sram";
+ };
+
+ timers: timer@4067c0 {
+ compatible = "brcm,brcmstb-timers";
+ reg = <0x4067c0 0x40>;
+ };
+
upg_gio: gpio@406700 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406700 0x80>;
@@ -509,5 +527,76 @@
interrupt-names = "mspi_done";
status = "disabled";
};
+
+ waketimer: waketimer@409580 {
+ compatible = "brcm,brcmstb-waketimer";
+ reg = <0x409580 0x14>;
+ interrupts = <0x3>;
+ interrupt-parent = <&aon_pm_l2_intc>;
+ interrupt-names = "timer";
+ clocks = <&upg_clk>;
+ status = "disabled";
+ };
+ };
+
+ memory_controllers {
+ compatible = "simple-bus";
+ ranges = <0x0 0x103b0000 0x1a000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory-controller@0 {
+ compatible = "brcm,brcmstb-memc", "simple-bus";
+ ranges = <0x0 0x0 0xa000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memc-arb@1000 {
+ compatible = "brcm,brcmstb-memc-arb";
+ reg = <0x1000 0x248>;
+ };
+
+ memc-ddr@2000 {
+ compatible = "brcm,brcmstb-memc-ddr";
+ reg = <0x2000 0x300>;
+ };
+
+ ddr-phy@6000 {
+ compatible = "brcm,brcmstb-ddr-phy";
+ reg = <0x6000 0xc8>;
+ };
+
+ shimphy@8000 {
+ compatible = "brcm,brcmstb-ddr-shimphy";
+ reg = <0x8000 0x13c>;
+ };
+ };
+
+ memory-controller@1 {
+ compatible = "brcm,brcmstb-memc", "simple-bus";
+ ranges = <0x0 0x10000 0xa000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memc-arb@1000 {
+ compatible = "brcm,brcmstb-memc-arb";
+ reg = <0x1000 0x248>;
+ };
+
+ memc-ddr@2000 {
+ compatible = "brcm,brcmstb-memc-ddr";
+ reg = <0x2000 0x300>;
+ };
+
+ ddr-phy@6000 {
+ compatible = "brcm,brcmstb-ddr-phy";
+ reg = <0x6000 0xc8>;
+ };
+
+ shimphy@8000 {
+ compatible = "brcm,brcmstb-ddr-shimphy";
+ reg = <0x8000 0x13c>;
+ };
+ };
};
};
diff --git a/dts/src/mips/brcm/bcm97125cbmb.dts b/dts/src/mips/brcm/bcm97125cbmb.dts
index 7f59ea2ded..79e9769f7e 100644
--- a/dts/src/mips/brcm/bcm97125cbmb.dts
+++ b/dts/src/mips/brcm/bcm97125cbmb.dts
@@ -50,6 +50,10 @@
status = "okay";
};
+&watchdog {
+ status = "okay";
+};
+
/* FIXME: USB is wonky; disable it for now */
&ehci0 {
status = "disabled";
diff --git a/dts/src/mips/brcm/bcm97346dbsmb.dts b/dts/src/mips/brcm/bcm97346dbsmb.dts
index 9e7d5228f2..28370ff77e 100644
--- a/dts/src/mips/brcm/bcm97346dbsmb.dts
+++ b/dts/src/mips/brcm/bcm97346dbsmb.dts
@@ -59,6 +59,10 @@
status = "okay";
};
+&watchdog {
+ status = "okay";
+};
+
&enet0 {
status = "okay";
};
@@ -114,3 +118,7 @@
&mspi {
status = "okay";
};
+
+&waketimer {
+ status = "okay";
+};
diff --git a/dts/src/mips/brcm/bcm97358svmb.dts b/dts/src/mips/brcm/bcm97358svmb.dts
index 708207a000..41c1b510c2 100644
--- a/dts/src/mips/brcm/bcm97358svmb.dts
+++ b/dts/src/mips/brcm/bcm97358svmb.dts
@@ -55,6 +55,10 @@
status = "okay";
};
+&watchdog {
+ status = "okay";
+};
+
&enet0 {
status = "okay";
};
@@ -106,3 +110,7 @@
&mspi {
status = "okay";
};
+
+&waketimer {
+ status = "okay";
+};
diff --git a/dts/src/mips/brcm/bcm97360svmb.dts b/dts/src/mips/brcm/bcm97360svmb.dts
index 73c6dc9c8c..9f6c6c9b7e 100644
--- a/dts/src/mips/brcm/bcm97360svmb.dts
+++ b/dts/src/mips/brcm/bcm97360svmb.dts
@@ -50,6 +50,10 @@
status = "okay";
};
+&watchdog {
+ status = "okay";
+};
+
&enet0 {
status = "okay";
};
@@ -109,3 +113,7 @@
&mspi {
status = "okay";
};
+
+&waketimer {
+ status = "okay";
+};
diff --git a/dts/src/mips/brcm/bcm97362svmb.dts b/dts/src/mips/brcm/bcm97362svmb.dts
index 37bacfdcf9..df8b755c39 100644
--- a/dts/src/mips/brcm/bcm97362svmb.dts
+++ b/dts/src/mips/brcm/bcm97362svmb.dts
@@ -47,6 +47,10 @@
status = "okay";
};
+&watchdog {
+ status = "okay";
+};
+
&enet0 {
status = "okay";
};
@@ -78,3 +82,7 @@
&mspi {
status = "okay";
};
+
+&waketimer {
+ status = "okay";
+};
diff --git a/dts/src/mips/brcm/bcm97420c.dts b/dts/src/mips/brcm/bcm97420c.dts
index f96241e948..086faeaa38 100644
--- a/dts/src/mips/brcm/bcm97420c.dts
+++ b/dts/src/mips/brcm/bcm97420c.dts
@@ -60,6 +60,10 @@
status = "okay";
};
+&watchdog {
+ status = "okay";
+};
+
/* FIXME: MAC driver comes up but cannot attach to PHY */
&enet0 {
status = "disabled";
diff --git a/dts/src/mips/brcm/bcm97425svmb.dts b/dts/src/mips/brcm/bcm97425svmb.dts
index ce762c7b2e..0ed22217bf 100644
--- a/dts/src/mips/brcm/bcm97425svmb.dts
+++ b/dts/src/mips/brcm/bcm97425svmb.dts
@@ -61,6 +61,10 @@
status = "okay";
};
+&watchdog {
+ status = "okay";
+};
+
&enet0 {
status = "okay";
};
@@ -144,3 +148,7 @@
&mspi {
status = "okay";
};
+
+&waketimer {
+ status = "okay";
+};
diff --git a/dts/src/mips/brcm/bcm97435svmb.dts b/dts/src/mips/brcm/bcm97435svmb.dts
index d4dd31a543..2c145a883a 100644
--- a/dts/src/mips/brcm/bcm97435svmb.dts
+++ b/dts/src/mips/brcm/bcm97435svmb.dts
@@ -61,6 +61,10 @@
status = "okay";
};
+&watchdog {
+ status = "okay";
+};
+
&enet0 {
status = "okay";
};
@@ -120,3 +124,7 @@
&mspi {
status = "okay";
};
+
+&waketimer {
+ status = "okay";
+};
diff --git a/dts/src/mips/img/boston.dts b/dts/src/mips/img/boston.dts
index 2cd49b60e0..1bd105428f 100644
--- a/dts/src/mips/img/boston.dts
+++ b/dts/src/mips/img/boston.dts
@@ -157,7 +157,7 @@
#address-cells = <1>;
#size-cells = <0>;
- rtc@0x68 {
+ rtc@68 {
compatible = "st,m41t81s";
reg = <0x68>;
};
diff --git a/dts/src/mips/ingenic/ci20.dts b/dts/src/mips/ingenic/ci20.dts
index a4cc52214d..38078594cf 100644
--- a/dts/src/mips/ingenic/ci20.dts
+++ b/dts/src/mips/ingenic/ci20.dts
@@ -110,22 +110,22 @@
reg = <0x0 0x0 0x0 0x800000>;
};
- partition@0x800000 {
+ partition@800000 {
label = "u-boot";
reg = <0x0 0x800000 0x0 0x200000>;
};
- partition@0xa00000 {
+ partition@a00000 {
label = "u-boot-env";
reg = <0x0 0xa00000 0x0 0x200000>;
};
- partition@0xc00000 {
+ partition@c00000 {
label = "boot";
reg = <0x0 0xc00000 0x0 0x4000000>;
};
- partition@0x8c00000 {
+ partition@4c00000 {
label = "system";
reg = <0x0 0x4c00000 0x1 0xfb400000>;
};
diff --git a/dts/src/mips/mscc/ocelot.dtsi b/dts/src/mips/mscc/ocelot.dtsi
new file mode 100644
index 0000000000..dd239cab2f
--- /dev/null
+++ b/dts/src/mips/mscc/ocelot.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2017 Microsemi Corporation */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,ocelot";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <&cpu_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <500000000>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&cpu_clk>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ ahb@70000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x70000000 0x2000000>;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon@0 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ intc: interrupt-controller@70 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100000 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@100800 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100800 0x20>;
+ interrupts = <7>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ reset@1070008 {
+ compatible = "mscc,ocelot-chip-reset";
+ reg = <0x1070008 0x4>;
+ };
+
+ gpio: pinctrl@1070034 {
+ compatible = "mscc,ocelot-pinctrl";
+ reg = <0x1070034 0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 22>;
+
+ uart_pins: uart-pins {
+ pins = "GPIO_6", "GPIO_7";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ pins = "GPIO_12", "GPIO_13";
+ function = "uart2";
+ };
+ };
+ };
+};
diff --git a/dts/src/mips/mscc/ocelot_pcb123.dts b/dts/src/mips/mscc/ocelot_pcb123.dts
new file mode 100644
index 0000000000..29d6414f88
--- /dev/null
+++ b/dts/src/mips/mscc/ocelot_pcb123.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2017 Microsemi Corporation */
+
+/dts-v1/;
+
+#include "ocelot.dtsi"
+
+/ {
+ compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0e000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 03:48:19 +0000