diff options
Diffstat (limited to 'include/mach/mxs')
25 files changed, 3057 insertions, 0 deletions
diff --git a/include/mach/mxs/debug_ll.h b/include/mach/mxs/debug_ll.h new file mode 100644 index 0000000000..41658ba0c5 --- /dev/null +++ b/include/mach/mxs/debug_ll.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MACH_MXS_DEBUG_LL_H__ +#define __MACH_MXS_DEBUG_LL_H__ + +#include <io.h> +#include <mach/mxs/imx-regs.h> + +#define UARTDBGDR 0x00 +#define UARTDBGFR 0x18 +# define TXFE (1 << 7) +# define TXFF (1 << 5) + +static inline void PUTC_LL(int c) +{ + void __iomem *base = (void *)IMX_DBGUART_BASE; + + /* Wait for room in TX FIFO */ + while (!(readl(base + UARTDBGFR) & TXFE)); + + writel(c, base + UARTDBGDR); +} + +#endif /* __MACH_MXS_DEBUG_LL_H__ */ diff --git a/include/mach/mxs/devices.h b/include/mach/mxs/devices.h new file mode 100644 index 0000000000..d200b4b5cd --- /dev/null +++ b/include/mach/mxs/devices.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MACH_MXS_DEVICES_H +#define __MACH_MXS_DEVICES_H + +#include <common.h> +#include <linux/sizes.h> +#include <xfuncs.h> +#include <driver.h> +#include <mach/mxs/imx-regs.h> + +static inline struct device *mxs_add_nand(unsigned long gpmi_base, unsigned long bch_base) +{ + struct resource res[] = { + { + .start = gpmi_base, + .end = gpmi_base + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = bch_base, + .end = bch_base + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + }; + + struct device *dev = xzalloc(sizeof(*dev)); + + dev->resource = xzalloc(sizeof(struct resource) * ARRAY_SIZE(res)); + memcpy(dev->resource, res, sizeof(struct resource) * ARRAY_SIZE(res)); + dev->num_resources = ARRAY_SIZE(res); + dev_set_name(dev, "mxs_nand"); + dev->id = DEVICE_ID_DYNAMIC; + + platform_device_register(dev); + + return dev; +}; + +static inline struct device *imx23_add_nand(void) +{ + return mxs_add_nand(MXS_GPMI_BASE, MXS_BCH_BASE); +} + +static inline struct device *imx28_add_nand(void) +{ + return mxs_add_nand(MXS_GPMI_BASE, MXS_BCH_BASE); +} + +#endif /* __MACH_MXS_DEVICES_H */ diff --git a/include/mach/mxs/fb.h b/include/mach/mxs/fb.h new file mode 100644 index 0000000000..8fcfe86520 --- /dev/null +++ b/include/mach/mxs/fb.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MACH_FB_H +# define __MACH_FB_H + +#include <fb.h> + +/** LC display uses active high data enable signal */ +#define FB_SYNC_DE_HIGH_ACT (1 << 27) +/** LC display will latch its data at clock's rising edge */ +#define FB_SYNC_CLK_INVERT (1 << 28) +/** output RGB digital data inverted */ +#define FB_SYNC_DATA_INVERT (1 << 29) +/** Stop clock if no data is sent (required for passive displays) */ +#define FB_SYNC_CLK_IDLE_DIS (1 << 30) +/** swap RGB to BGR */ +#define FB_SYNC_SWAP_RGB (1 << 31) + +#define USE_LCD_RESET 1 + +struct imx_fb_platformdata { + struct fb_videomode *mode_list; + unsigned mode_cnt; + + unsigned dotclk_delay; /**< refer manual HW_LCDIF_VDCTRL4 register */ + unsigned ld_intf_width; /* interface width in bits */ + unsigned bits_per_pixel; + + void *fixed_screen; /**< if != NULL use this as framebuffer memory */ + unsigned fixed_screen_size; /**< framebuffer memory size for fixed_screen */ + + unsigned flags; + void (*enable)(int enable); /**< hook to enable backlight */ +}; + +#endif /* __MACH_FB_H */ + diff --git a/include/mach/mxs/generic.h b/include/mach/mxs/generic.h new file mode 100644 index 0000000000..4cba591000 --- /dev/null +++ b/include/mach/mxs/generic.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2010 Juergen Beisert, Pengutronix */ + +#ifdef CONFIG_ARCH_IMX23 +# define cpu_is_mx23() (1) +#else +# define cpu_is_mx23() (0) +#endif + +#ifdef CONFIG_ARCH_IMX28 +# define cpu_is_mx28() (1) +#else +# define cpu_is_mx28() (0) +#endif + +#define cpu_is_mx1() (0) +#define cpu_is_mx21() (0) +#define cpu_is_mx25() (0) +#define cpu_is_mx27() (0) +#define cpu_is_mx31() (0) +#define cpu_is_mx35() (0) +#define cpu_is_mx51() (0) +#define cpu_is_mx53() (0) +#define cpu_is_mx6() (0) +#define cpu_is_mx7() (0) +#define cpu_is_mx6ul() (0) +#define cpu_is_mx6ull() (0) diff --git a/include/mach/mxs/imx-regs.h b/include/mach/mxs/imx-regs.h new file mode 100644 index 0000000000..648b200bc5 --- /dev/null +++ b/include/mach/mxs/imx-regs.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2010 Juergen Beisert, Pengutronix */ + +#ifndef _IMX_REGS_H +# define _IMX_REGS_H + +#if defined CONFIG_ARCH_IMX23 +#include <mach/mxs/imx23-regs.h> +#endif + +#if defined CONFIG_ARCH_IMX28 +#include <mach/mxs/imx28-regs.h> +#endif + +#endif /* _IMX_REGS_H */ diff --git a/include/mach/mxs/imx23-regs.h b/include/mach/mxs/imx23-regs.h new file mode 100644 index 0000000000..a9a295fcbc --- /dev/null +++ b/include/mach/mxs/imx23-regs.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2010 Juergen Beisert, Pengutronix */ + +#ifndef __ASM_ARCH_MX23_REGS_H +#define __ASM_ARCH_MX23_REGS_H + +#define IMX_MEMORY_BASE 0x40000000 +#define MXS_APBH_BASE 0x80004000 +#define MXS_BCH_BASE 0x8000a000 +#define MXS_GPMI_BASE 0x8000c000 +#define IMX_UART1_BASE 0x8006c000 +#define IMX_UART2_BASE 0x8006e000 +#define IMX_DBGUART_BASE 0x80070000 +#define IMX_TIM1_BASE 0x80068000 +#define IMX_IOMUXC_BASE 0x80018000 +#define IMX_EMI_BASE 0x80020000 +#define IMX_OCOTP_BASE 0x8002c000 +#define IMX_WDT_BASE 0x8005c000 +#define IMX_CCM_BASE 0x80040000 +#define IMX_LRADC_BASE 0x80050000 +#define IMX_I2C1_BASE 0x80058000 +#define IMX_SSP1_BASE 0x80010000 +#define IMX_FB_BASE 0x80030000 +#define IMX_SSP2_BASE 0x80034000 +#define IMX_POWER_BASE 0x80044000 +#define IMX_USBPHY_BASE 0x8007c000 +#define IMX_DIGCTL_BASE 0x8001c000 +#define IMX_USB_BASE 0x80080000 +#define IMX_SDRAMC_BASE 0x800e0000 + +#endif /* __ASM_ARCH_MX23_REGS_H */ diff --git a/include/mach/mxs/imx23.h b/include/mach/mxs/imx23.h new file mode 100644 index 0000000000..03eddabed0 --- /dev/null +++ b/include/mach/mxs/imx23.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MACH_IMX23_H +#define __MACH_IMX23_H + +#include <linux/bitfield.h> +#include <io.h> + +#define DRAM_CTL14_CS0_EN BIT(0) +#define DRAM_CTL14_CS1_EN BIT(1) +#define DRAM_CTL11_COLUMNS_DIFF GENMASK(10, 8) +#define DRAM_CTL10_ROWS_DIFF GENMASK(18, 16) + +#define DRAM_CTL(n) (IMX_SDRAMC_BASE + 4 * (n)) + +static inline u32 imx23_get_memsize(void) +{ + u32 ctl10 = readl(DRAM_CTL(10)); + u32 ctl11 = readl(DRAM_CTL(11)); + u32 ctl14 = readl(DRAM_CTL(14)); + int rows, columns, banks = 4, cs0, cs1; + + columns = 12 - FIELD_GET(DRAM_CTL11_COLUMNS_DIFF, ctl11); + rows = 13 - FIELD_GET(DRAM_CTL10_ROWS_DIFF, ctl10); + cs0 = FIELD_GET(DRAM_CTL14_CS0_EN, ctl14); + cs1 = FIELD_GET(DRAM_CTL14_CS1_EN, ctl14); + + return 2 * (1 << columns) * (1 << rows) * banks * (cs0 + cs1); +} + +#endif /* __MACH_IMX23_H */ diff --git a/include/mach/mxs/imx28-regs.h b/include/mach/mxs/imx28-regs.h new file mode 100644 index 0000000000..67e1009a99 --- /dev/null +++ b/include/mach/mxs/imx28-regs.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __ASM_ARCH_MX28_REGS_H +#define __ASM_ARCH_MX28_REGS_H + +#define IMX_SRAM_BASE 0x00000000 +#define IMX_MEMORY_BASE 0x40000000 + +#define MXS_APBH_BASE 0x80004000 +#define MXS_BCH_BASE 0x8000a000 +#define MXS_GPMI_BASE 0x8000c000 +#define IMX_SSP0_BASE 0x80010000 +#define IMX_SSP1_BASE 0x80012000 +#define IMX_SSP2_BASE 0x80014000 +#define IMX_SSP3_BASE 0x80016000 +#define IMX_IOMUXC_BASE 0x80018000 +#define IMX_DIGCTL_BASE 0x8001c000 +#define IMX_EMI_BASE 0x80020000 +#define IMX_OCOTP_BASE 0x8002c000 +#define IMX_FB_BASE 0x80030000 +#define IMX_CCM_BASE 0x80040000 +#define IMX_POWER_BASE 0x80044000 +#define IMX_LRADC_BASE 0x80050000 +#define IMX_WDT_BASE 0x80056000 +#define IMX_I2C0_BASE 0x80058000 +#define IMX_I2C1_BASE 0x8005a000 +#define IMX_PWM_BASE 0x80064000 +#define IMX_TIM1_BASE 0x80068000 +#define IMX_UART0_BASE 0x8006a000 +#define IMX_UART1_BASE 0x8006c000 +#define IMX_UART2_BASE 0x8006e000 +#define IMX_UART3_BASE 0x80070000 +#define IMX_UART4_BASE 0x80072000 +#define IMX_DBGUART_BASE 0x80074000 +#define IMX_USBPHY0_BASE 0x8007c000 +#define IMX_USBPHY1_BASE 0x8007e000 +#define IMX_USB0_BASE 0x80080000 +#define IMX_USB1_BASE 0x80090000 +#define IMX_SDRAMC_BASE 0x800e0000 +#define IMX_FEC0_BASE 0x800F0000 +#define IMX_FEC1_BASE 0x800F4000 + +#endif /* __ASM_ARCH_MX28_REGS_H */ diff --git a/include/mach/mxs/imx28.h b/include/mach/mxs/imx28.h new file mode 100644 index 0000000000..cf2d5fb6ef --- /dev/null +++ b/include/mach/mxs/imx28.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MACH_IMX28_H +#define __MACH_IMX28_H + +#include <linux/bitfield.h> +#include <io.h> + +#define DRAM_CTL29_CS0_EN BIT(24) +#define DRAM_CTL29_CS1_EN BIT(25) +#define DRAM_CTL29_COLUMNS_DIFF GENMASK(18, 16) +#define DRAM_CTL29_ROWS_DIFF GENMASK(10, 8) +#define DRAM_CTL31_EIGHT_BANKS BIT(16) + +#define DRAM_CTL(n) (IMX_SDRAMC_BASE + 4 * (n)) + +static inline u32 imx28_get_memsize(void) +{ + u32 ctl29 = readl(DRAM_CTL(29)); + u32 ctl31 = readl(DRAM_CTL(31)); + int rows, columns, banks, cs0, cs1; + + columns = 12 - FIELD_GET(DRAM_CTL29_COLUMNS_DIFF, ctl29); + rows = 15 - FIELD_GET(DRAM_CTL29_ROWS_DIFF, ctl29); + banks = FIELD_GET(DRAM_CTL31_EIGHT_BANKS, ctl31) ? 8 : 4; + cs0 = FIELD_GET(DRAM_CTL29_CS0_EN, ctl29); + cs1 = FIELD_GET(DRAM_CTL29_CS1_EN, ctl29); + + return (1 << columns) * (1 << rows) * banks * (cs0 + cs1); +} + +#endif /* __MACH_IMX28_H */ diff --git a/include/mach/mxs/init.h b/include/mach/mxs/init.h new file mode 100644 index 0000000000..53c1e05634 --- /dev/null +++ b/include/mach/mxs/init.h @@ -0,0 +1,74 @@ +/* + * Freescale i.MX28 SPL functions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __M28_INIT_H__ +#define __M28_INIT_H__ + +void mxs_early_delay(int delay); + +/** + * Power configuration of the system: + * - POWER_USE_5V: use 5V input as power supply + * - POWER_USE_BATTERY: use battery input when the system is supplied by a battery + * - POWER_USE_BATTERY_INPUT: use battery input when the system is supplied by + * a DC source (instead of a real battery) on the battery input + * - POWER_ENABLE_4P2: power up the 4P2 regulator (implied for POWER_USE_5V) + */ +enum mxs_power_config { + POWER_USE_5V = 0b00000000, + POWER_USE_BATTERY = 0b00000001, + POWER_USE_BATTERY_INPUT = 0b00000010, + POWER_ENABLE_4P2 = 0b00000100, +}; +extern int power_config; +static inline enum mxs_power_config mxs_power_config_get_use(void) { + return (power_config & 0b00000011); +} + + +struct mxs_power_ctrl { + uint32_t target; /*< target voltage */ + uint32_t brownout; /*< brownout threshhold */ +}; +struct mxs_power_ctrls { + struct mxs_power_ctrl * vdda; /*< if non-null, set values for VDDA */ + struct mxs_power_ctrl * vddd; /*< if non-null, set values for VDDD */ + struct mxs_power_ctrl * vddio; /*< if non-null, set values for VDDIO */ + struct mxs_power_ctrl * vddmem; /*< if non-null, set values for VDDMEM */ +}; + +extern struct mxs_power_ctrl mxs_vddio_default; +extern struct mxs_power_ctrl mxs_vddd_default; +extern struct mxs_power_ctrl mxs_vdda_default; +extern struct mxs_power_ctrl mx23_vddmem_default; +extern struct mxs_power_ctrls mx23_power_default; +extern struct mxs_power_ctrls mx28_power_default; + +void mx23_power_init(const int config, struct mxs_power_ctrls *ctrls); +void mx28_power_init(const int config, struct mxs_power_ctrls *ctrls); +void mxs_power_wait_pswitch(void); + +extern const uint32_t mx28_dram_vals_default[190]; +extern uint32_t mx23_dram_vals[]; + +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LPDDR1 (0b00 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2 (0b10 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0b11 << 16) + +void mx23_mem_init(void); +void mx28_mem_init(const int emi_ds_ctrl_ddr_mode, + const uint32_t dram_vals[190]); +void mxs_mem_setup_cpu_and_hbus(void); +void mxs_mem_setup_vdda(void); +void mxs_mem_init_clock(const uint8_t clk_emi_div, const uint8_t clk_emi_frac); + +void mxs_lradc_init(void); +void mxs_lradc_enable_batt_measurement(void); + +#endif /* __M28_INIT_H__ */ diff --git a/include/mach/mxs/iomux-imx23.h b/include/mach/mxs/iomux-imx23.h new file mode 100644 index 0000000000..78a55a47b1 --- /dev/null +++ b/include/mach/mxs/iomux-imx23.h @@ -0,0 +1,354 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2010 Juergen Beisert, Pengutronix */ + +#ifndef __ASM_MACH_IOMUX_MX23_H +#define __ASM_MACH_IOMUX_MX23_H + +/* Bank 0, pins 0 ... 15, GPIO pins 0 ... 15 */ +#define GPMI_D15 (FUNC(0) | PORTF(0, 15) | SE | PE) +#define GPMI_D15_AUART2_TX (FUNC(1) | PORTF(0, 15) | SE | PE) +#define GPMI_D15_GPMI_CE3N (FUNC(2) | PORTF(0, 15) | SE | PE) +#define GPMI_D15_GPIO (FUNC(3) | PORTF(0, 15) | SE | PE) +#define GPMI_D14 (FUNC(0) | PORTF(0, 14) | SE) +#define GPMI_D14_AUART2_RX (FUNC(1) | PORTF(0, 14) | SE) +#define GPMI_D14_GPIO (FUNC(3) | PORTF(0, 14) | SE) +#define GPMI_D13 (FUNC(0) | PORTF(0, 13) | SE) +#define GPMI_D13_LCD_D23 (FUNC(1) | PORTF(0, 13) | SE) +#define GPMI_D13_GPIO (FUNC(3) | PORTF(0, 13) | SE) +#define GPMI_D12 (FUNC(0) | PORTF(0, 12) | SE) +#define GPMI_D12_LCD_D22 (FUNC(1) | PORTF(0, 12) | SE) +#define GPMI_D12_GPIO (FUNC(3) | PORTF(0, 12) | SE) +#define GPMI_D11 (FUNC(0) | PORTF(0, 11) | SE | PE) +#define GPMI_D11_LCD_D21 (FUNC(1) | PORTF(0, 11) | SE | PE) +#define GPMI_D11_SSP1_D7 (FUNC(2) | PORTF(0, 11) | SE | PE) +#define GPMI_D11_GPIO (FUNC(3) | PORTF(0, 11) | SE | PE) +#define GPMI_D10 (FUNC(0) | PORTF(0, 10) | SE | PE) +#define GPMI_D10_LCD_D20 (FUNC(1) | PORTF(0, 10) | SE | PE) +#define GPMI_D10_SSP1_D6 (FUNC(2) | PORTF(0, 10) | SE | PE) +#define GPMI_D10_GPIO (FUNC(3) | PORTF(0, 10) | SE | PE) +#define GPMI_D09 (FUNC(0) | PORTF(0, 9) | SE | PE) +#define GPMI_D09_LCD_D19 (FUNC(1) | PORTF(0, 9) | SE | PE) +#define GPMI_D09_SSP1_D5 (FUNC(2) | PORTF(0, 9) | SE | PE) +#define GPMI_D09_GPIO (FUNC(3) | PORTF(0, 9) | SE | PE) +#define GPMI_D08 (FUNC(0) | PORTF(0, 8) | SE | PE) +#define GPMI_D08_LCD_D18 (FUNC(1) | PORTF(0, 8) | SE | PE) +#define GPMI_D08_SSP1_D4 (FUNC(2) | PORTF(0, 8) | SE | PE) +#define GPMI_D08_GPIO (FUNC(3) | PORTF(0, 8) | SE | PE) +#define GPMI_D07 (FUNC(0) | PORTF(0, 7) | SE | PE) +#define GPMI_D07_LCD_D15 (FUNC(1) | PORTF(0, 7) | SE | PE) +#define GPMI_D07_SSP2_D7 (FUNC(2) | PORTF(0, 7) | SE | PE) +#define GPMI_D07_GPIO (FUNC(3) | PORTF(0, 7) | SE | PE) +#define GPMI_D06 (FUNC(0) | PORTF(0, 6) | SE | PE) +#define GPMI_D06_LCD_D14 (FUNC(1) | PORTF(0, 6) | SE | PE) +#define GPMI_D06_SSP2_D6 (FUNC(2) | PORTF(0, 6) | SE | PE) +#define GPMI_D06_GPIO (FUNC(3) | PORTF(0, 6) | SE | PE) +#define GPMI_D05 (FUNC(0) | PORTF(0, 5) | SE | PE) +#define GPMI_D05_LCD_D13 (FUNC(1) | PORTF(0, 5) | SE | PE) +#define GPMI_D05_SSP2_D5 (FUNC(2) | PORTF(0, 5) | SE | PE) +#define GPMI_D05_GPIO (FUNC(3) | PORTF(0, 5) | SE | PE) +#define GPMI_D04 (FUNC(0) | PORTF(0, 4) | SE | PE) +#define GPMI_D04_LCD_D12 (FUNC(1) | PORTF(0, 4) | SE | PE) +#define GPMI_D04_SSP2_D4 (FUNC(2) | PORTF(0, 4) | SE | PE) +#define GPMI_D04_GPIO (FUNC(3) | PORTF(0, 4) | SE | PE) +#define GPMI_D03 (FUNC(0) | PORTF(0, 3) | SE | PE) +#define GPMI_D03_LCD_D11 (FUNC(1) | PORTF(0, 3) | SE | PE) +#define GPMI_D03_SSP2_D3 (FUNC(2) | PORTF(0, 3) | SE | PE) +#define GPMI_D03_GPIO (FUNC(3) | PORTF(0, 3) | SE | PE) +#define GPMI_D02 (FUNC(0) | PORTF(0, 2) | SE | PE) +#define GPMI_D02_LCD_D10 (FUNC(1) | PORTF(0, 2) | SE | PE) +#define GPMI_D02_SSP2_D2 (FUNC(2) | PORTF(0, 2) | SE | PE) +#define GPMI_D02_GPIO (FUNC(3) | PORTF(0, 2) | SE | PE) +#define GPMI_D01 (FUNC(0) | PORTF(0, 1) | SE | PE) +#define GPMI_D01_LCD_D9 (FUNC(1) | PORTF(0, 1) | SE | PE) +#define GPMI_D01_SSP2_D1 (FUNC(2) | PORTF(0, 1) | SE | PE) +#define GPMI_D01_GPIO (FUNC(3) | PORTF(0, 1) | SE | PE) +#define GPMI_D00 (FUNC(0) | PORTF(0, 0) | SE | PE) +#define GPMI_D00_LCD_D8 (FUNC(1) | PORTF(0, 0) | SE | PE) +#define GPMI_D00_SSP2_D0 (FUNC(2) | PORTF(0, 0) | SE | PE) +#define GPMI_D00_GPIO (FUNC(3) | PORTF(0, 0) | SE | PE) + +/* Bank 0, pins 16 ... 31 GPIO pins 16 ... 31 */ +#define I2C_SDA (FUNC(0) | PORTF(1, 15) | SE) +#define I2C_SDA_GPMI_CE2N (FUNC(1) | PORTF(1, 15) | SE) +#define I2C_SDA_AUART1_RX (FUNC(2) | PORTF(1, 15) | SE) +#define I2C_SDA_GPIO (FUNC(3) | PORTF(1, 15) | SE) +#define I2C_CLK (FUNC(0) | PORTF(1, 14) | SE | PE) +#define I2C_CLK_GPMI_RDY2 (FUNC(1) | PORTF(1, 14) | SE | PE) +#define I2C_CLK_AUART1_TX (FUNC(2) | PORTF(1, 14) | SE | PE) +#define I2C_CLK_GPIO (FUNC(3) | PORTF(1, 14) | SE | PE) +#define AUART1_TX (FUNC(0) | PORTF(1, 13) | SE | PE) +#define AUART1_TX_SSP1_D7 (FUNC(2) | PORTF(1, 13) | SE | PE) +#define AUART1_TX_GPIO (FUNC(3) | PORTF(1, 13) | SE | PE) +#define AUART1_RX (FUNC(0) | PORTF(1, 12) | SE | PE) +#define AUART1_RX_SSP1_D6 (FUNC(2) | PORTF(1, 12) | SE | PE) +#define AUART1_RX_GPIO (FUNC(3) | PORTF(1, 12) | SE | PE) +#define AUART1_RTS (FUNC(0) | PORTF(1, 11) | SE | PE) +#define AUART1_RTS_SSP1_D5 (FUNC(2) | PORTF(1, 11) | SE | PE) +#define AUART1_RTS_GPIO (FUNC(3) | PORTF(1, 11) | SE | PE) +#define AUART1_CTS (FUNC(0) | PORTF(1, 10) | SE | PE) +#define AUART1_CTS_SSP1_D4 (FUNC(2) | PORTF(1, 10) | SE | PE) +#define AUART1_CTS_GPIO (FUNC(3) | PORTF(1, 10) | SE | PE) +#define GPMI_RDN (FUNC(0) | PORTF(1, 9) | SE) +#define GPMI_RDN_GPIO (FUNC(3) | PORTF(1, 9) | SE) +#define GPMI_WRN (FUNC(0) | PORTF(1, 8) | SE) +#define GPMI_WRN_SSP2_SCK (FUNC(2) | PORTF(1, 8) | SE) +#define GPMI_WRN_GPIO (FUNC(3) | PORTF(1, 8) | SE) +#define GPMI_WPM (FUNC(0) | PORTF(1, 7) | SE) +#define GPMI_WPM_GPIO (FUNC(3) | PORTF(1, 7) | SE) +#define GPMI_RDY3 (FUNC(0) | PORTF(1, 6) | SE | PE) +#define GPMI_RDY3_GPIO (FUNC(3) | PORTF(1, 6) | SE | PE) +#define GPMI_RDY2 (FUNC(0) | PORTF(1, 5) | SE | PE) +#define GPMI_RDY2_GPIO (FUNC(3) | PORTF(1, 5) | SE | PE) +#define GPMI_RDY1 (FUNC(0) | PORTF(1, 4) | SE | PE) +#define GPMI_RDY1_SSP2_CMD (FUNC(2) | PORTF(1, 4) | SE | PE) +#define GPMI_RDY1_GPIO (FUNC(3) | PORTF(1, 4) | SE | PE) +#define GPMI_RDY0 (FUNC(0) | PORTF(1, 3) | SE | PE) +#define GPMI_RDY0_SSP2_DETECT (FUNC(2) | PORTF(1, 3) | SE | PE) +#define GPMI_RDY0_GPIO (FUNC(3) | PORTF(1, 3) | SE | PE) +#define GPMI_CE2N (FUNC(0) | PORTF(1, 2) | SE | PE) +#define GPMI_CE2N_GPIO (FUNC(3) | PORTF(1, 2) | SE | PE) +#define GPMI_ALE (FUNC(0) | PORTF(1, 1) | SE) +#define GPMI_ALE_LCD_D17 (FUNC(1) | PORTF(1, 1) | SE) +#define GPMI_ALE_GPIO (FUNC(3) | PORTF(1, 1) | SE) +#define GPMI_CLE (FUNC(0) | PORTF(1, 0) | SE) +#define GPMI_CLE_LCD_D16 (FUNC(1) | PORTF(1, 1) | SE) +#define GPMI_CLE_GPIO (FUNC(3) | PORTF(1, 0) | SE) + +/* Bank 1, pins 0 ... 15 GPIO pins 32 ... 47 */ +#define LCD_D15 (FUNC(0) | PORTF(2, 15) | SE) +#define LCD_D15_ETM_DA7 (FUNC(1) | PORTF(2, 15) | SE) +#define LCD_D15_SAIF1_SDATA1 (FUNC(2) | PORTF(2, 15) | SE) +#define LCD_D15_GPIO (FUNC(3) | PORTF(2, 15) | SE) +#define LCD_D14 (FUNC(0) | PORTF(2, 14) | SE) +#define LCD_D14_ETM_DA6 (FUNC(1) | PORTF(2, 14) | SE) +#define LCD_D14_SAIF1_SDATA2 (FUNC(2) | PORTF(2, 14) | SE) +#define LCD_D14_GPIO (FUNC(3) | PORTF(2, 14) | SE) +#define LCD_D13 (FUNC(0) | PORTF(2, 13) | SE) +#define LCD_D13_ETM_DA5 (FUNC(1) | PORTF(2, 13) | SE) +#define LCD_D13_SAIF2_SDATA2 (FUNC(2) | PORTF(2, 13) | SE) +#define LCD_D13_GPIO (FUNC(3) | PORTF(2, 13) | SE) +#define LCD_D12 (FUNC(0) | PORTF(2, 12) | SE) +#define LCD_D12_ETM_DA4 (FUNC(1) | PORTF(2, 12) | SE) +#define LCD_D12_SAIF2_SDATA1 (FUNC(2) | PORTF(2, 12) | SE) +#define LCD_D12_GPIO (FUNC(3) | PORTF(2, 12) | SE) +#define LCD_D11 (FUNC(0) | PORTF(2, 11) | SE) +#define LCD_D11_ETM_DA3 (FUNC(1) | PORTF(2, 11) | SE) +#define LCD_D11_SAIF_LRCLK (FUNC(2) | PORTF(2, 11) | SE) +#define LCD_D11_GPIO (FUNC(3) | PORTF(2, 11) | SE) +#define LCD_D10 (FUNC(0) | PORTF(2, 10) | SE) +#define LCD_D10_ETM_DA2 (FUNC(1) | PORTF(2, 10) | SE) +#define LCD_D10_SAIF_BITCLK (FUNC(2) | PORTF(2, 10) | SE) +#define LCD_D10_GPIO (FUNC(3) | PORTF(2, 10) | SE) +#define LCD_D9 (FUNC(0) | PORTF(2, 9) | SE) +#define LCD_D9_ETM_DA1 (FUNC(1) | PORTF(2, 9) | SE) +#define LCD_D9_SAIF1_SDATA0 (FUNC(2) | PORTF(2, 9) | SE) +#define LCD_D9_GPIO (FUNC(3) | PORTF(2, 9) | SE) +#define LCD_D8 (FUNC(0) | PORTF(2, 8) | SE) +#define LCD_D8_ETM_DA0 (FUNC(1) | PORTF(2, 8) | SE) +#define LCD_D8_SAIF2_SDATA0 (FUNC(2) | PORTF(2, 8) | SE) +#define LCD_D8_GPIO (FUNC(3) | PORTF(2, 8) | SE) +#define LCD_D7 (FUNC(0) | PORTF(2, 7) | SE) +#define LCD_D7_ETM_DA15 (FUNC(1) | PORTF(2, 7) | SE) +#define LCD_D7_GPIO (FUNC(3) | PORTF(2, 7) | SE) +#define LCD_D6 (FUNC(0) | PORTF(2, 6) | SE) +#define LCD_D6_ETM_DA14 (FUNC(1) | PORTF(2, 6) | SE) +#define LCD_D6_GPIO (FUNC(3) | PORTF(2, 6) | SE) +#define LCD_D5 (FUNC(0) | PORTF(2, 5) | SE) +#define LCD_D5_ETM_DA13 (FUNC(1) | PORTF(2, 5) | SE) +#define LCD_D5_GPIO (FUNC(3) | PORTF(2, 5) | SE) +#define LCD_D4 (FUNC(0) | PORTF(2, 4) | SE) +#define LCD_D4_ETM_DA12 (FUNC(1) | PORTF(2, 4) | SE) +#define LCD_D4_GPIO (FUNC(3) | PORTF(2, 4) | SE) +#define LCD_D3 (FUNC(0) | PORTF(2, 3) | SE) +#define LCD_D3_ETM_DA11 (FUNC(1) | PORTF(2, 3) | SE) +#define LCD_D3_GPIO (FUNC(3) | PORTF(2, 3) | SE) +#define LCD_D2 (FUNC(0) | PORTF(2, 2) | SE) +#define LCD_D2_ETM_DA10 (FUNC(1) | PORTF(2, 2) | SE) +#define LCD_D2_GPIO (FUNC(3) | PORTF(2, 2) | SE) +#define LCD_D1 (FUNC(0) | PORTF(2, 1) | SE) +#define LCD_D1_ETM_DA9 (FUNC(1) | PORTF(2, 1) | SE) +#define LCD_D1_GPIO (FUNC(3) | PORTF(2, 1) | SE) +#define LCD_D0 (FUNC(0) | PORTF(2, 0) | SE) +#define LCD_D0_ETM_DA8 (FUNC(1) | PORTF(2, 0) | SE) +#define LCD_D0_GPIO (FUNC(3) | PORTF(2, 0) | SE) + +/* Bank 1, pins 16 ... 30 GPIO pins 48 ... 63 */ +#define PWM4 (FUNC(0) | PORTF(3, 14) | SE) +#define PWM4_ETM_CLK (FUNC(1) | PORTF(3, 14) | SE) +#define PWM4_AUART1_RTS (FUNC(2) | PORTF(3, 14) | SE) +#define PWM4_GPIO (FUNC(3) | PORTF(3, 14) | SE) +#define PWM3 (FUNC(0) | PORTF(3, 13) | SE) +#define PWM3_ETM_TCTL (FUNC(1) | PORTF(3, 13) | SE) +#define PWM3_AUART1_CTS (FUNC(2) | PORTF(3, 13) | SE) +#define PWM3_GPIO (FUNC(3) | PORTF(3, 13) | SE) +#define PWM2 (FUNC(0) | PORTF(3, 12) | SE | PE) +#define PWM2_GPMI_READY3 (FUNC(1) | PORTF(3, 12) | SE | PE) +#define PWM2_GPIO (FUNC(3) | PORTF(3, 12) | SE | PE) +#define PWM1 (FUNC(0) | PORTF(3, 11) | SE) +#define PWM1_TIMROT2 (FUNC(1) | PORTF(3, 11) | SE) +#define PWM1_DUART_TX (FUNC(2) | PORTF(3, 11) | SE) +#define PWM1_GPIO (FUNC(3) | PORTF(3, 11) | SE) +#define PWM0 (FUNC(0) | PORTF(3, 10) | SE) +#define PWM0_TIMROT1 (FUNC(1) | PORTF(3, 10) | SE) +#define PWM0_DUART_RX (FUNC(2) | PORTF(3, 10) | SE) +#define PWM0_GPIO (FUNC(3) | PORTF(3, 10) | SE) +#define LCD_VSYNC (FUNC(0) | PORTF(3, 9) | SE) +#define LCD_VSYNC_LCD_BUSY (FUNC(1) | PORTF(3, 9) | SE) +#define LCD_VSYNC_GPIO (FUNC(3) | PORTF(3, 9) | SE) +#define LCD_HSYNC (FUNC(0) | PORTF(3, 8) | SE) +#define LCD_HSYNC_I2C_SD (FUNC(1) | PORTF(3, 8) | SE) +#define LCD_HSYNC_GPIO (FUNC(3) | PORTF(3, 8) | SE) +#define LCD_ENABE (FUNC(0) | PORTF(3, 7) | SE) +#define LCD_ENABE_I2C_CLK (FUNC(1) | PORTF(3, 7) | SE) +#define LCD_ENABE_GPIO (FUNC(3) | PORTF(3, 7) | SE) +#define LCD_DOTCLOCK (FUNC(0) | PORTF(3, 6) | SE | PE) +#define LCD_DOTCLOCK_GPMI_READY3 (FUNC(1) | PORTF(3, 6) | SE | PE) +#define LCD_DOTCLOCK_GPIO (FUNC(3) | PORTF(3, 6) | SE | PE) +#define LCD_CS (FUNC(0) | PORTF(3, 5) | SE) +#define LCD_CS_GPIO (FUNC(3) | PORTF(3, 5) | SE) +#define LCD_WR (FUNC(0) | PORTF(3, 4) | SE) +#define LCD_WR_GPIO (FUNC(3) | PORTF(3, 4) | SE) +#define LCD_RS (FUNC(0) | PORTF(3, 3) | SE) +#define LCD_RS_ETM_TCLK (FUNC(1) | PORTF(3, 3) | SE) +#define LCD_RS_GPIO (FUNC(3) | PORTF(3, 3) | SE) +#define LCD_RESET (FUNC(0) | PORTF(3, 2) | SE | PE) +#define LCD_RESET_ETM_TCTL (FUNC(1) | PORTF(3, 2) | SE | PE) +#define LCD_RESET_GPMI_CE3N (FUNC(2) | PORTF(3, 2) | SE | PE) +#define LCD_RESET_GPIO (FUNC(3) | PORTF(3, 2) | SE | PE) +#define LCD_D17 (FUNC(0) | PORTF(3, 1) | SE) +#define LCD_D17_GPIO (FUNC(3) | PORTF(3, 1) | SE) +#define LCD_D16 (FUNC(0) | PORTF(3, 0) | SE) +#define LCD_D16_SAIF_ALT_BITCLK (FUNC(2) | PORTF(3, 0) | SE) +#define LCD_D16_GPIO (FUNC(3) | PORTF(3, 0) | SE) + +/* Bank 2, pins 0 ... 15 GPIO pins 64 ... 79 */ +#define EMI_A6 (FUNC(0) | PORTF(4, 15) | SE | VE) +#define EMI_A6_GPIO (FUNC(3) | PORTF(4, 15) | SE | VE) +#define EMI_A5 (FUNC(0) | PORTF(4, 14) | SE | VE) +#define EMI_A5_GPIO (FUNC(3) | PORTF(4, 14) | SE | VE) +#define EMI_A4 (FUNC(0) | PORTF(4, 13) | SE | VE) +#define EMI_A4_GPIO (FUNC(3) | PORTF(4, 13) | SE | VE) +#define EMI_A3 (FUNC(0) | PORTF(4, 12) | SE | VE) +#define EMI_A3_GPIO (FUNC(3) | PORTF(4, 12) | SE | VE) +#define EMI_A2 (FUNC(0) | PORTF(4, 11) | SE | VE) +#define EMI_A2_GPIO (FUNC(3) | PORTF(4, 11) | SE | VE) +#define EMI_A1 (FUNC(0) | PORTF(4, 10) | SE | VE) +#define EMI_A1_GPIO (FUNC(3) | PORTF(4, 10) | SE | VE) +#define EMI_A0 (FUNC(0) | PORTF(4, 9) | SE | VE) +#define EMI_A0_GPIO (FUNC(3) | PORTF(4, 9) | SE | VE) +#define ROTARYB (FUNC(0) | PORTF(4, 8) | SE | PE) +#define ROTARYB_AUART2_CTS (FUNC(1) | PORTF(4, 8) | SE | PE) +#define ROTARYB_GPMI_CE3N (FUNC(2) | PORTF(4, 8) | SE | PE) +#define ROTARYB_GPIO (FUNC(3) | PORTF(4, 8) | SE | PE) +#define ROTARYA (FUNC(0) | PORTF(4, 7) | SE) +#define ROTARYA_AUART2_RTS (FUNC(1) | PORTF(4, 7) | SE) +#define ROTARYA_SPDIF (FUNC(2) | PORTF(4, 7) | SE) +#define ROTARYA_GPIO (FUNC(3) | PORTF(4, 7) | SE) +#define SSP1_SCK (FUNC(0) | PORTF(4, 6) | SE) +#define SSP1_SCK_ALT_JTAG_TRST (FUNC(2) | PORTF(4, 6) | SE) +#define SSP1_SCK_GPIO (FUNC(3) | PORTF(4, 6) | SE) +#define SSP1_DATA3 (FUNC(0) | PORTF(4, 5) | SE | PE) +#define SSP1_DATA3_ALT_JTAG_TMS (FUNC(2) | PORTF(4, 5) | SE | PE) +#define SSP1_DATA3_GPIO (FUNC(3) | PORTF(4, 5) | SE | PE) +#define SSP1_DATA2 (FUNC(0) | PORTF(4, 4) | SE | PE) +#define SSP1_DATA2_I2C_SD (FUNC(1) | PORTF(4, 4) | SE | PE) +#define SSP1_DATA2_ALT_JTAG_RTCK (FUNC(2) | PORTF(4, 4) | SE | PE) +#define SSP1_DATA2_GPIO (FUNC(3) | PORTF(4, 4) | SE | PE) +#define SSP1_DATA1 (FUNC(0) | PORTF(4, 3) | SE | PE) +#define SSP1_DATA1_I2C_CLK (FUNC(1) | PORTF(4, 3) | SE | PE) +#define SSP1_DATA1_ALT_JTAG_TCK (FUNC(2) | PORTF(4, 3) | SE | PE) +#define SSP1_DATA1_GPIO (FUNC(3) | PORTF(4, 3) | SE | PE) +#define SSP1_DATA0 (FUNC(0) | PORTF(4, 2) | SE | PE) +#define SSP1_DATA0_ALT_JTAG_TDI (FUNC(2) | PORTF(4, 2) | SE | PE) +#define SSP1_DATA0_GPIO (FUNC(3) | PORTF(4, 2) | SE | PE) +#define SSP1_DETECT (FUNC(0) | PORTF(4, 1) | SE | PE) +#define SSP1_DETECT_GPMI_CE3N (FUNC(1) | PORTF(4, 1) | SE | PE) +#define SSP1_DETECT_USB_ID (FUNC(2) | PORTF(4, 1) | SE | PE) +#define SSP1_DETECT_GPIO (FUNC(3) | PORTF(4, 1) | SE | PE) +#define SSP1_CMD (FUNC(0) | PORTF(4, 0) | SE | PE) +#define SSP1_CMD_JTAG_TDO (FUNC(2) | PORTF(4, 0) | SE | PE) +#define SSP1_CMD_GPIO (FUNC(3) | PORTF(4, 0) | SE | PE) + +/* Bank 2, pins 16 ... 31 GPIO pins 80 ... 95 */ +#define EMI_WEN (FUNC(0) | PORTF(5, 15) | SE | VE) +#define EMI_WEN_GPIO (FUNC(3) | PORTF(5, 15) | SE | VE) +#define EMI_RASN (FUNC(0) | PORTF(5, 14) | SE | VE) +#define EMI_RASN_GPIO (FUNC(3) | PORTF(5, 14) | SE | VE) +#define EMI_CKE (FUNC(0) | PORTF(5, 13) | SE | VE) +#define EMI_CKE_GPIO (FUNC(3) | PORTF(5, 13) | SE | VE) +#define GPMI_CE0N (FUNC(0) | PORTF(5, 12) | SE) +#define GPMI_CE0N_GPIO (FUNC(3) | PORTF(5, 12) | SE) +#define GPMI_CE1N (FUNC(0) | PORTF(5, 11) | SE | PE) +#define GPMI_CE1N_GPIO (FUNC(3) | PORTF(5, 11) | SE | PE) +#define EMI_CE1N (FUNC(0) | PORTF(5, 10) | SE | VE | PE) +#define EMI_CE1N_GPIO (FUNC(3) | PORTF(5, 10) | SE | VE | PE) +#define EMI_CE0N (FUNC(0) | PORTF(5, 9) | SE | VE) +#define EMI_CE0N_GPIO (FUNC(3) | PORTF(5, 9) | SE | VE) +#define EMI_CASN (FUNC(0) | PORTF(5, 8) | SE | VE) +#define EMI_CASN_GPIO (FUNC(3) | PORTF(5, 8) | SE | VE) +#define EMI_BA1 (FUNC(0) | PORTF(5, 7) | SE | VE) +#define EMI_BA1_GPIO (FUNC(3) | PORTF(5, 7) | SE | VE) +#define EMI_BA0 (FUNC(0) | PORTF(5, 6) | SE | VE) +#define EMI_BA0_GPIO (FUNC(3) | PORTF(5, 6) | SE | VE) +#define EMI_A12 (FUNC(0) | PORTF(5, 5) | SE | VE) +#define EMI_A12_GPIO (FUNC(3) | PORTF(5, 5) | SE | VE) +#define EMI_A11 (FUNC(0) | PORTF(5, 4) | SE | VE) +#define EMI_A11_GPIO (FUNC(3) | PORTF(5, 4) | SE | VE) +#define EMI_A10 (FUNC(0) | PORTF(5, 3) | SE | VE) +#define EMI_A10_GPIO (FUNC(3) | PORTF(5, 3) | SE | VE) +#define EMI_A9 (FUNC(0) | PORTF(5, 2) | SE | VE) +#define EMI_A9_GPIO (FUNC(3) | PORTF(5, 2) | SE | VE) +#define EMI_A8 (FUNC(0) | PORTF(5, 1) | SE | VE) +#define EMI_A8_GPIO (FUNC(3) | PORTF(5, 1) | SE | VE) +#define EMI_A7 (FUNC(0) | PORTF(5, 0) | SE | VE) +#define EMI_A7_GPIO (FUNC(3) | PORTF(5, 0) | SE | VE) + +/* Bank 3, pins 0 ... 15 GPIO pins 96 ... 111 */ +#define EMI_D15 (FUNC(0) | PORTF(6, 15) | SE | VE | PE) +#define EMI_D15_DISABLED (FUNC(3) | PORTF(6, 15) | SE | VE | PE) +#define EMI_D14 (FUNC(0) | PORTF(6, 14) | SE | VE | PE) +#define EMI_D14_DISABLED (FUNC(3) | PORTF(6, 14) | SE | VE | PE) +#define EMI_D13 (FUNC(0) | PORTF(6, 13) | SE | VE | PE) +#define EMI_D13_DISABLED (FUNC(3) | PORTF(6, 13) | SE | VE | PE) +#define EMI_D12 (FUNC(0) | PORTF(6, 12) | SE | VE | PE) +#define EMI_D12_DISABLED (FUNC(3) | PORTF(6, 12) | SE | VE | PE) +#define EMI_D11 (FUNC(0) | PORTF(6, 11) | SE | VE | PE) +#define EMI_D11_DISABLED (FUNC(3) | PORTF(6, 11) | SE | VE | PE) +#define EMI_D10 (FUNC(0) | PORTF(6, 10) | SE | VE | PE) +#define EMI_D10_DISABLED (FUNC(3) | PORTF(6, 10) | SE | VE | PE) +#define EMI_D9 (FUNC(0) | PORTF(6, 9) | SE | VE | PE) +#define EMI_D9_DISABLED (FUNC(3) | PORTF(6, 9) | SE | VE | PE) +#define EMI_D8 (FUNC(0) | PORTF(6, 8) | SE | VE | PE) +#define EMI_D8_DISABLED (FUNC(3) | PORTF(6, 8) | SE | VE | PE) +#define EMI_D7 (FUNC(0) | PORTF(6, 7) | SE | VE | PE) +#define EMI_D7_DISABLED (FUNC(3) | PORTF(6, 7) | SE | VE | PE) +#define EMI_D6 (FUNC(0) | PORTF(6, 6) | SE | VE | PE) +#define EMI_D6_DISABLED (FUNC(3) | PORTF(6, 6) | SE | VE | PE) +#define EMI_D5 (FUNC(0) | PORTF(6, 5) | SE | VE | PE) +#define EMI_D5_DISABLED (FUNC(3) | PORTF(6, 5) | SE | VE | PE) +#define EMI_D4 (FUNC(0) | PORTF(6, 4) | SE | VE | PE) +#define EMI_D4_DISABLED (FUNC(3) | PORTF(6, 4) | SE | VE | PE) +#define EMI_D3 (FUNC(0) | PORTF(6, 3) | SE | VE | PE) +#define EMI_D3_DISABLED (FUNC(3) | PORTF(6, 3) | SE | VE | PE) +#define EMI_D2 (FUNC(0) | PORTF(6, 2) | SE | VE | PE) +#define EMI_D2_DISABLED (FUNC(3) | PORTF(6, 2) | SE | VE | PE) +#define EMI_D1 (FUNC(0) | PORTF(6, 1) | SE | VE | PE) +#define EMI_D1_DISABLED (FUNC(3) | PORTF(6, 1) | SE | VE | PE) +#define EMI_D0 (FUNC(0) | PORTF(6, 0) | SE | VE | PE) +#define EMI_D0_DISABLED (FUNC(3) | PORTF(6, 0) | SE | VE | PE) + +/* Bank 3, pins 16 ... 21 GPIO pins 112 ... 117 */ +#define EMI_CLKN (FUNC(0) | PORTF(7, 5) | SE | VE) +#define EMI_CLKN_DISABLED (FUNC(3) | PORTF(7, 5) | SE | VE) +#define EMI_CLK (FUNC(0) | PORTF(7, 4) | SE | VE) +#define EMI_CLK_DISABLED (FUNC(3) | PORTF(7, 4) | SE | VE) +#define EMI_DQS1 (FUNC(0) | PORTF(7, 3) | SE | VE) +#define EMI_DQS1_DISABLED (FUNC(3) | PORTF(7, 3) | SE | VE) +#define EMI_DQS0 (FUNC(0) | PORTF(7, 2) | SE | VE) +#define EMI_DQS0_DISABLED (FUNC(3) | PORTF(7, 2) | SE | VE) +#define EMI_DQM1 (FUNC(0) | PORTF(7, 1) | SE | VE | PE) +#define EMI_DQM1_DISABLED (FUNC(3) | PORTF(7, 1) | SE | VE | PE) +#define EMI_DQM0 (FUNC(0) | PORTF(7, 0) | SE | VE | PE) +#define EMI_DQM0_DISABLED (FUNC(3) | PORTF(7, 0) | SE | VE | PE) + +#endif /* __ASM_MACH_IOMUX_MX23_H */ diff --git a/include/mach/mxs/iomux-imx28.h b/include/mach/mxs/iomux-imx28.h new file mode 100644 index 0000000000..9fefe3a2af --- /dev/null +++ b/include/mach/mxs/iomux-imx28.h @@ -0,0 +1,561 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MACH_IOMUX_IMX28_H +#define __MACH_IOMUX_IMX28_H + +/* Bank 0, GPIO pins 0 ... 31 */ +#define GPMI_RESETN (FUNC(0) | PORTF(0, 28) | SE | VE | PE) +#define GPMI_RESETN_SSP3_CMD (FUNC(1) | PORTF(0, 28) | SE | VE | PE) +#define GPMI_RESETN_GPIO (FUNC(3) | PORTF(0, 28) | SE | VE | PE) +#define GPMI_CLE (FUNC(0) | PORTF(0, 27) | SE | VE | PE) +#define GPMI_CLE_SSP3_D2 (FUNC(1) | PORTF(0, 27) | SE | VE | PE) +#define GPMI_CLE_SSP3_D5 (FUNC(2) | PORTF(0, 27) | SE | VE | PE) +#define GPMI_CLE_GPIO (FUNC(3) | PORTF(0, 27) | SE | VE | PE) +#define GPMI_ALE (FUNC(0) | PORTF(0, 26) | SE | VE | PE) +#define GPMI_ALE_SSP3_D1 (FUNC(1) | PORTF(0, 26) | SE | VE | PE) +#define GPMI_ALE_SSP3_D4 (FUNC(2) | PORTF(0, 26) | SE | VE | PE) +#define GPMI_ALE_GPIO (FUNC(3) | PORTF(0, 26) | SE | VE | PE) +#define GPMI_WRN (FUNC(0) | PORTF(0, 25) | SE | VE | BK) +#define GPMI_WRN_SSP1_SCK (FUNC(1) | PORTF(0, 25) | SE | VE | BK) +#define GPMI_WRN_GPIO (FUNC(3) | PORTF(0, 25) | SE | VE | BK) +#define GPMI_RDN (FUNC(0) | PORTF(0, 24) | SE | VE | PE) +#define GPMI_RDN_SSP3_SCK (FUNC(1) | PORTF(0, 24) | SE | VE | PE) +#define GPMI_RDN_GPIO (FUNC(3) | PORTF(0, 24) | SE | VE | PE) +#define GPMI_READY3 (FUNC(0) | PORTF(0, 23) | SE | VE | PE) +#define GPMI_READY3_CAN0_RX (FUNC(1) | PORTF(0, 23) | SE | VE | PE) +#define GPMI_READY3_HSDAC_TRIG (FUNC(2) | PORTF(0, 23) | SE | VE | PE) +#define GPMI_READY3_GPIO (FUNC(3) | PORTF(0, 23) | SE | VE | PE) +#define GPMI_READY2 (FUNC(0) | PORTF(0, 22) | SE | VE | PE) +#define GPMI_READY2_CAN0_TX (FUNC(1) | PORTF(0, 22) | SE | VE | PE) +#define GPMI_READY2_ENET0_TX_ER (FUNC(2) | PORTF(0, 22) | SE | VE | PE) +#define GPMI_READY2_GPIO (FUNC(3) | PORTF(0, 22) | SE | VE | PE) +#define GPMI_READY1 (FUNC(0) | PORTF(0, 21) | SE | VE | PE) +#define GPMI_READY1_SSP1_CMD (FUNC(1) | PORTF(0, 21) | SE | VE | PE) +#define GPMI_READY1_GPIO (FUNC(3) | PORTF(0, 21) | SE | VE | PE) +#define GPMI_READY0 (FUNC(0) | PORTF(0, 20) | SE | VE | PE) +#define GPMI_READY0_SSP1_CD (FUNC(1) | PORTF(0, 20) | SE | VE | PE) +#define GPMI_READY0_USB0_ID (FUNC(2) | PORTF(0, 20) | SE | VE | PE) +#define GPMI_READY0_GPIO (FUNC(3) | PORTF(0, 20) | SE | VE | PE) +#define GPMI_CE3N (FUNC(0) | PORTF(0, 19) | SE | VE | PE) +#define GPMI_CE3N_CAN1_RX (FUNC(1) | PORTF(0, 19) | SE | VE | PE) +#define GPMI_CE3N_SAIF1_MCLK (FUNC(2) | PORTF(0, 19) | SE | VE | PE) +#define GPMI_CE3N_GPIO (FUNC(3) | PORTF(0, 19) | SE | VE | PE) +#define GPMI_CE2N (FUNC(0) | PORTF(0, 18) | SE | VE | PE) +#define GPMI_CE2N_CAN1_TX (FUNC(1) | PORTF(0, 18) | SE | VE | PE) +#define GPMI_CE2N_ENET0_RX_ER (FUNC(2) | PORTF(0, 18) | SE | VE | PE) +#define GPMI_CE2N_GPIO (FUNC(3) | PORTF(0, 18) | SE | VE | PE) +#define GPMI_CE1N (FUNC(0) | PORTF(0, 17) | SE | VE | PE) +#define GPMI_CE1N_SSP3_D3 (FUNC(1) | PORTF(0, 17) | SE | VE | PE) +#define GPMI_CE1N_GPIO (FUNC(3) | PORTF(0, 17) | SE | VE | PE) +#define GPMI_CE0N (FUNC(0) | PORTF(0, 16) | SE | VE | PE) +#define GPMI_CE0N_SSP3_D0 (FUNC(1) | PORTF(0, 16) | SE | VE | PE) +#define GPMI_CE0N_GPIO (FUNC(3) | PORTF(0, 16) | SE | VE | PE) +#define GPMI_D7 (FUNC(0) | PORTF(0, 7) | SE | VE | PE) +#define GPMI_D7_SSP1_D7 (FUNC(1) | PORTF(0, 7) | SE | VE | PE) +#define GPMI_D7_GPIO (FUNC(3) | PORTF(0, 7) | SE | VE | PE) +#define GPMI_D6 (FUNC(0) | PORTF(0, 6) | SE | VE | PE) +#define GPMI_D6_SSP1_D6 (FUNC(1) | PORTF(0, 6) | SE | VE | PE) +#define GPMI_D6_GPIO (FUNC(3) | PORTF(0, 6) | SE | VE | PE) +#define GPMI_D5 (FUNC(0) | PORTF(0, 5) | SE | VE | PE) +#define GPMI_D5_SSP1_D5 (FUNC(1) | PORTF(0, 5) | SE | VE | PE) +#define GPMI_D5_GPIO (FUNC(3) | PORTF(0, 5) | SE | VE | PE) +#define GPMI_D4 (FUNC(0) | PORTF(0, 4) | SE | VE | PE) +#define GPMI_D4_SSP1_D4 (FUNC(1) | PORTF(0, 4) | SE | VE | PE) +#define GPMI_D4_GPIO (FUNC(3) | PORTF(0, 4) | SE | VE | PE) +#define GPMI_D3 (FUNC(0) | PORTF(0, 3) | SE | VE | PE) +#define GPMI_D3_SSP1_D3 (FUNC(1) | PORTF(0, 3) | SE | VE | PE) +#define GPMI_D3_GPIO (FUNC(3) | PORTF(0, 3) | SE | VE | PE) +#define GPMI_D2 (FUNC(0) | PORTF(0, 2) | SE | VE | PE) +#define GPMI_D2_SSP1_D2 (FUNC(1) | PORTF(0, 2) | SE | VE | PE) +#define GPMI_D2_GPIO (FUNC(3) | PORTF(0, 2) | SE | VE | PE) +#define GPMI_D1 (FUNC(0) | PORTF(0, 1) | SE | VE | PE) +#define GPMI_D1_SSP1_D1 (FUNC(1) | PORTF(0, 1) | SE | VE | PE) +#define GPMI_D1_GPIO (FUNC(3) | PORTF(0, 1) | SE | VE | PE) +#define GPMI_D0 (FUNC(0) | PORTF(0, 0) | SE | VE | PE) +#define GPMI_D0_SSP1_D0 (FUNC(1) | PORTF(0, 0) | SE | VE | PE) +#define GPMI_D0_GPIO (FUNC(3) | PORTF(0, 0) | SE | VE | PE) + +/* Bank 1, GPIO pins 32 ... 63 */ +#define LCD_ENABLE (FUNC(0) | PORTF(1, 31) | SE | VE | BK) +#define LCD_ENABLE_GPIO (FUNC(3) | PORTF(1, 31) | SE | VE | BK) +#define LCD_DOTCLK (FUNC(0) | PORTF(1, 30) | SE | VE | BK) +#define LCD_DOTCLK_SAIF1_MCLK (FUNC(1) | PORTF(1, 30) | SE | VE | BK) +#define LCD_DOTCLK_ETM_TCLK (FUNC(2) | PORTF(1, 30) | SE | VE | BK) +#define LCD_DOTCLK_GPIO (FUNC(3) | PORTF(1, 30) | SE | VE | BK) +#define LCD_HSYNC (FUNC(0) | PORTF(1, 29) | SE | VE | BK) +#define LCD_HSYNC_SAIF1_SDATA1 (FUNC(1) | PORTF(1, 29) | SE | VE | BK) +#define LCD_HSYNC_ETM_TCTL (FUNC(2) | PORTF(1, 29) | SE | VE | BK) +#define LCD_HSYNC_GPIO (FUNC(3) | PORTF(1, 29) | SE | VE | BK) +#define LCD_VSYNC (FUNC(0) | PORTF(1, 28) | SE | VE | BK) +#define LCD_VSYNC_SAIF1_SDATA0 (FUNC(1) | PORTF(1, 28) | SE | VE | BK) +#define LCD_VSYNC_GPIO (FUNC(3) | PORTF(1, 28) | SE | VE | BK) +#define LCD_CS (FUNC(0) | PORTF(1, 27) | SE | VE | BK) +#define LCD_CS_LCD_ENABLE (FUNC(1) | PORTF(1, 27) | SE | VE | BK) +#define LCD_CS_GPIO (FUNC(3) | PORTF(1, 27) | SE | VE | BK) +#define LCD_RS (FUNC(0) | PORTF(1, 26) | SE | VE | BK) +#define LCD_RS_LCD_DOTCLK (FUNC(1) | PORTF(1, 26) | SE | VE | BK) +#define LCD_RS_GPIO (FUNC(3) | PORTF(1, 26) | SE | VE | BK) +#define LCD_WR_RWN (FUNC(0) | PORTF(1, 25) | SE | VE | BK) +#define LCD_WR_RWN_LCD_HSYNC (FUNC(1) | PORTF(1, 25) | SE | VE | BK) +#define LCD_WR_RWN_ETM_TCLK (FUNC(2) | PORTF(1, 25) | SE | VE | BK) +#define LCD_WR_RWN_GPIO (FUNC(3) | PORTF(1, 25) | SE | VE | BK) +#define LCD_RD_E (FUNC(0) | PORTF(1, 24) | SE | VE | BK) +#define LCD_RD_E_LCD_VSYNC (FUNC(1) | PORTF(1, 24) | SE | VE | BK) +#define LCD_RD_E_ETM_TCTL (FUNC(2) | PORTF(1, 24) | SE | VE | BK) +#define LCD_RD_E_GPIO (FUNC(3) | PORTF(1, 24) | SE | VE | BK) +#define LCD_D23 (FUNC(0) | PORTF(1, 23) | SE | VE | BK) +#define LCD_D23_ENET1_1588_EVENT3_IN (FUNC(1) | PORTF(1, 23) | SE | VE | BK) +#define LCD_D23_ETM_DA0 (FUNC(2) | PORTF(1, 23) | SE | VE | BK) +#define LCD_D23_GPIO (FUNC(3) | PORTF(1, 23) | SE | VE | BK) +#define LCD_D22 (FUNC(0) | PORTF(1, 22) | SE | VE | BK) +#define LCD_D22_ENET1_1588_EVENT3_OUT (FUNC(1) | PORTF(1, 22) | SE | VE | BK) +#define LCD_D22_ETM_DA1 (FUNC(2) | PORTF(1, 22) | SE | VE | BK) +#define LCD_D22_GPIO (FUNC(3) | PORTF(1, 22) | SE | VE | BK) +#define LCD_D21 (FUNC(0) | PORTF(1, 21) | SE | VE | BK) +#define LCD_D21_ENET1_1588_EVENT2_IN (FUNC(1) | PORTF(1, 21) | SE | VE | BK) +#define LCD_D21_ETM_DA2 (FUNC(2) | PORTF(1, 21) | SE | VE | BK) +#define LCD_D21_GPIO (FUNC(3) | PORTF(1, 21) | SE | VE | BK) +#define LCD_D20 (FUNC(0) | PORTF(1, 20) | SE | VE | BK) +#define LCD_D20_ENET1_1588_EVENT2_OUT (FUNC(1) | PORTF(1, 20) | SE | VE | BK) +#define LCD_D20_ETM_DA3 (FUNC(2) | PORTF(1, 20) | SE | VE | BK) +#define LCD_D20_GPIO (FUNC(3) | PORTF(1, 20) | SE | VE | BK) +#define LCD_D19 (FUNC(0) | PORTF(1, 19) | SE | VE | BK) +#define LCD_D19_ETM_DA4 (FUNC(2) | PORTF(1, 19) | SE | VE | BK) +#define LCD_D19_GPIO (FUNC(3) | PORTF(1, 19) | SE | VE | BK) +#define LCD_D18 (FUNC(0) | PORTF(1, 18) | SE | VE | BK) +#define LCD_D18_ETM_DA5 (FUNC(2) | PORTF(1, 18) | SE | VE | BK) +#define LCD_D18_GPIO (FUNC(3) | PORTF(1, 18) | SE | VE | BK) +#define LCD_D17 (FUNC(0) | PORTF(1, 17) | SE | VE | BK) +#define LCD_D17_ETM_DA6 (FUNC(2) | PORTF(1, 17) | SE | VE | BK) +#define LCD_D17_GPIO (FUNC(3) | PORTF(1, 17) | SE | VE | BK) +#define LCD_D16 (FUNC(0) | PORTF(1, 16) | SE | VE | BK) +#define LCD_D16_ETM_DA7 (FUNC(2) | PORTF(1, 16) | SE | VE | BK) +#define LCD_D16_GPIO (FUNC(3) | PORTF(1, 16) | SE | VE | BK) +#define LCD_D15 (FUNC(0) | PORTF(1, 15) | SE | VE | BK) +#define LCD_D15_ETM_DA15 (FUNC(2) | PORTF(1, 15) | SE | VE | BK) +#define LCD_D15_GPIO (FUNC(3) | PORTF(1, 15) | SE | VE | BK) +#define LCD_D14 (FUNC(0) | PORTF(1, 14) | SE | VE | BK) +#define LCD_D14_ETM_DA14 (FUNC(2) | PORTF(1, 14) | SE | VE | BK) +#define LCD_D14_GPIO (FUNC(3) | PORTF(1, 14) | SE | VE | BK) +#define LCD_D13 (FUNC(0) | PORTF(1, 13) | SE | VE | BK) +#define LCD_D13_ETM_DA13 (FUNC(2) | PORTF(1, 13) | SE | VE | BK) +#define LCD_D13_GPIO (FUNC(3) | PORTF(1, 13) | SE | VE | BK) +#define LCD_D12 (FUNC(0) | PORTF(1, 12) | SE | VE | BK) +#define LCD_D12_ETM_DA12 (FUNC(2) | PORTF(1, 12) | SE | VE | BK) +#define LCD_D12_GPIO (FUNC(3) | PORTF(1, 12) | SE | VE | BK) +#define LCD_D11 (FUNC(0) | PORTF(1, 11) | SE | VE | BK) +#define LCD_D11_ETM_DA11 (FUNC(2) | PORTF(1, 11) | SE | VE | BK) +#define LCD_D11_GPIO (FUNC(3) | PORTF(1, 11) | SE | VE | BK) +#define LCD_D10 (FUNC(0) | PORTF(1, 10) | SE | VE | BK) +#define LCD_D10_ETM_DA10 (FUNC(2) | PORTF(1, 10) | SE | VE | BK) +#define LCD_D10_GPIO (FUNC(3) | PORTF(1, 10) | SE | VE | BK) +#define LCD_D9 (FUNC(0) | PORTF(1, 9) | SE | VE | BK) +#define LCD_D9_ETM_DA4 (FUNC(1) | PORTF(1, 9) | SE | VE | BK) +#define LCD_D9_ETM_DA9 (FUNC(2) | PORTF(1, 9) | SE | VE | BK) +#define LCD_D9_GPIO (FUNC(3) | PORTF(1, 9) | SE | VE | BK) +#define LCD_D8 (FUNC(0) | PORTF(1, 8) | SE | VE | BK) +#define LCD_D8_ETM_DA3 (FUNC(1) | PORTF(1, 8) | SE | VE | BK) +#define LCD_D8_ETM_DA8 (FUNC(2) | PORTF(1, 8) | SE | VE | BK) +#define LCD_D8_GPIO (FUNC(3) | PORTF(1, 8) | SE | VE | BK) +#define LCD_D7 (FUNC(0) | PORTF(1, 7) | SE | VE | BK) +#define LCD_D7_ETM_DA7 (FUNC(2) | PORTF(1, 7) | SE | VE | BK) +#define LCD_D7_GPIO (FUNC(3) | PORTF(1, 7) | SE | VE | BK) +#define LCD_D6 (FUNC(0) | PORTF(1, 6) | SE | VE | BK) +#define LCD_D6_ETM_DA6 (FUNC(2) | PORTF(1, 6) | SE | VE | BK) +#define LCD_D6_GPIO (FUNC(3) | PORTF(1, 6) | SE | VE | BK) +#define LCD_D5 (FUNC(0) | PORTF(1, 5) | SE | VE | BK) +#define LCD_D5_ETM_DA5 (FUNC(2) | PORTF(1, 5) | SE | VE | BK) +#define LCD_D5_GPIO (FUNC(3) | PORTF(1, 5) | SE | VE | BK) +#define LCD_D4 (FUNC(0) | PORTF(1, 4) | SE | VE | BK) +#define LCD_D4_ETM_DA9 (FUNC(1) | PORTF(1, 4) | SE | VE | BK) +#define LCD_D4_ETM_DA4 (FUNC(2) | PORTF(1, 4) | SE | VE | BK) +#define LCD_D4_GPIO (FUNC(3) | PORTF(1, 4) | SE | VE | BK) +#define LCD_D3 (FUNC(0) | PORTF(1, 3) | SE | VE | BK) +#define LCD_D3_ETM_DA8 (FUNC(1) | PORTF(1, 3) | SE | VE | BK) +#define LCD_D3_ETM_DA3 (FUNC(2) | PORTF(1, 3) | SE | VE | BK) +#define LCD_D3_GPIO (FUNC(3) | PORTF(1, 3) | SE | VE | BK) +#define LCD_D2 (FUNC(0) | PORTF(1, 2) | SE | VE | BK) +#define LCD_D2_ETM_DA2 (FUNC(2) | PORTF(1, 2) | SE | VE | BK) +#define LCD_D2_GPIO (FUNC(3) | PORTF(1, 2) | SE | VE | BK) +#define LCD_D1 (FUNC(0) | PORTF(1, 1) | SE | VE | BK) +#define LCD_D1_ETM_DA1 (FUNC(2) | PORTF(1, 1) | SE | VE | BK) +#define LCD_D1_GPIO (FUNC(3) | PORTF(1, 1) | SE | VE | BK) +#define LCD_D0 (FUNC(0) | PORTF(1, 0) | SE | VE | BK) +#define LCD_D0_ETM_DA0 (FUNC(2) | PORTF(1, 0) | SE | VE | BK) +#define LCD_D0_GPIO (FUNC(3) | PORTF(1, 0) | SE | VE | BK) + +/* Bank 2, GPIO pins 64 ... 95 */ +#define SSP3_D3 (FUNC(0) | PORTF(2, 27) | SE | VE | PE) +#define SSP3_D3_AUART4_CTS (FUNC(1) | PORTF(2, 27) | SE | VE | PE) +#define SSP3_D3_ENET1_1588_EVENT1_IN (FUNC(2) | PORTF(2, 27) | SE | VE | PE) +#define SSP3_D3_GPIO (FUNC(3) | PORTF(2, 27) | SE | VE | PE) +#define SSP3_D0 (FUNC(0) | PORTF(2, 26) | SE | VE | PE) +#define SSP3_D0_AUART4_RTS (FUNC(1) | PORTF(2, 26) | SE | VE | PE) +#define SSP3_D0_ENET1_1588_EVENT1_OUT (FUNC(2) | PORTF(2, 26) | SE | VE | PE) +#define SSP3_D0_GPIO (FUNC(3) | PORTF(2, 26) | SE | VE | PE) +#define SSP3_CMD (FUNC(0) | PORTF(2, 25) | SE | VE | PE) +#define SSP3_CMD_AUART4_RX (FUNC(1) | PORTF(2, 25) | SE | VE | PE) +#define SSP3_CMD_ENET1_1588_EVENT0_IN (FUNC(2) | PORTF(2, 25) | SE | VE | PE) +#define SSP3_CMD_GPIO (FUNC(3) | PORTF(2, 25) | SE | VE | PE) +#define SSP3_SCK (FUNC(0) | PORTF(2, 24) | SE | VE | PE) +#define SSP3_SCK_AUART4_TX (FUNC(1) | PORTF(2, 24) | SE | VE | BK) +#define SSP3_SCK_ENET1_1588_EVENT0_OUT (FUNC(2) | PORTF(2, 24) | SE | VE | BK) +#define SSP3_SCK_GPIO (FUNC(3) | PORTF(2, 24) | SE | VE | BK) +#define SSP2_D5 (FUNC(0) | PORTF(2, 21) | SE | VE | PE) +#define SSP2_D5_SSP2_D2 (FUNC(1) | PORTF(2, 21) | SE | VE | PE) +#define SSP2_D5_USB0_OC (FUNC(2) | PORTF(2, 21) | SE | VE | PE) +#define SSP2_D5_GPIO (FUNC(3) | PORTF(2, 21) | SE | VE | PE) +#define SSP2_D4 (FUNC(0) | PORTF(2, 20) | SE | VE | PE) +#define SSP2_D4_SSP2_D1 (FUNC(1) | PORTF(2, 20) | SE | VE | PE) +#define SSP2_D4_USB1_OC (FUNC(2) | PORTF(2, 20) | SE | VE | PE) +#define SSP2_D4_GPIO (FUNC(3) | PORTF(2, 20) | SE | VE | PE) +#define SSP2_D3 (FUNC(0) | PORTF(2, 19) | SE | VE | PE) +#define SSP2_D3_AUART3_TX (FUNC(1) | PORTF(2, 19) | SE | VE | PE) +#define SSP2_D3_SAIF1_SDATA2 (FUNC(2) | PORTF(2, 19) | SE | VE | PE) +#define SSP2_D3_GPIO (FUNC(3) | PORTF(2, 19) | SE | VE | PE) +#define SSP2_D0 (FUNC(0) | PORTF(2, 18) | SE | VE | PE) +#define SSP2_D0_AUART3_RX (FUNC(1) | PORTF(2, 18) | SE | VE | PE) +#define SSP2_D0_SAIF1_SDATA1 (FUNC(2) | PORTF(2, 18) | SE | VE | PE) +#define SSP2_D0_GPIO (FUNC(3) | PORTF(2, 18) | SE | VE | PE) +#define SSP2_CMD (FUNC(0) | PORTF(2, 17) | SE | VE | PE) +#define SSP2_CMD_AUART2_TX (FUNC(1) | PORTF(2, 17) | SE | VE | PE) +#define SSP2_CMD_SAIF0_SDATA2 (FUNC(2) | PORTF(2, 17) | SE | VE | PE) +#define SSP2_CMD_GPIO (FUNC(3) | PORTF(2, 17) | SE | VE | PE) +#define SSP2_SCK (FUNC(0) | PORTF(2, 16) | SE | VE | BK) +#define SSP2_SCK_AUART2_RX (FUNC(1) | PORTF(2, 16) | SE | VE | BK) +#define SSP2_SCK_SAIF0_SDATA1 (FUNC(2) | PORTF(2, 16) | SE | VE | BK) +#define SSP2_SCK_GPIO (FUNC(3) | PORTF(2, 16) | SE | VE | PE) +#define SSP1_D3 (FUNC(0) | PORTF(2, 15) | SE | VE | PE) +#define SSP1_D3_SSP2_D7 (FUNC(1) | PORTF(2, 15) | SE | VE | PE) +#define SSP1_D3_ENET_1588_EVENT3_IN (FUNC(2) | PORTF(4, 15) | SE | VE | PE) +#define SSP1_D3_GPIO (FUNC(3) | PORTF(2, 15) | SE | VE | PE) +#define SSP1_D0 (FUNC(0) | PORTF(2, 14) | SE | VE | PE) +#define SSP1_D0_SSP2_D6 (FUNC(1) | PORTF(2, 14) | SE | VE | PE) +#define SSP1_D0_ENET_1588_EVENT3_OUT (FUNC(2) | PORTF(2, 14) | SE | VE | PE) +#define SSP1_D0_GPIO (FUNC(3) | PORTF(2, 14) | SE | VE | PE) +#define SSP1_CMD (FUNC(0) | PORTF(2, 13) | SE | VE | PE) +#define SSP1_CMD_SSP2_D2 (FUNC(1) | PORTF(2, 13) | SE | VE | PE) +#define SSP1_CMD_ENET_1588_EVENT2_IN (FUNC(2) | PORTF(2, 13) | SE | VE | PE) +#define SSP1_CMD_GPIO (FUNC(3) | PORTF(2, 13) | SE | VE | PE) +#define SSP1_SCK (FUNC(0) | PORTF(2, 12) | SE | VE | PE) +#define SSP1_SCK_SSP2_D1 (FUNC(1) | PORTF(2, 12) | SE | VE | PE) +#define SSP1_SCK_ENET_1588_EVENT2_OUT (FUNC(2) | PORTF(2, 12) | SE | VE | PE) +#define SSP1_SCK_GPIO (FUNC(3) | PORTF(2, 12) | SE | VE | PE) +#define SSP0_SCK (FUNC(0) | PORTF(2, 10) | SE | VE | BK) +#define SSP0_SCK_GPIO (FUNC(3) | PORTF(2, 10) | SE | VE | BK) +#define SSP0_CD (FUNC(0) | PORTF(2, 9) | SE | VE | PE) +#define SSP0_CD_GPIO (FUNC(3) | PORTF(2, 9) | SE | VE | PE) +#define SSP0_CMD (FUNC(0) | PORTF(2, 8) | SE | VE | PE) +#define SSP0_CMD_GPIO (FUNC(3) | PORTF(2, 8) | SE | VE | PE) +#define SSP0_D7 (FUNC(0) | PORTF(2, 7) | SE | VE | PE) +#define SSP0_D7_SSP2_SCK (FUNC(1) | PORTF(2, 7) | SE | VE | PE) +#define SSP0_D7_GPIO (FUNC(3) | PORTF(2, 7) | SE | VE | PE) +#define SSP0_D6 (FUNC(0) | PORTF(2, 6) | SE | VE | PE) +#define SSP0_D6_SSP2_CMD (FUNC(1) | PORTF(2, 6) | SE | VE | PE) +#define SSP0_D6_GPIO (FUNC(3) | PORTF(2, 6) | SE | VE | PE) +#define SSP0_D5 (FUNC(0) | PORTF(2, 5) | SE | VE | PE) +#define SSP0_D5_SSP2_D3 (FUNC(1) | PORTF(2, 5) | SE | VE | PE) +#define SSP0_D5_GPIO (FUNC(3) | PORTF(2, 5) | SE | VE | PE) +#define SSP0_D4 (FUNC(0) | PORTF(2, 4) | SE | VE | PE) +#define SSP0_D4_SSP2_D0 (FUNC(1) | PORTF(2, 4) | SE | VE | PE) +#define SSP0_D4_GPIO (FUNC(3) | PORTF(2, 4) | SE | VE | PE) +#define SSP0_D3 (FUNC(0) | PORTF(2, 3) | SE | VE | PE) +#define SSP0_D3_GPIO (FUNC(3) | PORTF(2, 3) | SE | VE | PE) +#define SSP0_D2 (FUNC(0) | PORTF(2, 2) | SE | VE | PE) +#define SSP0_D2_GPIO (FUNC(3) | PORTF(2, 2) | SE | VE | PE) +#define SSP0_D1 (FUNC(0) | PORTF(2, 1) | SE | VE | PE) +#define SSP0_D1_GPIO (FUNC(3) | PORTF(2, 1) | SE | VE | PE) +#define SSP0_D0 (FUNC(0) | PORTF(2, 0) | SE | VE | PE) +#define SSP0_D0_GPIO (FUNC(3) | PORTF(2, 0) | SE | VE | PE) + +/* Bank 3, GPIO pins 96 ... 127 */ +#define LCD_RESET (FUNC(0) | PORTF(3, 30) | SE | VE | BK) +#define LCD_RESET_LCD_VSYNC (FUNC(1) | PORTF(3, 30) | SE | VE | BK) +#define LCD_RESET_GPIO (FUNC(3) | PORTF(3, 30) | SE | VE | BK) +#define PWM4 (FUNC(0) | PORTF(3, 29) | SE | VE | BK) +#define PWM4_GPIO (FUNC(3) | PORTF(3, 29) | SE | VE | BK) +#define PWM3 (FUNC(0) | PORTF(3, 28) | SE | VE | BK) +#define PWM3_GPIO (FUNC(3) | PORTF(3, 28) | SE | VE | BK) +#define SPDIF_TX (FUNC(0) | PORTF(3, 27) | SE | VE | BK) +#define SPDIF_TX_ENET1_RX_ER (FUNC(2) | PORTF(3, 27) | SE | VE | BK) +#define SPDIF_TX_GPIO (FUNC(3) | PORTF(3, 27) | SE | VE | BK) +#define SAIF1_SDATA0 (FUNC(0) | PORTF(3, 26) | SE | VE | BK) +#define SAIF1_SDATA0_PWM7 (FUNC(1) | PORTF(3, 26) | SE | VE | BK) +#define SAIF1_SDATA0_SAIF0_SDATA1 (FUNC(2) | PORTF(3, 26) | SE | VE | BK) +#define SAIF1_SDATA0_GPIO (FUNC(3) | PORTF(3, 26) | SE | VE | BK) +#define I2C0_SDA (FUNC(0) | PORTF(3, 25) | SE | VE | BK) +#define I2C0_SDA_TIMROT_ROTARYB (FUNC(1) | PORTF(3, 25) | SE | VE | BK) +#define I2C0_SDA_DUART_TX (FUNC(2) | PORTF(3, 25) | SE | VE | BK) +#define I2C0_SDA_GPIO (FUNC(3) | PORTF(3, 25) | SE | VE | BK) +#define I2C0_SCL (FUNC(0) | PORTF(3, 24) | SE | VE | BK) +#define I2C0_SCL_TIMROT_ROTARYA (FUNC(1) | PORTF(3, 24) | SE | VE | BK) +#define I2C0_SCL_DUART_RX (FUNC(2) | PORTF(3, 24) | SE | VE | BK) +#define I2C0_SCL_GPIO (FUNC(3) | PORTF(3, 24) | SE | VE | BK) +#define SAIF0_SDATA0 (FUNC(0) | PORTF(3, 23) | SE | VE | BK) +#define SAIF0_SDATA0_PWM6 (FUNC(1) | PORTF(3, 23) | SE | VE | BK) +#define SAIF0_SDATA0_AUART4_TX (FUNC(2) | PORTF(3, 23) | SE | VE | BK) +#define SAIF0_SDATA0_GPIO (FUNC(3) | PORTF(3, 23) | SE | VE | BK) +#define SAIF0_BITCLK (FUNC(0) | PORTF(3, 22) | SE | VE | BK) +#define SAIF0_BITCLK_PWM5 (FUNC(1) | PORTF(3, 22) | SE | VE | BK) +#define SAIF0_BITCLK_AUART4_RX (FUNC(2) | PORTF(3, 22) | SE | VE | BK) +#define SAIF0_BITCLK_GPIO (FUNC(3) | PORTF(3, 22) | SE | VE | BK) +#define SAIF0_LRCLK (FUNC(0) | PORTF(3, 21) | SE | VE | BK) +#define SAIF0_LRCLK_PWM4 (FUNC(1) | PORTF(3, 21) | SE | VE | BK) +#define SAIF0_LRCLK_AUART4_RTS (FUNC(2) | PORTF(3, 21) | SE | VE | BK) +#define SAIF0_LRCLK_GPIO (FUNC(3) | PORTF(3, 21) | SE | VE | BK) +#define SAIF0_MCLK (FUNC(0) | PORTF(3, 20) | SE | VE | BK) +#define SAIF0_MCLK_PWM3 (FUNC(1) | PORTF(3, 20) | SE | VE | BK) +#define SAIF0_MCLK_AUART4_CTS (FUNC(2) | PORTF(3, 20) | SE | VE | BK) +#define SAIF0_MCLK_GPIO (FUNC(3) | PORTF(3, 20) | SE | VE | BK) +#define PWM2 (FUNC(0) | PORTF(3, 18) | SE | VE | PE) +#define PWM2_USB0_ID (FUNC(1) | PORTF(3, 18) | SE | VE | PE) +#define PWM2_USB1_OC (FUNC(2) | PORTF(3, 18) | SE | VE | PE) +#define PWM2_GPIO (FUNC(3) | PORTF(3, 18) | SE | VE | PE) +#define PWM1 (FUNC(0) | PORTF(3, 17) | SE | VE | BK) +#define PWM1_I2C1_SDA (FUNC(1) | PORTF(3, 17) | SE | VE | BK) +#define PWM1_DUART_TX (FUNC(2) | PORTF(3, 17) | SE | VE | BK) +#define PWM1_GPIO (FUNC(3) | PORTF(3, 17) | SE | VE | BK) +#define PWM0 (FUNC(0) | PORTF(3, 16) | SE | VE | BK) +#define PWM0_I2C1_SCL (FUNC(1) | PORTF(3, 16) | SE | VE | BK) +#define PWM0_DUART_RX (FUNC(2) | PORTF(3, 16) | SE | VE | BK) +#define PWM0_GPIO (FUNC(3) | PORTF(3, 16) | SE | VE | BK) +#define AUART3_RTS (FUNC(0) | PORTF(3, 15) | SE | VE | BK) +#define AUART3_RTS_CAN1_RX (FUNC(1) | PORTF(3, 15) | SE | VE | BK) +#define AUART3_RTS_ENET0_1588_EVENT1_IN (FUNC(2) | PORTF(3, 15) | SE | VE | BK) +#define AUART3_RTS_GPIO (FUNC(3) | PORTF(3, 15) | SE | VE | BK) +#define AUART3_CTS (FUNC(0) | PORTF(3, 14) | SE | VE | BK) +#define AUART3_CTS_CAN1_TX (FUNC(1) | PORTF(3, 14) | SE | VE | BK) +#define AUART3_CTS_ENET0_1588_EVENT1_OUT (FUNC(2) | PORTF(3, 14) | SE | VE | BK) +#define AUART3_CTS_GPIO (FUNC(3) | PORTF(3, 14) | SE | VE | BK) +#define AUART3_TX (FUNC(0) | PORTF(3, 13) | SE | VE | BK) +#define AUART3_TX_CAN0_RX (FUNC(1) | PORTF(3, 13) | SE | VE | BK) +#define AUART3_TX_ENET0_1588_EVENT0_IN (FUNC(2) | PORTF(3, 13) | SE | VE | BK) +#define AUART3_TX_GPIO (FUNC(3) | PORTF(3, 13) | SE | VE | BK) +#define AUART3_RX (FUNC(0) | PORTF(3, 12) | SE | VE | BK) +#define AUART3_RX_CAN0_TX (FUNC(1) | PORTF(3, 12) | SE | VE | BK) +#define AUART3_RX_ENET0_1588_EVENT0_OUT (FUNC(2) | PORTF(3, 12) | SE | VE | BK) +#define AUART3_RX_GPIO (FUNC(3) | PORTF(3, 12) | SE | VE | BK) +#define AUART2_RTS (FUNC(0) | PORTF(3, 11) | SE | VE | BK) +#define AUART2_RTS_I2C1_SDA (FUNC(1) | PORTF(3, 11) | SE | VE | BK) +#define AUART2_RTS_SAIF1_IRCLK (FUNC(2) | PORTF(3, 11) | SE | VE | BK) +#define AUART2_RTS_GPIO (FUNC(3) | PORTF(3, 11) | SE | VE | BK) +#define AUART2_CTS (FUNC(0) | PORTF(3, 10) | SE | VE | BK) +#define AUART2_CTS_I2C1_SCL (FUNC(1) | PORTF(3, 10) | SE | VE | BK) +#define AUART2_CTS_SAIF1_BITCLK (FUNC(2) | PORTF(3, 10) | SE | VE | BK) +#define AUART2_CTS_GPIO (FUNC(3) | PORTF(3, 10) | SE | VE | BK) +#define AUART2_TX (FUNC(0) | PORTF(3, 9) | SE | VE | PE) +#define AUART2_TX_SSP3_D2 (FUNC(1) | PORTF(3, 9) | SE | VE | PE) +#define AUART2_TX_SSP3_D5 (FUNC(2) | PORTF(3, 9) | SE | VE | PE) +#define AUART2_TX_GPIO (FUNC(3) | PORTF(3, 9) | SE | VE | PE) +#define AUART2_RX (FUNC(0) | PORTF(3, 8) | SE | VE | PE) +#define AUART2_RX_SSP3_D1 (FUNC(1) | PORTF(3, 8) | SE | VE | PE) +#define AUART2_RX_SSP3_D4 (FUNC(2) | PORTF(3, 8) | SE | VE | PE) +#define AUART2_RX_GPIO (FUNC(3) | PORTF(3, 8) | SE | VE | PE) +#define AUART1_RTS (FUNC(0) | PORTF(3, 7) | SE | VE | PE) +#define AUART1_RTS_USB0_ID (FUNC(1) | PORTF(3, 7) | SE | VE | PE) +#define AUART1_RTS_ROTARYB (FUNC(2) | PORTF(3, 7) | SE | VE | PE) +#define AUART1_RTS_GPIO (FUNC(3) | PORTF(3, 7) | SE | VE | PE) +#define AUART1_CTS (FUNC(0) | PORTF(3, 6) | SE | VE | PE) +#define AUART1_CTS_USB0_OC (FUNC(1) | PORTF(3, 6) | SE | VE | PE) +#define AUART1_CTS_ROTARYA (FUNC(2) | PORTF(3, 6) | SE | VE | PE) +#define AUART1_CTS_GPIO (FUNC(3) | PORTF(3, 6) | SE | VE | PE) +#define AUART1_TX (FUNC(0) | PORTF(3, 5) | SE | VE | BK) +#define AUART1_TX_SSP3_CD (FUNC(1) | PORTF(3, 5) | SE | VE | BK) +#define AUART1_TX_PWM1 (FUNC(2) | PORTF(3, 5) | SE | VE | BK) +#define AUART1_TX_GPIO (FUNC(3) | PORTF(3, 5) | SE | VE | BK) +#define AUART1_RX (FUNC(0) | PORTF(3, 4) | SE | VE | BK) +#define AUART1_RX_SSP2_CD (FUNC(1) | PORTF(3, 4) | SE | VE | BK) +#define AUART1_RX_PWM0 (FUNC(2) | PORTF(3, 4) | SE | VE | BK) +#define AUART1_RX_GPIO (FUNC(3) | PORTF(3, 4) | SE | VE | BK) +#define AUART0_RTS (FUNC(0) | PORTF(3, 3) | SE | VE | BK) +#define AUART0_RTS_AUART4_TX (FUNC(1) | PORTF(3, 3) | SE | VE | BK) +#define AUART0_RTS_DUART_TX (FUNC(2) | PORTF(3, 3) | SE | VE | BK) +#define AUART0_RTS_GPIO (FUNC(3) | PORTF(3, 3) | SE | VE | BK) +#define AUART0_CTS (FUNC(0) | PORTF(3, 2) | SE | VE | BK) +#define AUART0_CTS_AUART4_RX (FUNC(1) | PORTF(3, 2) | SE | VE | BK) +#define AUART0_CTS_DUART_RX (FUNC(2) | PORTF(3, 2) | SE | VE | BK) +#define AUART0_CTS_GPIO (FUNC(3) | PORTF(3, 2) | SE | VE | BK) +#define AUART0_TX (FUNC(0) | PORTF(3, 1) | SE | VE | BK) +#define AUART0_TX_I2C0_SDA (FUNC(1) | PORTF(3, 1) | SE | VE | BK) +#define AUART0_TX_DUART_RTS (FUNC(2) | PORTF(3, 1) | SE | VE | BK) +#define AUART0_TX_GPIO (FUNC(3) | PORTF(3, 1) | SE | VE | BK) +#define AUART0_RX (FUNC(0) | PORTF(3, 0) | SE | VE | BK) +#define AUART0_RX_I2C0_SCL (FUNC(1) | PORTF(3, 0) | SE | VE | BK) +#define AUART0_RX_DUART_CTS (FUNC(2) | PORTF(3, 0) | SE | VE | BK) +#define AUART0_RX_GPIO (FUNC(3) | PORTF(3, 0) | SE | VE | BK) + +/* Bank 4, GPIO pins 128 ... 159 */ +#define JTAG_RTCK (FUNC(0) | PORTF(4, 20) | SE | VE | BK) +#define JTAG_RTCK_GPIO (FUNC(3) | PORTF(4, 20) | SE | VE | BK) +#define ENET_CLK (FUNC(0) | PORTF(4, 16) | SE | VE | BK) +#define ENET_CLK_GPIO (FUNC(3) | PORTF(4, 16) | SE | VE | BK) +#define ENET0_CRS (FUNC(0) | PORTF(4, 15) | SE | VE | BK) +#define ENET0_CRS_ENET1_RX_EN (FUNC(1) | PORTF(4, 15) | SE | VE | BK) +#define ENET0_CRS_ENET0_1588_EVENT3_IN (FUNC(2) | PORTF(4, 15) | SE | VE | BK) +#define ENET0_CRS_GPIO (FUNC(3) | PORTF(4, 15) | SE | VE | BK) +#define ENET0_COL (FUNC(0) | PORTF(4, 14) | SE | VE | BK) +#define ENET0_COL_ENET1_TX_EN (FUNC(1) | PORTF(4, 14) | SE | VE | BK) +#define ENET0_COL_1588_EVENT3_OUT (FUNC(2) | PORTF(4, 14) | SE | VE | BK) +#define ENET0_COL_GPIO (FUNC(3) | PORTF(4, 14) | SE | VE | BK) +#define ENET0_RX_CLK (FUNC(0) | PORTF(4, 13) | SE | VE | BK) +#define ENET0_RX_CLK_RX_ER (FUNC(1) | PORTF(4, 13) | SE | VE | BK) +#define ENET0_RX_ENET0_1588_EVENT2_IN (FUNC(2) | PORTF(4, 13) | SE | VE | BK) +#define ENET0_RX_CLK_GPIO (FUNC(3) | PORTF(4, 13) | SE | VE | BK) +#define ENET0_TXD3 (FUNC(0) | PORTF(4, 12) | SE | VE | BK) +#define ENET0_TXD3_ENET1_TXD1 (FUNC(1) | PORTF(4, 12) | SE | VE | BK) +#define ENET0_TXD3_ENET0_1588_EVENT1_IN (FUNC(2) | PORTF(4, 12) | SE | VE | BK) +#define ENET0_TXD3_GPIO (FUNC(3) | PORTF(4, 12) | SE | VE | BK) +#define ENET0_TXD2 (FUNC(0) | PORTF(4, 11) | SE | VE | BK) +#define ENET0_TXD2_ENET1_TXD0 (FUNC(1) | PORTF(4, 11) | SE | VE | BK) +#define ENET0_TXD2_ENET0_1588_EVENT1_OUT (FUNC(2) | PORTF(4, 11) | SE | VE | BK) +#define ENET0_TXD2_GPIO (FUNC(3) | PORTF(4, 11) | SE | VE | BK) +#define ENET0_RXD3 (FUNC(0) | PORTF(4, 10) | SE | VE | BK) +#define ENET0_RXD3_ENET1_RXD1 (FUNC(1) | PORTF(4, 10) | SE | VE | BK) +#define ENET0_RXD3_ENET0_1588_EVENT0_IN (FUNC(2) | PORTF(4, 10) | SE | VE | BK) +#define ENET0_RXD3_GPIO (FUNC(3) | PORTF(4, 10) | SE | VE | BK) +#define ENET0_RXD2 (FUNC(0) | PORTF(4, 9) | SE | VE | BK) +#define ENET0_RXD2_ENET1_RXD0 (FUNC(1) | PORTF(4, 9) | SE | VE | BK) +#define ENET0_RXD2_ENET0_1588_EVENT0_OUT (FUNC(2) | PORTF(4, 9) | SE | VE | BK) +#define ENET0_RXD2_GPIO (FUNC(3) | PORTF(4, 9) | SE | VE | BK) +#define ENET0_TXD1 (FUNC(0) | PORTF(4, 8) | SE | VE | PE) +#define ENET0_TXD1_GPMI_READY7 (FUNC(1) | PORTF(4, 8) | SE | VE | PE) +#define ENET0_TXD1_GPIO (FUNC(3) | PORTF(4, 8) | SE | VE | PE) +#define ENET0_TXD0 (FUNC(0) | PORTF(4, 7) | SE | VE | PE) +#define ENET0_TXD0_GPMI_READY6 (FUNC(1) | PORTF(4, 7) | SE | VE | PE) +#define ENET0_TXD0_GPIO (FUNC(3) | PORTF(4, 7) | SE | VE | PE) +#define ENET0_TX_EN (FUNC(0) | PORTF(4, 6) | SE | VE | PE) +#define ENET0_TX_EN_GPMI_READY5 (FUNC(1) | PORTF(4, 6) | SE | VE | PE) +#define ENET0_TX_EN_GPIO (FUNC(3) | PORTF(4, 6) | SE | VE | PE) +#define ENET0_TX_CLK (FUNC(0) | PORTF(4, 5) | SE | VE | BK) +#define ENET0_TX_CLK_HSADC_TRIGGER (FUNC(1) | PORTF(4, 5) | SE | VE | BK) +#define ENET0_TX_CLK_ENET0_1588_EVENT2_OUT (FUNC(2) | PORTF(4, 5) | SE | VE | BK) +#define ENET0_TX_CLK_GPIO (FUNC(3) | PORTF(4, 5) | SE | VE | BK) +#define ENET0_RXD1 (FUNC(0) | PORTF(4, 4) | SE | VE | PE) +#define ENET0_RXD1_GPMI_READY4 (FUNC(1) | PORTF(4, 4) | SE | VE | PE) +#define ENET0_RXD1_GPIO (FUNC(3) | PORTF(4, 4) | SE | VE | PE) +#define ENET0_RXD0 (FUNC(0) | PORTF(4, 3) | SE | VE | PE) +#define ENET0_RXD0_GPMI_CE7N (FUNC(1) | PORTF(4, 3) | SE | VE | PE) +#define ENET0_RXD0_SAIF1_SDATA2 (FUNC(2) | PORTF(4, 3) | SE | VE | PE) +#define ENET0_RXD0_GPIO (FUNC(3) | PORTF(4, 3) | SE | VE | PE) +#define ENET0_RX_EN (FUNC(0) | PORTF(4, 2) | SE | VE | PE) +#define ENET0_RX_EN_GPMI_CE6N (FUNC(1) | PORTF(4, 2) | SE | VE | PE) +#define ENET0_RX_EN_SAIF1_SDATA1 (FUNC(2) | PORTF(4, 2) | SE | VE | PE) +#define ENET0_RX_EN_GPIO (FUNC(3) | PORTF(4, 2) | SE | VE | PE) +#define ENET0_MDIO (FUNC(0) | PORTF(4, 1) | SE | VE | PE) +#define ENET0_MDIO_GPMI_CE5N (FUNC(1) | PORTF(4, 1) | SE | VE | PE) +#define ENET0_MDIO_SAIF0_SDATA2 (FUNC(2) | PORTF(4, 1) | SE | VE | PE) +#define ENET0_MDIO_GPIO (FUNC(3) | PORTF(4, 1) | SE | VE | PE) +#define ENET0_MDC (FUNC(0) | PORTF(4, 0) | SE | VE | PE) +#define ENET0_MDC_GPMI_CE4N (FUNC(1) | PORTF(4, 0) | SE | VE | PE) +#define ENET0_MDC_SAIF0_SDATA1 (FUNC(2) | PORTF(4, 0) | SE | VE | PE) +#define ENET0_MDC_GPIO (FUNC(3) | PORTF(4, 0) | SE | VE | PE) + +/* + * Bank 5, GPIO pins 160 ... 191 + * Note: These pins are disabled instead of being GPIOs + */ +#define EMI_DDR_OPEN (FUNC(0) | PORTF(5, 26) | BK) +#define EMI_DDR_OPEN_OFF (FUNC(3) | PORTF(5, 26) | BK) +#define EMI_DSQ1 (FUNC(0) | PORTF(5, 23) | BK) +#define EMI_DSQ1_OFF (FUNC(3) | PORTF(5, 23) | BK) +#define EMI_DSQ0 (FUNC(0) | PORTF(5, 22) | BK) +#define EMI_DSQ0_OFF (FUNC(3) | PORTF(5, 22) | BK) +#define EMI_CLK (FUNC(0) | PORTF(5, 21) | BK) +#define EMI_CLK_OFF (FUNC(3) | PORTF(5, 21) | BK) +#define EMI_DDR_OPEN_FB (FUNC(0) | PORTF(5, 20) | BK) +#define EMI_DDR_OPEN_FB_OFF (FUNC(3) | PORTF(5, 20) | BK) +#define EMI_DQM1 (FUNC(0) | PORTF(5, 19) | BK) +#define EMI_DQM1_OFF (FUNC(3) | PORTF(5, 19) | BK) +#define EMI_ODT1 (FUNC(0) | PORTF(5, 18) | BK) +#define EMI_ODT1_OFF (FUNC(3) | PORTF(5, 18) | BK) +#define EMI_DQM0 (FUNC(0) | PORTF(5, 17) | BK) +#define EMI_DQM0_OFF (FUNC(3) | PORTF(5, 17) | BK) +#define EMI_ODT0 (FUNC(0) | PORTF(5, 16) | BK) +#define EMI_ODT0_OFF (FUNC(3) | PORTF(5, 16) | BK) +#define EMI_DATA15 (FUNC(0) | PORTF(5, 15) | BK) +#define EMI_DATA15_OFF (FUNC(3) | PORTF(5, 15) | BK) +#define EMI_DATA14 (FUNC(0) | PORTF(5, 14) | BK) +#define EMI_DATA14_OFF (FUNC(3) | PORTF(5, 14) | BK) +#define EMI_DATA13 (FUNC(0) | PORTF(5, 13) | BK) +#define EMI_DATA13_OFF (FUNC(3) | PORTF(5, 13) | BK) +#define EMI_DATA12 (FUNC(0) | PORTF(5, 12) | BK) +#define EMI_DATA12_OFF (FUNC(3) | PORTF(5, 12) | BK) +#define EMI_DATA11 (FUNC(0) | PORTF(5, 11) | BK) +#define EMI_DATA10_OFF (FUNC(3) | PORTF(5, 10) | BK) +#define EMI_DATA10 (FUNC(0) | PORTF(5, 10) | BK) +#define EMI_DATA10_OFF (FUNC(3) | PORTF(5, 10) | BK) +#define EMI_DATA9 (FUNC(0) | PORTF(5, 9) | BK) +#define EMI_DATA9_OFF (FUNC(3) | PORTF(5, 9) | BK) +#define EMI_DATA8 (FUNC(0) | PORTF(5, 8) | BK) +#define EMI_DATA8_OFF (FUNC(3) | PORTF(5, 8) | BK) +#define EMI_DATA7 (FUNC(0) | PORTF(5, 7) | BK) +#define EMI_DATA7_OFF (FUNC(3) | PORTF(5, 7) | BK) +#define EMI_DATA6 (FUNC(0) | PORTF(5, 6) | BK) +#define EMI_DATA6_OFF (FUNC(3) | PORTF(5, 6) | BK) +#define EMI_DATA5 (FUNC(0) | PORTF(5, 5) | BK) +#define EMI_DATA5_OFF (FUNC(3) | PORTF(5, 5) | BK) +#define EMI_DATA4 (FUNC(0) | PORTF(5, 4) | BK) +#define EMI_DATA4_OFF (FUNC(3) | PORTF(5, 4) | BK) +#define EMI_DATA3 (FUNC(0) | PORTF(5, 3) | BK) +#define EMI_DATA3_OFF (FUNC(3) | PORTF(5, 3) | BK) +#define EMI_DATA2 (FUNC(0) | PORTF(5, 2) | BK) +#define EMI_DATA2_OFF (FUNC(3) | PORTF(5, 2) | BK) +#define EMI_DATA1 (FUNC(0) | PORTF(5, 1) | BK) +#define EMI_DATA1_OFF (FUNC(3) | PORTF(5, 1) | BK) +#define EMI_DATA0 (FUNC(0) | PORTF(5, 0) | BK) +#define EMI_DATA0_OFF (FUNC(3) | PORTF(5, 0) | BK) + +/* + * Bank 6, GPIO pins 192 ... 223 + * Note: This pins are disabled instead of being GPIOs + */ +#define EMI_CKE (FUNC(0) | PORTF(6, 24) | BK) +#define EMI_CKE_OFF (FUNC(3) | PORTF(6, 24) | BK) +#define EMI_CE1N (FUNC(0) | PORTF(6, 23) | BK) +#define EMI_CE1N_OFF (FUNC(3) | PORTF(6, 23) | BK) +#define EMI_CE0N (FUNC(0) | PORTF(6, 22) | BK) +#define EMI_CE0N_OFF (FUNC(3) | PORTF(6, 22) | BK) +#define EMI_WEN (FUNC(0) | PORTF(6, 21) | BK) +#define EMI_WEN_OFF (FUNC(3) | PORTF(6, 21) | BK) +#define EMI_RASN (FUNC(0) | PORTF(6, 20) | BK) +#define EMI_RASN_OFF (FUNC(3) | PORTF(6, 20) | BK) +#define EMI_CASN (FUNC(0) | PORTF(6, 19) | BK) +#define EMI_CASN_OFF (FUNC(3) | PORTF(6, 19) | BK) +#define EMI_BA2 (FUNC(0) | PORTF(6, 18) | BK) +#define EMI_BA2_OFF (FUNC(3) | PORTF(6, 18) | BK) +#define EMI_BA1 (FUNC(0) | PORTF(6, 17) | BK) +#define EMI_BA1_OFF (FUNC(3) | PORTF(6, 17) | BK) +#define EMI_BA0 (FUNC(0) | PORTF(6, 16) | BK) +#define EMI_BA0_OFF (FUNC(3) | PORTF(6, 16) | BK) +#define EMI_A14 (FUNC(0) | PORTF(6, 14) | BK) +#define EMI_A14_OFF (FUNC(3) | PORTF(6, 14) | BK) +#define EMI_A13 (FUNC(0) | PORTF(6, 13) | BK) +#define EMI_A13_OFF (FUNC(3) | PORTF(6, 13) | BK) +#define EMI_A12 (FUNC(0) | PORTF(6, 12) | BK) +#define EMI_A12_OFF (FUNC(3) | PORTF(6, 12) | BK) +#define EMI_A11 (FUNC(0) | PORTF(6, 11) | BK) +#define EMI_A11_OFF (FUNC(3) | PORTF(6, 11) | BK) +#define EMI_A10 (FUNC(0) | PORTF(6, 10) | BK) +#define EMI_A10_OFF (FUNC(3) | PORTF(6, 10) | BK) +#define EMI_A9 (FUNC(0) | PORTF(6, 9) | BK) +#define EMI_A9_OFF (FUNC(3) | PORTF(6, 9) | BK) +#define EMI_A8 (FUNC(0) | PORTF(6, 8) | BK) +#define EMI_A8_OFF (FUNC(3) | PORTF(6, 8) | BK) +#define EMI_A7 (FUNC(0) | PORTF(6, 7) | BK) +#define EMI_A7_OFF (FUNC(3) | PORTF(6, 7) | BK) +#define EMI_A6 (FUNC(0) | PORTF(6, 6) | BK) +#define EMI_A6_OFF (FUNC(3) | PORTF(6, 6) | BK) +#define EMI_A5 (FUNC(0) | PORTF(6, 5) | BK) +#define EMI_A5_OFF (FUNC(3) | PORTF(6, 5) | BK) +#define EMI_A4 (FUNC(0) | PORTF(6, 4) | BK) +#define EMI_A4_OFF (FUNC(3) | PORTF(6, 4) | BK) +#define EMI_A3 (FUNC(0) | PORTF(6, 3) | BK) +#define EMI_A3_OFF (FUNC(3) | PORTF(6, 3) | BK) +#define EMI_A2 (FUNC(0) | PORTF(6, 2) | BK) +#define EMI_A2_OFF (FUNC(3) | PORTF(6, 2) | BK) +#define EMI_A1 (FUNC(0) | PORTF(6, 1) | BK) +#define EMI_A1_OFF (FUNC(3) | PORTF(6, 1) | BK) +#define EMI_A0 (FUNC(0) | PORTF(6, 0) | BK) +#define EMI_A0_OFF (FUNC(3) | PORTF(6, 0) | BK) + +#endif /* __MACH_IOMUX_IMX28_H */ diff --git a/include/mach/mxs/iomux.h b/include/mach/mxs/iomux.h new file mode 100644 index 0000000000..b61661263e --- /dev/null +++ b/include/mach/mxs/iomux.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2010 Juergen Beisert, Pengutronix */ + +#ifndef __ASM_MACH_IOMUX_H +#define __ASM_MACH_IOMUX_H + +#include <types.h> + +/* + * The muxable pins on i.MX23 are organized in 4 banks. On i.MX28 there are 7 + * banks. Each bank has up to 32 pins each. Furthermore for each pin some of the + * following properties can be configured: + * - drive strength: 4 mA, 8 mA, 12 mA or 16 mA + * - pull up enabled or bit keeper enabled (a pin cannot have both) + * - voltage: 1.8 V, 2.5 V (i.MX23 only) or 3.3 V (i.MX28 only) + * - function: 0..3, with 3 being the GPIO functionality + * + * So a configuration for a given pin can be described in an unsigned integer of + * length 32: + * - [ 4: 0] bank pin + * - [ 7: 5] bank + * - [ 8] 1 iff pin has a switchable pull up + * - [ 9] 1 iff pin has a switchable bit keeper + * - [ 10] 1 iff pin has switchable drive strength + * - [ 11] 1 iff pin has switchable voltage + * - [13:12] function + * - [ 14] 1 for enabled pull up + * - [ 15] 1 iff [14] is a valid pull up value + * - [ 16] 1 for enabled bit keeper + * - [ 17] 1 iff [16] is a valid bit keeper value + * - [19:18] value for drive strength i -> i * 4 mA + * - [ 20] 1 iff [19:18] is valid + * - [ 21] 0 for 1.8 V, 1 for 2.5 V resp. 3.3 V + * - [ 22] 1 iff [21] is valid + * - [ 23] 1 iff configure as GPIO out if function == 3 (i.e. GPIO) + * - [ 24] initial value iff configured as GPIO out + * - [ 25] error + */ + +#define BANKPIN(p) (((p) & 31) | ERROR((p) & ~31)) +#define BANK(b) ((((b) & 7) << 5) | (ERROR((b) & ~7))) +#define PE (1 << 8) +#define BK (1 << 9) +#define SE (1 << 10) +#define VE (1 << 11) +#define FUNC(f) ((((f) & 3) << 12) | (ERROR((f) & ~3))) +#define PULLUP(p) ((((p) & 1) << 14) | PEVALID | ERROR((p) & ~1)) +#define PEVALID (1 << 15) +#define BITKEEPER(b) ((((b) & 1) << 16) | BKVALID | ERROR((b) & ~1)) +#define BKVALID (1 << 17) +#define STRENGTH(s) ((((s) & 3) << 18) | SEVALID | ERROR((s) & ~3)) +#define S4MA 0 +#define S8MA 1 +#define S12MA 2 +#define S16MA 3 +#define SEVALID (1 << 20) +#define VOLTAGE(v) ((((v) & 1) << 21) | VEVALID | ERROR((v) & ~1)) +#define VE_1_8V VOLTAGE(0) +#define VEVALID (1 << 22) + +#define GPIO_OUT (1 << 23) +#define GPIO_IN (0 << 23) +#define GPIO_VALUE(v) ((((v) & 1) << 24) | ERROR((v) & ~1)) + +#define ERROR(x) (!!(x) << 25) + +#define GET_GPIO_NO(m) ((m) & 0xff) +#define GET_FUNC(m) (((m) >> 12) & 3) +#define PE_PRESENT(m) ((m) & PE) +#define GET_PULLUP(m) (((m) >> 14) & 1) +#define BK_PRESENT(m) ((m) & BK) +#define GET_BITKEEPER(m)(((m) >> 16) & 1) +#define SE_PRESENT(m) ((m) & SE) +#define GET_STRENGTH(m) (((m) >> 18) & 3) +#define VE_PRESENT(m) ((m) & VE) +#define GET_VOLTAGE(m) (((m) >> 21) & 1) +#define GET_GPIODIR(m) (!!((m) & GPIO_OUT)) +#define GET_GPIOVAL(m) (!!((m) & GPIO_VALUE(1))) +#define IS_GPIO 3 + +#if defined CONFIG_ARCH_IMX23 +/* + * The pin definition of i.MX23 are strange. Bank 0's pins 0 .. 15 are defined + * using PORTF(0, 0) .. PORTF(0, 15). Its pins 16 .. 31 however use PORTF(1, 0) + * .. PORTF(1, 15). So the PORTF macro is more ugly than necessary. + */ +# define PORTF(bank,bit) (BANK((bank) / 2) | BANKPIN((((bank) & 1) << 4) | (bit)) | ERROR((bit) & ~15) | ERROR((bank) & ~7)) +# define VE_2_5V VOLTAGE(0) +#include <mach/mxs/iomux-imx23.h> +#endif + +#if defined CONFIG_ARCH_IMX28 +# define PORTF(bank,bit) (BANK(bank) | BANKPIN(bit)) +# define VE_3_3V VOLTAGE(1) +#include <mach/mxs/iomux-imx28.h> +#endif + +void imx_gpio_mode(uint32_t); + +#endif /* __ASM_MACH_IOMUX_H */ diff --git a/include/mach/mxs/mci.h b/include/mach/mxs/mci.h new file mode 100644 index 0000000000..3383635dfc --- /dev/null +++ b/include/mach/mxs/mci.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MACH_MMC_H +#define __MACH_MMC_H + +struct mxs_mci_platform_data { + const char *devname; + unsigned caps; /**< supported operating modes (MMC_MODE_*) */ + unsigned voltages; /**< supported voltage range (MMC_VDD_*) */ + unsigned f_min; /**< min operating frequency in Hz (0 -> no limit) */ + unsigned f_max; /**< max operating frequency in Hz (0 -> no limit) */ + /* TODO */ + /* function to modify the voltage */ + /* function to switch the voltage */ + /* function to detect the presence of a SD card in the socket */ +}; + +#endif /* __MACH_MMC_H */ diff --git a/include/mach/mxs/ocotp.h b/include/mach/mxs/ocotp.h new file mode 100644 index 0000000000..86b30c96e1 --- /dev/null +++ b/include/mach/mxs/ocotp.h @@ -0,0 +1,12 @@ +/* + * Header file for mxs ocotp driver - same license as driver + * + * Copyright (C) 2012 by Wolfram Sang, Pengutronix e.K. + */ + +#ifndef __MACH_OCOTP_H +#define __MACH_OCOTP_H + +int mxs_ocotp_read(void *buf, int count, int offset); + +#endif /* __MACH_OCOTP_H */ diff --git a/include/mach/mxs/power.h b/include/mach/mxs/power.h new file mode 100644 index 0000000000..9d0ea89bca --- /dev/null +++ b/include/mach/mxs/power.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MACH_POWER_H +#define __MACH_POWER_H + +void imx_power_prepare_usbphy(void); +int imx_get_vddio(void); +int imx_set_vddio(int); + +#endif /* __MACH_POWER_H */ diff --git a/include/mach/mxs/regs-clkctrl-mx23.h b/include/mach/mxs/regs-clkctrl-mx23.h new file mode 100644 index 0000000000..ad3e7a21b1 --- /dev/null +++ b/include/mach/mxs/regs-clkctrl-mx23.h @@ -0,0 +1,208 @@ +/* + * Freescale i.MX23 CLKCTRL Register Definitions + * + * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX23_REGS_CLKCTRL_H__ +#define __MX23_REGS_CLKCTRL_H__ + +#include <mach/mxs/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mxs_clkctrl_regs { + mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ + uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */ + uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */ + mxs_reg_32(hw_clkctrl_cpu) /* 0x20 */ + mxs_reg_32(hw_clkctrl_hbus) /* 0x30 */ + mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */ + mxs_reg_32(hw_clkctrl_xtal) /* 0x50 */ + mxs_reg_32(hw_clkctrl_pix) /* 0x60 */ + mxs_reg_32(hw_clkctrl_ssp0) /* 0x70 */ + mxs_reg_32(hw_clkctrl_gpmi) /* 0x80 */ + mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */ + mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */ + + uint32_t reserved1[4]; + + mxs_reg_32(hw_clkctrl_saif0) /* 0xc0 */ + mxs_reg_32(hw_clkctrl_tv) /* 0xd0 */ + mxs_reg_32(hw_clkctrl_etm) /* 0xe0 */ + mxs_reg_8(hw_clkctrl_frac0) /* 0xf0 */ + mxs_reg_8(hw_clkctrl_frac1) /* 0x100 */ + mxs_reg_32(hw_clkctrl_clkseq) /* 0x110 */ + mxs_reg_32(hw_clkctrl_reset) /* 0x120 */ + mxs_reg_32(hw_clkctrl_status) /* 0x130 */ + mxs_reg_32(hw_clkctrl_version) /* 0x140 */ +}; +#endif + +#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 +#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) +#define CLKCTRL_PLL0CTRL0_POWER (1 << 16) + +#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) +#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 + +#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) +#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) +#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) +#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 +#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) +#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) +#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f +#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 + +#define CLKCTRL_HBUS_BUSY (1 << 29) +#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 28) +#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 27) +#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) +#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) +#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) +#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) +#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) +#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) +#define CLKCTRL_HBUS_AUTO_SLOW_MODE (1 << 20) +#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 +#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) +#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) +#define CLKCTRL_HBUS_DIV_MASK 0x1f +#define CLKCTRL_HBUS_DIV_OFFSET 0 + +#define CLKCTRL_XBUS_BUSY (1 << 31) +#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_XBUS_DIV_MASK 0x3ff +#define CLKCTRL_XBUS_DIV_OFFSET 0 + +#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) +#define CLKCTRL_XTAL_FILT_CLK24M_GATE (1 << 30) +#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) +#define CLKCTRL_XTAL_DRI_CLK24M_GATE (1 << 28) +#define CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE (1 << 27) +#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) +#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 +#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 + +#define CLKCTRL_PIX_CLKGATE (1 << 31) +#define CLKCTRL_PIX_BUSY (1 << 29) +#define CLKCTRL_PIX_DIV_FRAC_EN (1 << 12) +#define CLKCTRL_PIX_DIV_MASK 0xfff +#define CLKCTRL_PIX_DIV_OFFSET 0 + +#define CLKCTRL_SSP_CLKGATE (1 << 31) +#define CLKCTRL_SSP_BUSY (1 << 29) +#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) +#define CLKCTRL_SSP_DIV_MASK 0x1ff +#define CLKCTRL_SSP_DIV_OFFSET 0 + +#define CLKCTRL_GPMI_CLKGATE (1 << 31) +#define CLKCTRL_GPMI_BUSY (1 << 29) +#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_GPMI_DIV_MASK 0x3ff +#define CLKCTRL_GPMI_DIV_OFFSET 0 + +#define CLKCTRL_SPDIF_CLKGATE (1 << 31) + +#define CLKCTRL_EMI_CLKGATE (1 << 31) +#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) +#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) +#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) +#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) +#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) +#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) +#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) +#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 +#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f +#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 + +#define CLKCTRL_IR_CLKGATE (1 << 31) +#define CLKCTRL_IR_AUTO_DIV (1 << 29) +#define CLKCTRL_IR_IR_BUSY (1 << 28) +#define CLKCTRL_IR_IROV_BUSY (1 << 27) +#define CLKCTRL_IR_IROV_DIV_MASK (0x1ff << 16) +#define CLKCTRL_IR_IROV_DIV_OFFSET 16 +#define CLKCTRL_IR_IR_DIV_MASK 0x3ff +#define CLKCTRL_IR_IR_DIV_OFFSET 0 + +#define CLKCTRL_SAIF0_CLKGATE (1 << 31) +#define CLKCTRL_SAIF0_BUSY (1 << 29) +#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF0_DIV_MASK 0xffff +#define CLKCTRL_SAIF0_DIV_OFFSET 0 + +#define CLKCTRL_TV_CLK_TV108M_GATE (1 << 31) +#define CLKCTRL_TV_CLK_TV_GATE (1 << 30) + +#define CLKCTRL_ETM_CLKGATE (1 << 31) +#define CLKCTRL_ETM_BUSY (1 << 29) +#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 6) +#define CLKCTRL_ETM_DIV_MASK 0x3f +#define CLKCTRL_ETM_DIV_OFFSET 0 + +#define CLKCTRL_FRAC_CLKGATE (1 << 7) +#define CLKCTRL_FRAC_STABLE (1 << 6) +#define CLKCTRL_FRAC_FRAC_MASK 0x3f +#define CLKCTRL_FRAC_FRAC_OFFSET 0 +#define CLKCTRL_FRAC0_CPU 0 +#define CLKCTRL_FRAC0_EMI 1 +#define CLKCTRL_FRAC0_PIX 2 +#define CLKCTRL_FRAC0_IO0 3 +#define CLKCTRL_FRAC1_VID 3 + +#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) +#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7) +#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6) +#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 5) +#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4) +#define CLKCTRL_CLKSEQ_BYPASS_IR (1 << 3) +#define CLKCTRL_CLKSEQ_BYPASS_PIX (1 << 1) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF (1 << 0) + +#define CLKCTRL_RESET_CHIP (1 << 1) +#define CLKCTRL_RESET_DIG (1 << 0) + +#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) +#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 + +#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) +#define CLKCTRL_VERSION_MAJOR_OFFSET 24 +#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) +#define CLKCTRL_VERSION_MINOR_OFFSET 16 +#define CLKCTRL_VERSION_STEP_MASK 0xffff +#define CLKCTRL_VERSION_STEP_OFFSET 0 + +#endif /* __MX23_REGS_CLKCTRL_H__ */ diff --git a/include/mach/mxs/regs-clkctrl-mx28.h b/include/mach/mxs/regs-clkctrl-mx28.h new file mode 100644 index 0000000000..ce01892274 --- /dev/null +++ b/include/mach/mxs/regs-clkctrl-mx28.h @@ -0,0 +1,283 @@ +/* + * Freescale i.MX28 CLKCTRL Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX28_REGS_CLKCTRL_H__ +#define __MX28_REGS_CLKCTRL_H__ + +#include <mach/mxs/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mxs_clkctrl_regs { + mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ + uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */ + uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */ + mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ + uint32_t hw_clkctrl_pll1ctrl1; /* 0x30 */ + uint32_t reserved_pll1ctrl1[3]; /* 0x34-0x3c */ + mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ + mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */ + mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */ + mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */ + mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */ + mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */ + mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ + mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ + mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ + mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ + mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */ + mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */ + mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */ + mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */ + mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */ + mxs_reg_32(hw_clkctrl_etm) /* 0x130 */ + mxs_reg_32(hw_clkctrl_enet) /* 0x140 */ + mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */ + mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */ + + uint32_t reserved[16]; + + mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ + mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ + mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ + mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */ + mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */ + mxs_reg_32(hw_clkctrl_version) /* 0x200 */ +}; +#endif + +#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 +#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) +#define CLKCTRL_PLL0CTRL0_POWER (1 << 17) + +#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) +#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 + +#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) +#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20 +#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) +#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18) +#define CLKCTRL_PLL1CTRL0_POWER (1 << 17) + +#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31) +#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff +#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0 + +#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) +#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26) +#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL2CTRL0_POWER (1 << 23) + +#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) +#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) +#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) +#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 +#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) +#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) +#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f +#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 + +#define CLKCTRL_HBUS_ASM_BUSY (1 << 31) +#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30) +#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29) +#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27) +#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) +#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) +#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) +#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) +#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) +#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) +#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20) +#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19) +#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 +#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) +#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) +#define CLKCTRL_HBUS_DIV_MASK 0x1f +#define CLKCTRL_HBUS_DIV_OFFSET 0 + +#define CLKCTRL_XBUS_BUSY (1 << 31) +#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11) +#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_XBUS_DIV_MASK 0x3ff +#define CLKCTRL_XBUS_DIV_OFFSET 0 + +#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) +#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) +#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) +#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 +#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 + +#define CLKCTRL_SSP_CLKGATE (1 << 31) +#define CLKCTRL_SSP_BUSY (1 << 29) +#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) +#define CLKCTRL_SSP_DIV_MASK 0x1ff +#define CLKCTRL_SSP_DIV_OFFSET 0 + +#define CLKCTRL_GPMI_CLKGATE (1 << 31) +#define CLKCTRL_GPMI_BUSY (1 << 29) +#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_GPMI_DIV_MASK 0x3ff +#define CLKCTRL_GPMI_DIV_OFFSET 0 + +#define CLKCTRL_SPDIF_CLKGATE (1 << 31) + +#define CLKCTRL_EMI_CLKGATE (1 << 31) +#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) +#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) +#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) +#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) +#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) +#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) +#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) +#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 +#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f +#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 + +#define CLKCTRL_SAIF0_CLKGATE (1 << 31) +#define CLKCTRL_SAIF0_BUSY (1 << 29) +#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF0_DIV_MASK 0xffff +#define CLKCTRL_SAIF0_DIV_OFFSET 0 + +#define CLKCTRL_SAIF1_CLKGATE (1 << 31) +#define CLKCTRL_SAIF1_BUSY (1 << 29) +#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF1_DIV_MASK 0xffff +#define CLKCTRL_SAIF1_DIV_OFFSET 0 + +#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31) +#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) +#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13) +#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff +#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0 + +#define CLKCTRL_ETM_CLKGATE (1 << 31) +#define CLKCTRL_ETM_BUSY (1 << 29) +#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7) +#define CLKCTRL_ETM_DIV_MASK 0x7f +#define CLKCTRL_ETM_DIV_OFFSET 0 + +#define CLKCTRL_ENET_SLEEP (1 << 31) +#define CLKCTRL_ENET_DISABLE (1 << 30) +#define CLKCTRL_ENET_STATUS (1 << 29) +#define CLKCTRL_ENET_BUSY_TIME (1 << 27) +#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21) +#define CLKCTRL_ENET_DIV_TIME_OFFSET 21 +#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19) +#define CLKCTRL_ENET_TIME_SEL_OFFSET 19 +#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19) +#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19) +#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19) +#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19) +#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) +#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17) +#define CLKCTRL_ENET_RESET_BY_SW (1 << 16) + +#define CLKCTRL_HSADC_RESETB (1 << 30) +#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28) +#define CLKCTRL_HSADC_FREQDIV_OFFSET 28 + +#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30) +#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29) +#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) +#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) + +#define CLKCTRL_FRAC_CLKGATE (1 << 7) +#define CLKCTRL_FRAC_STABLE (1 << 6) +#define CLKCTRL_FRAC_FRAC_MASK 0x3f +#define CLKCTRL_FRAC_FRAC_OFFSET 0 +#define CLKCTRL_FRAC0_CPU 0 +#define CLKCTRL_FRAC0_EMI 1 +#define CLKCTRL_FRAC0_IO1 2 +#define CLKCTRL_FRAC0_IO0 3 +#define CLKCTRL_FRAC1_PIX 0 +#define CLKCTRL_FRAC1_HSADC 1 +#define CLKCTRL_FRAC1_GPMI 2 + +#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) +#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) +#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) +#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) +#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) +#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) +#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) + +#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5) +#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4) +#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3) +#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2) +#define CLKCTRL_RESET_CHIP (1 << 1) +#define CLKCTRL_RESET_DIG (1 << 0) + +#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) +#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 + +#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) +#define CLKCTRL_VERSION_MAJOR_OFFSET 24 +#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) +#define CLKCTRL_VERSION_MINOR_OFFSET 16 +#define CLKCTRL_VERSION_STEP_MASK 0xffff +#define CLKCTRL_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_CLKCTRL_H__ */ diff --git a/include/mach/mxs/regs-common.h b/include/mach/mxs/regs-common.h new file mode 100644 index 0000000000..e54a220fa3 --- /dev/null +++ b/include/mach/mxs/regs-common.h @@ -0,0 +1,69 @@ +/* + * Freescale i.MXS Register Accessors + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MXS_REGS_COMMON_H__ +#define __MXS_REGS_COMMON_H__ + +/* + * The i.MXS has interesting feature when it comes to register access. There + * are four kinds of access to one particular register. Those are: + * + * 1) Common read/write access. To use this mode, just write to the address of + * the register. + * 2) Set bits only access. To set bits, write which bits you want to set to the + * address of the register + 0x4. + * 3) Clear bits only access. To clear bits, write which bits you want to clear + * to the address of the register + 0x8. + * 4) Toggle bits only access. To toggle bits, write which bits you want to + * toggle to the address of the register + 0xc. + * + * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits + * can be set/cleared by pure write as in access type 1, some need to be + * explicitly set/cleared by using access type 2-3. + * + * The following macros and structures allow the user to either access the + * register in all aforementioned modes (by accessing reg_name, reg_name_set, + * reg_name_clr, reg_name_tog) or pass the register structure further into + * various functions with correct type information (by accessing reg_name_reg). + * + */ + +#define __mxs_reg_8(name) \ + uint8_t name[4]; \ + uint8_t name##_set[4]; \ + uint8_t name##_clr[4]; \ + uint8_t name##_tog[4]; \ + +#define __mxs_reg_32(name) \ + uint32_t name; \ + uint32_t name##_set; \ + uint32_t name##_clr; \ + uint32_t name##_tog; + +struct mxs_register_8 { + __mxs_reg_8(reg) +}; + +struct mxs_register_32 { + __mxs_reg_32(reg) +}; + +#define mxs_reg_8(name) \ + union { \ + struct { __mxs_reg_8(name) }; \ + struct mxs_register_8 name##_reg; \ + }; + +#define mxs_reg_32(name) \ + union { \ + struct { __mxs_reg_32(name) }; \ + struct mxs_register_32 name##_reg; \ + }; + +#endif /* __MXS_REGS_COMMON_H__ */ diff --git a/include/mach/mxs/regs-lradc.h b/include/mach/mxs/regs-lradc.h new file mode 100644 index 0000000000..02e6b9bf09 --- /dev/null +++ b/include/mach/mxs/regs-lradc.h @@ -0,0 +1,387 @@ +/* + * Freescale i.MX28 LRADC Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX28_REGS_LRADC_H__ +#define __MX28_REGS_LRADC_H__ + +#include <mach/mxs/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mxs_lradc_regs { + mxs_reg_32(hw_lradc_ctrl0); + mxs_reg_32(hw_lradc_ctrl1); + mxs_reg_32(hw_lradc_ctrl2); + mxs_reg_32(hw_lradc_ctrl3); + mxs_reg_32(hw_lradc_status); + mxs_reg_32(hw_lradc_ch0); + mxs_reg_32(hw_lradc_ch1); + mxs_reg_32(hw_lradc_ch2); + mxs_reg_32(hw_lradc_ch3); + mxs_reg_32(hw_lradc_ch4); + mxs_reg_32(hw_lradc_ch5); + mxs_reg_32(hw_lradc_ch6); + mxs_reg_32(hw_lradc_ch7); + mxs_reg_32(hw_lradc_delay0); + mxs_reg_32(hw_lradc_delay1); + mxs_reg_32(hw_lradc_delay2); + mxs_reg_32(hw_lradc_delay3); + mxs_reg_32(hw_lradc_debug0); + mxs_reg_32(hw_lradc_debug1); + mxs_reg_32(hw_lradc_conversion); + mxs_reg_32(hw_lradc_ctrl4); + mxs_reg_32(hw_lradc_treshold0); + mxs_reg_32(hw_lradc_treshold1); + mxs_reg_32(hw_lradc_version); +}; +#endif + +#define LRADC_CTRL0_SFTRST (1 << 31) +#define LRADC_CTRL0_CLKGATE (1 << 30) +#define LRADC_CTRL0_ONCHIP_GROUNDREF (1 << 26) +#define LRADC_CTRL0_BUTTON1_DETECT_ENABLE (1 << 25) +#define LRADC_CTRL0_BUTTON0_DETECT_ENABLE (1 << 24) +#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23) +#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22) +#define LRADC_CTRL0_YNLRSW (1 << 21) +#define LRADC_CTRL0_YPLLSW_MASK (0x3 << 19) +#define LRADC_CTRL0_YPLLSW_OFFSET 19 +#define LRADC_CTRL0_XNURSW_MASK (0x3 << 17) +#define LRADC_CTRL0_XNURSW_OFFSET 17 +#define LRADC_CTRL0_XPULSW (1 << 16) +#define LRADC_CTRL0_SCHEDULE_MASK 0xff +#define LRADC_CTRL0_SCHEDULE_OFFSET 0 + +#define LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN (1 << 28) +#define LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN (1 << 27) +#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN (1 << 26) +#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN (1 << 25) +#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24) +#define LRADC_CTRL1_LRADC7_IRQ_EN (1 << 23) +#define LRADC_CTRL1_LRADC6_IRQ_EN (1 << 22) +#define LRADC_CTRL1_LRADC5_IRQ_EN (1 << 21) +#define LRADC_CTRL1_LRADC4_IRQ_EN (1 << 20) +#define LRADC_CTRL1_LRADC3_IRQ_EN (1 << 19) +#define LRADC_CTRL1_LRADC2_IRQ_EN (1 << 18) +#define LRADC_CTRL1_LRADC1_IRQ_EN (1 << 17) +#define LRADC_CTRL1_LRADC0_IRQ_EN (1 << 16) +#define LRADC_CTRL1_BUTTON1_DETECT_IRQ (1 << 12) +#define LRADC_CTRL1_BUTTON0_DETECT_IRQ (1 << 11) +#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ (1 << 10) +#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ (1 << 9) +#define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8) +#define LRADC_CTRL1_LRADC7_IRQ (1 << 7) +#define LRADC_CTRL1_LRADC6_IRQ (1 << 6) +#define LRADC_CTRL1_LRADC5_IRQ (1 << 5) +#define LRADC_CTRL1_LRADC4_IRQ (1 << 4) +#define LRADC_CTRL1_LRADC3_IRQ (1 << 3) +#define LRADC_CTRL1_LRADC2_IRQ (1 << 2) +#define LRADC_CTRL1_LRADC1_IRQ (1 << 1) +#define LRADC_CTRL1_LRADC0_IRQ (1 << 0) + +#define LRADC_CTRL2_DIVIDE_BY_TWO_MASK (0xff << 24) +#define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24 +#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15) +#define LRADC_CTRL2_VTHSENSE_MASK (0x3 << 13) +#define LRADC_CTRL2_VTHSENSE_OFFSET 13 +#define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS (1 << 12) +#define LRADC_CTRL2_TEMP_SENSOR_IENABLE1 (1 << 9) +#define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 (1 << 8) +#define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4) +#define LRADC_CTRL2_TEMP_ISRC1_OFFSET 4 +#define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4) +#define LRADC_CTRL2_TEMP_ISRC1_280 (0xe << 4) +#define LRADC_CTRL2_TEMP_ISRC1_260 (0xd << 4) +#define LRADC_CTRL2_TEMP_ISRC1_240 (0xc << 4) +#define LRADC_CTRL2_TEMP_ISRC1_220 (0xb << 4) +#define LRADC_CTRL2_TEMP_ISRC1_200 (0xa << 4) +#define LRADC_CTRL2_TEMP_ISRC1_180 (0x9 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_160 (0x8 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_140 (0x7 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_120 (0x6 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_100 (0x5 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_80 (0x4 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_60 (0x3 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_40 (0x2 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_20 (0x1 << 4) +#define LRADC_CTRL2_TEMP_ISRC1_ZERO (0x0 << 4) +#define LRADC_CTRL2_TEMP_ISRC0_MASK (0xf << 0) +#define LRADC_CTRL2_TEMP_ISRC0_OFFSET 0 +#define LRADC_CTRL2_TEMP_ISRC0_300 (0xf << 0) +#define LRADC_CTRL2_TEMP_ISRC0_280 (0xe << 0) +#define LRADC_CTRL2_TEMP_ISRC0_260 (0xd << 0) +#define LRADC_CTRL2_TEMP_ISRC0_240 (0xc << 0) +#define LRADC_CTRL2_TEMP_ISRC0_220 (0xb << 0) +#define LRADC_CTRL2_TEMP_ISRC0_200 (0xa << 0) +#define LRADC_CTRL2_TEMP_ISRC0_180 (0x9 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_160 (0x8 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_140 (0x7 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_120 (0x6 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_100 (0x5 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_80 (0x4 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_60 (0x3 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_40 (0x2 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_20 (0x1 << 0) +#define LRADC_CTRL2_TEMP_ISRC0_ZERO (0x0 << 0) + +#define LRADC_CTRL3_DISCARD_MASK (0x3 << 24) +#define LRADC_CTRL3_DISCARD_OFFSET 24 +#define LRADC_CTRL3_DISCARD_1_SAMPLE (0x1 << 24) +#define LRADC_CTRL3_DISCARD_2_SAMPLES (0x2 << 24) +#define LRADC_CTRL3_DISCARD_3_SAMPLES (0x3 << 24) +#define LRADC_CTRL3_FORCE_ANALOG_PWUP (1 << 23) +#define LRADC_CTRL3_FORCE_ANALOG_PWDN (1 << 22) +#define LRADC_CTRL3_CYCLE_TIME_MASK (0x3 << 8) +#define LRADC_CTRL3_CYCLE_TIME_OFFSET 8 +#define LRADC_CTRL3_CYCLE_TIME_6MHZ (0x0 << 8) +#define LRADC_CTRL3_CYCLE_TIME_4MHZ (0x1 << 8) +#define LRADC_CTRL3_CYCLE_TIME_3MHZ (0x2 << 8) +#define LRADC_CTRL3_CYCLE_TIME_2MHZ (0x3 << 8) +#define LRADC_CTRL3_HIGH_TIME_MASK (0x3 << 4) +#define LRADC_CTRL3_HIGH_TIME_OFFSET 4 +#define LRADC_CTRL3_HIGH_TIME_42NS (0x0 << 4) +#define LRADC_CTRL3_HIGH_TIME_83NS (0x1 << 4) +#define LRADC_CTRL3_HIGH_TIME_125NS (0x2 << 4) +#define LRADC_CTRL3_HIGH_TIME_250NS (0x3 << 4) +#define LRADC_CTRL3_DELAY_CLOCK (1 << 1) +#define LRADC_CTRL3_INVERT_CLOCK (1 << 0) + +#define LRADC_STATUS_BUTTON1_PRESENT (1 << 28) +#define LRADC_STATUS_BUTTON0_PRESENT (1 << 27) +#define LRADC_STATUS_TEMP1_PRESENT (1 << 26) +#define LRADC_STATUS_TEMP0_PRESENT (1 << 25) +#define LRADC_STATUS_TOUCH_PANEL_PRESENT (1 << 24) +#define LRADC_STATUS_CHANNEL7_PRESENT (1 << 23) +#define LRADC_STATUS_CHANNEL6_PRESENT (1 << 22) +#define LRADC_STATUS_CHANNEL5_PRESENT (1 << 21) +#define LRADC_STATUS_CHANNEL4_PRESENT (1 << 20) +#define LRADC_STATUS_CHANNEL3_PRESENT (1 << 19) +#define LRADC_STATUS_CHANNEL2_PRESENT (1 << 18) +#define LRADC_STATUS_CHANNEL1_PRESENT (1 << 17) +#define LRADC_STATUS_CHANNEL0_PRESENT (1 << 16) +#define LRADC_STATUS_BUTTON1_DETECT_RAW (1 << 2) +#define LRADC_STATUS_BUTTON0_DETECT_RAW (1 << 1) +#define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0) + +#define LRADC_CH_TOGGLE (1 << 31) +#define LRADC_CH7_TESTMODE_TOGGLE (1 << 30) +#define LRADC_CH_ACCUMULATE (1 << 29) +#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24) +#define LRADC_CH_NUM_SAMPLES_OFFSET 24 +#define LRADC_CH_VALUE_MASK 0x3ffff +#define LRADC_CH_VALUE_OFFSET 0 + +#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24) +#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24 +#define LRADC_DELAY_KICK (1 << 20) +#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16) +#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16 +#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11) +#define LRADC_DELAY_LOOP_COUNT_OFFSET 11 +#define LRADC_DELAY_DELAY_MASK 0x7ff +#define LRADC_DELAY_DELAY_OFFSET 0 + +#define LRADC_DEBUG0_READONLY_MASK (0xffff << 16) +#define LRADC_DEBUG0_READONLY_OFFSET 16 +#define LRADC_DEBUG0_STATE_MASK (0xfff << 0) +#define LRADC_DEBUG0_STATE_OFFSET 0 + +#define LRADC_DEBUG1_REQUEST_MASK (0xff << 16) +#define LRADC_DEBUG1_REQUEST_OFFSET 16 +#define LRADC_DEBUG1_TESTMODE_COUNT_MASK (0x1f << 8) +#define LRADC_DEBUG1_TESTMODE_COUNT_OFFSET 8 +#define LRADC_DEBUG1_TESTMODE6 (1 << 2) +#define LRADC_DEBUG1_TESTMODE5 (1 << 1) +#define LRADC_DEBUG1_TESTMODE (1 << 0) + +#define LRADC_CONVERSION_AUTOMATIC (1 << 20) +#define LRADC_CONVERSION_SCALE_FACTOR_MASK (0x3 << 16) +#define LRADC_CONVERSION_SCALE_FACTOR_OFFSET 16 +#define LRADC_CONVERSION_SCALE_FACTOR_NIMH (0x0 << 16) +#define LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH (0x1 << 16) +#define LRADC_CONVERSION_SCALE_FACTOR_LI_ION (0x2 << 16) +#define LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION (0x3 << 16) +#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK 0x3ff +#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET 0 + +#define LRADC_CTRL4_LRADC7SELECT_MASK (0xf << 28) +#define LRADC_CTRL4_LRADC7SELECT_OFFSET 28 +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL0 (0x0 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL1 (0x1 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL2 (0x2 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL3 (0x3 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL4 (0x4 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL5 (0x5 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL6 (0x6 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL7 (0x7 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL8 (0x8 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL9 (0x9 << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL10 (0xa << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL11 (0xb << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL12 (0xc << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL13 (0xd << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL14 (0xe << 28) +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL15 (0xf << 28) +#define LRADC_CTRL4_LRADC6SELECT_MASK (0xf << 24) +#define LRADC_CTRL4_LRADC6SELECT_OFFSET 24 +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL0 (0x0 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL1 (0x1 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL2 (0x2 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL3 (0x3 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL4 (0x4 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL5 (0x5 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL6 (0x6 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL7 (0x7 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL8 (0x8 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL9 (0x9 << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL10 (0xa << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL11 (0xb << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL12 (0xc << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL13 (0xd << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL14 (0xe << 24) +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL15 (0xf << 24) +#define LRADC_CTRL4_LRADC5SELECT_MASK (0xf << 20) +#define LRADC_CTRL4_LRADC5SELECT_OFFSET 20 +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL0 (0x0 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL1 (0x1 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL2 (0x2 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL3 (0x3 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL4 (0x4 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL5 (0x5 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL6 (0x6 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL7 (0x7 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL8 (0x8 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL9 (0x9 << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL10 (0xa << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL11 (0xb << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL12 (0xc << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL13 (0xd << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL14 (0xe << 20) +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL15 (0xf << 20) +#define LRADC_CTRL4_LRADC4SELECT_MASK (0xf << 16) +#define LRADC_CTRL4_LRADC4SELECT_OFFSET 16 +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL0 (0x0 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL1 (0x1 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL2 (0x2 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL3 (0x3 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL4 (0x4 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL5 (0x5 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL6 (0x6 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL7 (0x7 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL8 (0x8 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL9 (0x9 << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL10 (0xa << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL11 (0xb << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL12 (0xc << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL13 (0xd << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL14 (0xe << 16) +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL15 (0xf << 16) +#define LRADC_CTRL4_LRADC3SELECT_MASK (0xf << 12) +#define LRADC_CTRL4_LRADC3SELECT_OFFSET 12 +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL0 (0x0 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL1 (0x1 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL2 (0x2 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL3 (0x3 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL4 (0x4 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL5 (0x5 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL6 (0x6 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL7 (0x7 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL8 (0x8 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL9 (0x9 << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL10 (0xa << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL11 (0xb << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL12 (0xc << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL13 (0xd << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL14 (0xe << 12) +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL15 (0xf << 12) +#define LRADC_CTRL4_LRADC2SELECT_MASK (0xf << 8) +#define LRADC_CTRL4_LRADC2SELECT_OFFSET 8 +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL0 (0x0 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL1 (0x1 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL2 (0x2 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL3 (0x3 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL4 (0x4 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL5 (0x5 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL6 (0x6 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL7 (0x7 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL8 (0x8 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL9 (0x9 << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL10 (0xa << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL11 (0xb << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL12 (0xc << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL13 (0xd << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL14 (0xe << 8) +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL15 (0xf << 8) +#define LRADC_CTRL4_LRADC1SELECT_MASK (0xf << 4) +#define LRADC_CTRL4_LRADC1SELECT_OFFSET 4 +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL0 (0x0 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL1 (0x1 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL2 (0x2 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL3 (0x3 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL4 (0x4 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL5 (0x5 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL6 (0x6 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL7 (0x7 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL8 (0x8 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL9 (0x9 << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL10 (0xa << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL11 (0xb << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL12 (0xc << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL13 (0xd << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL14 (0xe << 4) +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL15 (0xf << 4) +#define LRADC_CTRL4_LRADC0SELECT_MASK 0xf +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL0 (0x0 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL1 (0x1 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL2 (0x2 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL3 (0x3 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL4 (0x4 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL5 (0x5 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL6 (0x6 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL7 (0x7 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL8 (0x8 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL9 (0x9 << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL10 (0xa << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL11 (0xb << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL12 (0xc << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL13 (0xd << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL14 (0xe << 0) +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL15 (0xf << 0) + +#define LRADC_THRESHOLD_ENABLE (1 << 24) +#define LRADC_THRESHOLD_BATTCHRG_DISABLE (1 << 23) +#define LRADC_THRESHOLD_CHANNEL_SEL_MASK (0x7 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_OFFSET 20 +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0 (0x0 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1 (0x1 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2 (0x2 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3 (0x3 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4 (0x4 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5 (0x5 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6 (0x6 << 20) +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7 (0x7 << 20) +#define LRADC_THRESHOLD_SETTING_MASK (0x3 << 18) +#define LRADC_THRESHOLD_SETTING_OFFSET 18 +#define LRADC_THRESHOLD_SETTING_NO_COMPARE (0x0 << 18) +#define LRADC_THRESHOLD_SETTING_DETECT_LOW (0x1 << 18) +#define LRADC_THRESHOLD_SETTING_DETECT_HIGH (0x2 << 18) +#define LRADC_THRESHOLD_SETTING_RESERVED (0x3 << 18) +#define LRADC_THRESHOLD_VALUE_MASK 0x3ffff +#define LRADC_THRESHOLD_VALUE_OFFSET 0 + +#define LRADC_VERSION_MAJOR_MASK (0xff << 24) +#define LRADC_VERSION_MAJOR_OFFSET 24 +#define LRADC_VERSION_MINOR_MASK (0xff << 16) +#define LRADC_VERSION_MINOR_OFFSET 16 +#define LRADC_VERSION_STEP_MASK 0xffff +#define LRADC_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_LRADC_H__ */ diff --git a/include/mach/mxs/regs-power-mx28.h b/include/mach/mxs/regs-power-mx28.h new file mode 100644 index 0000000000..510305a2e2 --- /dev/null +++ b/include/mach/mxs/regs-power-mx28.h @@ -0,0 +1,408 @@ +/* + * Freescale i.MX28 Power Controller Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX28_REGS_POWER_H__ +#define __MX28_REGS_POWER_H__ + +#include <mach/mxs/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mxs_power_regs { + mxs_reg_32(hw_power_ctrl) + mxs_reg_32(hw_power_5vctrl) + mxs_reg_32(hw_power_minpwr) + mxs_reg_32(hw_power_charge) + uint32_t hw_power_vdddctrl; + uint32_t reserved_vddd[3]; + uint32_t hw_power_vddactrl; + uint32_t reserved_vdda[3]; + uint32_t hw_power_vddioctrl; + uint32_t reserved_vddio[3]; + uint32_t hw_power_vddmemctrl; + uint32_t reserved_vddmem[3]; + uint32_t hw_power_dcdc4p2; + uint32_t reserved_dcdc4p2[3]; + uint32_t hw_power_misc; + uint32_t reserved_misc[3]; + uint32_t hw_power_dclimits; + uint32_t reserved_dclimits[3]; + mxs_reg_32(hw_power_loopctrl) + uint32_t hw_power_sts; + uint32_t reserved_sts[3]; + mxs_reg_32(hw_power_speed) + uint32_t hw_power_battmonitor; + uint32_t reserved_battmonitor[3]; + + uint32_t reserved[4]; + + mxs_reg_32(hw_power_reset) +}; +#endif + +#define MX23_POWER_CTRL_CLKGATE (1 << 30) +#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) +#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) +#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) +#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) +#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) +#define POWER_CTRL_PSWITCH_IRQ (1 << 20) +#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) +#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) +#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) +#define POWER_CTRL_POLARITY_DC_OK (1 << 16) +#define POWER_CTRL_DC_OK_IRQ (1 << 15) +#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) +#define POWER_CTRL_BATT_BO_IRQ (1 << 13) +#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) +#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) +#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) +#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) +#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) +#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) +#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) +#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) +#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) +#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) +#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) +#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) +#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) + +#define MX28_POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30) +#define MX28_POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30 +#define MX28_POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30) +#define MX28_POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30) +#define MX28_POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30) +#define MX28_POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30) + +#define MX23_POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 28) +#define MX23_POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 28 +#define MX23_POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 28) +#define MX23_POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 28) +#define MX23_POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 28) +#define MX23_POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 28) + +#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) +#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 +#define MX28_POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20) +#define MX23_POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x1 << 20) +#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 +#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) +#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 +#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 +#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) +#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) +#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) +#define POWER_5VCTRL_DCDC_XFER (1 << 5) +#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) +#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) +#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) +#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) +#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) + +#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) +#define MX23_POWER_MINPWR_VDAC_DUMP_CTRL (1 << 13) +#define POWER_MINPWR_PWD_BO (1 << 12) +#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) +#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) +#define POWER_MINPWR_ENABLE_OSC (1 << 9) +#define POWER_MINPWR_SELECT_OSC (1 << 8) +#define POWER_MINPWR_VBG_OFF (1 << 7) +#define POWER_MINPWR_DOUBLE_FETS (1 << 6) +#define POWER_MINPWR_HALFFETS (1 << 5) +#define POWER_MINPWR_LESSANA_I (1 << 4) +#define POWER_MINPWR_PWD_XTAL24 (1 << 3) +#define POWER_MINPWR_DC_STOPCLK (1 << 2) +#define POWER_MINPWR_EN_DC_PFM (1 << 1) +#define POWER_MINPWR_DC_HALFCLK (1 << 0) + +#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) +#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 +#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) +#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) +#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) +#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) +#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) +#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) +#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) +#define POWER_CHARGE_ENABLE_LOAD (1 << 22) +#define MX23_POWER_CHARGE_ENABLE_CHARGER_RESISTORS (1 << 21) +#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) +#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) +#define MX28_POWER_CHARGE_LIION_4P1 (1 << 18) +#define MX23_POWER_CHARGE_USE_EXTERN_R (1 << 17) +#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) +#define MX28_POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13) +#define MX28_POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12) +#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) +#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 +#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) +#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) +#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) +#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) +#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f +#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 +#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 +#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 +#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 +#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 +#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 +#define POWER_CHARGE_BATTCHRG_I_400MA 0x20 + +#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) +#define POWER_VDDDCTRL_ADJTN_OFFSET 28 +#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) +#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) +#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) +#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) +#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 +#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) +#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDDCTRL_TRG_MASK 0x1f +#define POWER_VDDDCTRL_TRG_OFFSET 0 + +#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) +#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) +#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) +#define POWER_VDDACTRL_DISABLE_FET (1 << 16) +#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 +#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) +#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDACTRL_TRG_MASK 0x1f +#define POWER_VDDACTRL_TRG_OFFSET 0 + +#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) +#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 +#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) +#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) +#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) +#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 +#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) +#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDIOCTRL_TRG_MASK 0x1f +#define POWER_VDDIOCTRL_TRG_OFFSET 0 + +#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) +#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) +#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) +#define MX28_POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5) +#define MX28_POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5 +#define POWER_VDDMEMCTRL_TRG_MASK 0x1f +#define POWER_VDDMEMCTRL_TRG_OFFSET 0 + +#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 +#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) +#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) +#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 +#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) +#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) +#define POWER_DCDC4P2_HYST_DIR (1 << 21) +#define POWER_DCDC4P2_HYST_THRESH (1 << 20) +#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) +#define POWER_DCDC4P2_TRG_OFFSET 16 +#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) +#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) +#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) +#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) +#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) +#define POWER_DCDC4P2_BO_MASK (0x1f << 8) +#define POWER_DCDC4P2_BO_OFFSET 8 +#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f +#define POWER_DCDC4P2_CMPTRIP_OFFSET 0 + +#define POWER_MISC_FREQSEL_MASK (0x7 << 4) +#define POWER_MISC_FREQSEL_OFFSET 4 +#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) +#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) +#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) +#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) +#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) +#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) +#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) +#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) +#define POWER_MISC_DELAY_TIMING (1 << 2) +#define POWER_MISC_TEST (1 << 1) +#define POWER_MISC_SEL_PLLCLK (1 << 0) + +#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) +#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 +#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f +#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 + +#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) +#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) +#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) +#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) +#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) +#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) +#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) +#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 +#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) +#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) +#define POWER_LOOPCTRL_DC_FF_OFFSET 8 +#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) +#define POWER_LOOPCTRL_DC_R_OFFSET 4 +#define POWER_LOOPCTRL_DC_C_MASK 0x3 +#define POWER_LOOPCTRL_DC_C_OFFSET 0 +#define POWER_LOOPCTRL_DC_C_MAX 0x0 +#define POWER_LOOPCTRL_DC_C_2X 0x1 +#define POWER_LOOPCTRL_DC_C_4X 0x2 +#define POWER_LOOPCTRL_DC_C_MIN 0x3 + +#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) +#define POWER_STS_PWRUP_SOURCE_OFFSET 24 +#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) +#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) +#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) +#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) +#define POWER_STS_PSWITCH_MASK (0x3 << 20) +#define POWER_STS_PSWITCH_OFFSET 20 +#define MX28_POWER_STS_THERMAL_WARNING (1 << 19) +#define MX28_POWER_STS_VDDMEM_BO (1 << 18) +#define POWER_STS_AVALID0_STATUS (1 << 17) +#define POWER_STS_BVALID0_STATUS (1 << 16) +#define POWER_STS_VBUSVALID0_STATUS (1 << 15) +#define POWER_STS_SESSEND0_STATUS (1 << 14) +#define POWER_STS_BATT_BO (1 << 13) +#define POWER_STS_VDD5V_FAULT (1 << 12) +#define POWER_STS_CHRGSTS (1 << 11) +#define POWER_STS_DCDC_4P2_BO (1 << 10) +#define POWER_STS_DC_OK (1 << 9) +#define POWER_STS_VDDIO_BO (1 << 8) +#define POWER_STS_VDDA_BO (1 << 7) +#define POWER_STS_VDDD_BO (1 << 6) +#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) +#define POWER_STS_VDD5V_DROOP (1 << 4) +#define POWER_STS_AVALID0 (1 << 3) +#define POWER_STS_BVALID0 (1 << 2) +#define POWER_STS_VBUSVALID0 (1 << 1) +#define POWER_STS_SESSEND0 (1 << 0) + +#define MX23_POWER_SPEED_STATUS_MASK (0xff << 16) +#define MX23_POWER_SPEED_STATUS_OFFSET 16 +#define MX28_POWER_SPEED_STATUS_MASK (0xffff << 8) +#define MX28_POWER_SPEED_STATUS_OFFSET 8 +#define MX28_POWER_SPEED_STATUS_SEL_MASK (0x3 << 6) +#define MX28_POWER_SPEED_STATUS_SEL_OFFSET 6 +#define MX28_POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6) +#define MX28_POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6) +#define MX28_POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6) +#define POWER_SPEED_CTRL_MASK 0x3 +#define POWER_SPEED_CTRL_OFFSET 0 +#define POWER_SPEED_CTRL_SS_OFF 0x0 +#define POWER_SPEED_CTRL_SS_ON 0x1 +#define POWER_SPEED_CTRL_SS_ENABLE 0x3 + +#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) +#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 +#define MX28_POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11) +#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) +#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) +#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) +#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f +#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 + +#define POWER_RESET_UNLOCK_MASK (0xffff << 16) +#define POWER_RESET_UNLOCK_OFFSET 16 +#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) +#define MX28_POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2) +#define POWER_RESET_PWD_OFF (1 << 1) +#define POWER_RESET_PWD (1 << 0) + +#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) +#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) +#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) +#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) + +#define MX28_POWER_THERMAL_TEST (1 << 8) +#define MX28_POWER_THERMAL_PWD (1 << 7) +#define MX28_POWER_THERMAL_LOW_POWER (1 << 6) +#define MX28_POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4) +#define MX28_POWER_THERMAL_OFFSET_ADJ_OFFSET 4 +#define MX28_POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3) +#define MX28_POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7 +#define MX28_POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0 + +#define MX28_POWER_USB1CTRL_AVALID1 (1 << 3) +#define MX28_POWER_USB1CTRL_BVALID1 (1 << 2) +#define MX28_POWER_USB1CTRL_VBUSVALID1 (1 << 1) +#define MX28_POWER_USB1CTRL_SESSEND1 (1 << 0) + +#define POWER_SPECIAL_TEST_MASK 0xffffffff +#define POWER_SPECIAL_TEST_OFFSET 0 + +#define POWER_VERSION_MAJOR_MASK (0xff << 24) +#define POWER_VERSION_MAJOR_OFFSET 24 +#define POWER_VERSION_MINOR_MASK (0xff << 16) +#define POWER_VERSION_MINOR_OFFSET 16 +#define POWER_VERSION_STEP_MASK 0xffff +#define POWER_VERSION_STEP_OFFSET 0 + +#define MX28_POWER_ANACLKCTRL_CLKGATE_0 (1 << 31) +#define MX28_POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28) +#define MX28_POWER_ANACLKCTRL_OUTDIV_OFFSET 28 +#define MX28_POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27) +#define MX28_POWER_ANACLKCTRL_CLKGATE_I (1 << 26) +#define MX28_POWER_ANACLKCTRL_DITHER_OFF (1 << 10) +#define MX28_POWER_ANACLKCTRL_SLOW_DITHER (1 << 9) +#define MX28_POWER_ANACLKCTRL_INVERT_INCLK (1 << 8) +#define MX28_POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4) +#define MX28_POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4 +#define MX28_POWER_ANACLKCTRL_INDIV_MASK 0x7 +#define MX28_POWER_ANACLKCTRL_INDIV_OFFSET 0 + +#define MX28_POWER_REFCTRL_FASTSETTLING (1 << 26) +#define MX28_POWER_REFCTRL_RAISE_REF (1 << 25) +#define MX28_POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24) +#define MX28_POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20) +#define MX28_POWER_REFCTRL_VBG_ADJ_OFFSET 20 +#define MX28_POWER_REFCTRL_LOW_PWR (1 << 19) +#define MX28_POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16) +#define MX28_POWER_REFCTRL_BIAS_CTRL_OFFSET 16 +#define MX28_POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14) +#define MX28_POWER_REFCTRL_ADJ_ANA (1 << 13) +#define MX28_POWER_REFCTRL_ADJ_VAG (1 << 12) +#define MX28_POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8) +#define MX28_POWER_REFCTRL_ANA_REFVAL_OFFSET 8 +#define MX28_POWER_REFCTRL_VAG_VAL_MASK (0xf << 4) +#define MX28_POWER_REFCTRL_VAG_VAL_OFFSET 4 + +#endif /* __MX28_REGS_POWER_H__ */ diff --git a/include/mach/mxs/regs-rtc.h b/include/mach/mxs/regs-rtc.h new file mode 100644 index 0000000000..4d2e218e3b --- /dev/null +++ b/include/mach/mxs/regs-rtc.h @@ -0,0 +1,134 @@ +/* + * Freescale i.MX28 RTC Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX28_REGS_RTC_H__ +#define __MX28_REGS_RTC_H__ + +#include <mach/mxs/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mxs_rtc_regs { + mxs_reg_32(hw_rtc_ctrl) + mxs_reg_32(hw_rtc_stat) + mxs_reg_32(hw_rtc_milliseconds) + mxs_reg_32(hw_rtc_seconds) + mxs_reg_32(hw_rtc_rtc_alarm) + mxs_reg_32(hw_rtc_watchdog) + mxs_reg_32(hw_rtc_persistent0) + mxs_reg_32(hw_rtc_persistent1) + mxs_reg_32(hw_rtc_persistent2) + mxs_reg_32(hw_rtc_persistent3) + mxs_reg_32(hw_rtc_persistent4) + mxs_reg_32(hw_rtc_persistent5) + mxs_reg_32(hw_rtc_debug) + mxs_reg_32(hw_rtc_version) +}; +#endif + +#define RTC_CTRL_SFTRST (1 << 31) +#define RTC_CTRL_CLKGATE (1 << 30) +#define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6) +#define RTC_CTRL_FORCE_UPDATE (1 << 5) +#define RTC_CTRL_WATCHDOGEN (1 << 4) +#define RTC_CTRL_ONEMSEC_IRQ (1 << 3) +#define RTC_CTRL_ALARM_IRQ (1 << 2) +#define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1) +#define RTC_CTRL_ALARM_IRQ_EN (1 << 0) + +#define RTC_STAT_RTC_PRESENT (1 << 31) +#define RTC_STAT_ALARM_PRESENT (1 << 30) +#define RTC_STAT_WATCHDOG_PRESENT (1 << 29) +#define RTC_STAT_XTAL32000_PRESENT (1 << 28) +#define RTC_STAT_XTAL32768_PRESENT (1 << 27) +#define RTC_STAT_STALE_REGS_MASK (0xff << 16) +#define RTC_STAT_STALE_REGS_OFFSET 16 +#define RTC_STAT_NEW_REGS_MASK (0xff << 8) +#define RTC_STAT_NEW_REGS_OFFSET 8 + +#define RTC_MILLISECONDS_COUNT_MASK 0xffffffff +#define RTC_MILLISECONDS_COUNT_OFFSET 0 + +#define RTC_SECONDS_COUNT_MASK 0xffffffff +#define RTC_SECONDS_COUNT_OFFSET 0 + +#define RTC_ALARM_VALUE_MASK 0xffffffff +#define RTC_ALARM_VALUE_OFFSET 0 + +#define RTC_WATCHDOG_COUNT_MASK 0xffffffff +#define RTC_WATCHDOG_COUNT_OFFSET 0 + +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28 +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28) +#define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21) +#define RTC_PERSISTENT0_THERMAL_RESET (1 << 20) +#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18) +#define RTC_PERSISTENT0_AUTO_RESTART (1 << 17) +#define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16) +#define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14) +#define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14 +#define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14) +#define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14) +#define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14) +#define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13) +#define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8) +#define RTC_PERSISTENT0_MSEC_RES_OFFSET 8 +#define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8) +#define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8) +#define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8) +#define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8) +#define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8) +#define RTC_PERSISTENT0_ALARM_WAKE (1 << 7) +#define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6) +#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5) +#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4) +#define RTC_PERSISTENT0_LCK_SECS (1 << 3) +#define RTC_PERSISTENT0_ALARM_EN (1 << 2) +#define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1) +#define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0) + +#define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT1_GENERAL_OFFSET 0 +#define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080 +#define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100 +#define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200 +#define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400 +#define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800 +#define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000 + +#define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT2_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT3_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT4_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT5_GENERAL_OFFSET 0 + +#define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1) +#define RTC_DEBUG_WATCHDOG_RESET (1 << 0) + +#define RTC_VERSION_MAJOR_MASK (0xff << 24) +#define RTC_VERSION_MAJOR_OFFSET 24 +#define RTC_VERSION_MINOR_MASK (0xff << 16) +#define RTC_VERSION_MINOR_OFFSET 16 +#define RTC_VERSION_STEP_MASK 0xffff +#define RTC_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_RTC_H__ */ diff --git a/include/mach/mxs/revision.h b/include/mach/mxs/revision.h new file mode 100644 index 0000000000..65daf3db98 --- /dev/null +++ b/include/mach/mxs/revision.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MACH_REVISION_H__ +#define __MACH_REVISION_H__ + +/* silicon revisions */ +enum silicon_revision { + SILICON_REVISION_1_0 = 0x10, + SILICON_REVISION_1_1 = 0x11, + SILICON_REVISION_1_2 = 0x12, + SILICON_REVISION_1_3 = 0x13, + SILICON_REVISION_1_4 = 0x14, + SILICON_REVISION_2_0 = 0x20, + SILICON_REVISION_2_1 = 0x21, + SILICON_REVISION_2_2 = 0x22, + SILICON_REVISION_2_3 = 0x23, + SILICON_REVISION_3_0 = 0x30, + SILICON_REVISION_3_1 = 0x31, + SILICON_REVISION_3_2 = 0x32, + SILICON_REVISION_UNKNOWN =0xff +}; + +int silicon_revision_get(void); +void silicon_revision_set(const char *soc, int revision); + +#endif /* __MACH_REVISION_H__ */ diff --git a/include/mach/mxs/ssp.h b/include/mach/mxs/ssp.h new file mode 100644 index 0000000000..b90a448205 --- /dev/null +++ b/include/mach/mxs/ssp.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2013 Michael Grzeschik <mgr@pengutronix.de> */ + +/* Freescale MXS SSP */ + +#ifndef __SSP_H__ +#define __SSP_H__ + +#ifdef CONFIG_ARCH_IMX23 +# define HW_SSP_CTRL0 0x000 +# define HW_SSP_CMD0 0x010 +# define HW_SSP_CMD1 0x020 +# define HW_SSP_COMPREF 0x030 +# define HW_SSP_COMPMASK 0x040 +# define HW_SSP_TIMING 0x050 +# define HW_SSP_CTRL1 0x060 +# define HW_SSP_DATA 0x070 +# define HW_SSP_SDRESP0 0x080 +# define HW_SSP_SDRESP1 0x090 +# define HW_SSP_SDRESP2 0x0A0 +# define HW_SSP_SDRESP3 0x0B0 +# define HW_SSP_STATUS 0x0C0 +# define HW_SSP_DEBUG 0x100 +# define HW_SSP_VERSION 0x110 +#endif + +#ifdef CONFIG_ARCH_IMX28 +# define HW_SSP_CTRL0 0x000 +# define HW_SSP_CMD0 0x010 +# define HW_SSP_CMD1 0x020 +# define HW_SSP_XFER_COUNT 0x030 +# define HW_SSP_BLOCK_SIZE 0x040 +# define HW_SSP_COMPREF 0x050 +# define HW_SSP_COMPMASK 0x060 +# define HW_SSP_TIMING 0x070 +# define HW_SSP_CTRL1 0x080 +# define HW_SSP_DATA 0x090 +# define HW_SSP_SDRESP0 0x0A0 +# define HW_SSP_SDRESP1 0x0B0 +# define HW_SSP_SDRESP2 0x0C0 +# define HW_SSP_SDRESP3 0x0D0 +# define HW_SSP_DDR_CTRL 0x0E0 +# define HW_SSP_DLL_CTRL 0x0F0 +# define HW_SSP_STATUS 0x100 +# define HW_SSP_DLL_STS 0x110 +# define HW_SSP_DEBUG 0x120 +# define HW_SSP_VERSION 0x130 +#endif + +#define SSP_CTRL0_SFTRST (1 << 31) +#define SSP_CTRL0_CLKGATE (1 << 30) +#define SSP_CTRL0_RUN (1 << 29) +#define SSP_CTRL0_LOCK_CS (1 << 27) +#define SSP_CTRL0_READ (1 << 25) +#define SSP_CTRL0_IGNORE_CRC (1 << 26) +#define SSP_CTRL0_DATA_XFER (1 << 24) +#define SSP_CTRL0_BUS_WIDTH(x) (((x) & 0x3) << 22) +#define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) +#define SSP_CTRL0_WAIT_FOR_CMD (1 << 20) +#define SSP_CTRL0_SSP_ASSERT_OUT(x) (((x) & 0x3) << 20) +#define SSP_CTRL0_LONG_RESP (1 << 19) +#define SSP_CTRL0_GET_RESP (1 << 17) +#define SSP_CTRL0_ENABLE (1 << 16) + +#define SSP_CMD0_SLOW_CLK (1 << 22) +#define SSP_CMD0_CONT_CLK (1 << 21) +#define SSP_CMD0_APPEND_8CYC (1 << 20) +#ifdef CONFIG_ARCH_IMX23 +# define SSP_CTRL0_XFER_COUNT(x) ((x) & 0xffff) +# define SSP_CMD0_BLOCK_SIZE(x) (((x) & 0xf) << 16) +# define SSP_CMD0_BLOCK_COUNT(x) (((x) & 0xff) << 8) +#endif +#define SSP_CMD0_CMD(x) ((x) & 0xff) + +#ifdef CONFIG_ARCH_IMX28 +# define SSP_BLOCK_SIZE(x) ((x) & 0xf) +# define SSP_BLOCK_COUNT(x) (((x) & 0xffffff) << 4) +#endif + +/* bit definition for register HW_SSP_TIMING */ +#define SSP_TIMING_TIMEOUT_MASK (0xffff0000) +#define SSP_TIMING_TIMEOUT(x) ((x) << 16) +#define SSP_TIMING_CLOCK_DIVIDE(x) (((x) & 0xff) << 8) +#define SSP_TIMING_CLOCK_RATE(x) ((x) & 0xff) + +/* bit definition for register HW_SSP_CTRL1 */ +#define SSP_CTRL1_POLARITY (1 << 9) +#define SSP_CTRL1_PHASE (1 << 10) +#define SSP_CTRL1_DMA_ENABLE (1 << 13) +#define SSP_CTRL1_WORD_LENGTH(x) (((x) & 0xf) << 4) +#define SSP_CTRL1_SSP_MODE(x) ((x) & 0xf) + +/* bit definition for register HW_SSP_STATUS */ +# define SSP_STATUS_PRESENT (1 << 31) +# define SSP_STATUS_SD_PRESENT (1 << 29) +# define SSP_STATUS_CARD_DETECT (1 << 28) +# define SSP_STATUS_RESP_CRC_ERR (1 << 16) +# define SSP_STATUS_RESP_ERR (1 << 15) +# define SSP_STATUS_RESP_TIMEOUT (1 << 14) +# define SSP_STATUS_DATA_CRC_ERR (1 << 13) +# define SSP_STATUS_TIMEOUT (1 << 12) +# define SSP_STATUS_FIFO_OVRFLW (1 << 9) +# define SSP_STATUS_FIFO_FULL (1 << 8) +# define SSP_STATUS_FIFO_EMPTY (1 << 5) +# define SSP_STATUS_FIFO_UNDRFLW (1 << 4) +# define SSP_STATUS_CMD_BUSY (1 << 3) +# define SSP_STATUS_DATA_BUSY (1 << 2) +# define SSP_STATUS_BUSY (1 << 0) +# define SSP_STATUS_ERROR (SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW | \ + SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR | \ + SSP_STATUS_RESP_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | SSP_STATUS_TIMEOUT) + +#endif /* __SSP_H__ */ diff --git a/include/mach/mxs/usb.h b/include/mach/mxs/usb.h new file mode 100644 index 0000000000..132fc16eec --- /dev/null +++ b/include/mach/mxs/usb.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MACH_USB_H +#define __MACH_USB_H + +int imx23_usb_phy_enable(void); + +int imx28_usb_phy0_enable(void); +int imx28_usb_phy1_enable(void); + +#endif /* __MACH_USB_H */ |