| Commit message (Collapse) | Author | Age | Files | Lines |
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Add support for 8bit HW ECC modes supported by later IP versions.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add support for 4bit HW ECC modes supported by later IP versions.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Marvell PXA3xx NAND flash controller IP has been reused in later SoCs
with additional HW features. Add HW BCH ECC as the first known HW
difference.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Newer versions of Marvell PXA3xx NFC also support BCH and therefore
higher ECC strengths than 1. Prepare for different ECC strength by
factoring out ECC init into separate functions by strength. Also,
add a new host variable that indicates BCH ECC.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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With DT helpers for ECC step size and strength, now use them on
Marvell NAND driver.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The "num-cs" property does not encode flashes CS line but number
of available CS signals. Fix wrong property parsing to ->cs by
adding proper ->num_cs variable to host struct.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Parsing DT nodes if CONFIG_OFTREE isn't enabled is pointless, also
we should prefer potential platform_data passed earlier.
Protect mrvl_nand_probe_dt by bailing out early if either
CONFIG_OFTREE is not enabled or dev's platform_data is non-NULL.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Marvell NAND controller allows to enable an Auto Read Status feature
that will automatically monitor NAND status during Erase and Program
operations. Ready bit in status register will be set after the
controller is sure the NAND device has finished the operation and
saves us from guessing the real timeout values.
Using the Auto Read Status feature prevents timeout issues on the
two operations with none or wrong timing register setup.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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If OOB data is not required on page program, we have to clear
the corresponding data with 0xff instead of 0x00.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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With a common clock provided for NAND controller, get rid of the
mach/clock.h way of getting the NAND clock.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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With PXA3xx now providing a common clock for the NAND clock, use it
and get rid of the mach/clock.h. This will allow Marvell Armada 370/XP
to reuse the same driver.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add a clock with clk_add_physbase for the NAND flash controller on
Zylonite board.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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To allow PXA3xx nand driver to be reused on Marvell Armada 370/XP,
prepare to provide a common clock for the NAND driver on PXA3xx.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Kconfig prompt for Marvell Orion SoCs is missing a "Marvell"
prefix, add it to the prompt.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This imports DT helpers for MTD ECC step size and strength from
Linux kernel.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The Synopsys DesignWare core supports 52 MHz MMC mode and 50 MHz SD
mode, so add the cap flags so they are used.
This works on socfpga. The other user of this driver is Rockchip and
the datasheet I found for the RK30xx indicated it supported highspeed
modes as well.
The Linux kernel has DT properties, e.g. "cap-mmc-highspeed", but none
of the drivers in barebox support this at all. They all specify flags
in their code.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Nothing used it.
Also delete the local mci alias pointer to host->mci in
dw_mmc_probe(). It only saved a few characters and all the references
but one are using host->mci.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Since there is no OF support in the xloader on socfpga it uses the
platform_data system. There needs to be a way to supply the
equivalent of the DT property bus-width this way to support devices
that need to use a smaller bus.
So that we don't need to put every flag that might get added to the
MMC_CAP list into platform_data, just put the bus width ones into
platform_data.
The socfpga dts sources specify a bus-width of 4 so use that in the
platform_data for socfpga.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The OF code for parsing bus-width would only add the specified width
to those the driver might have already set capability flags for.
Because of this, if the driver had set 8 or 4 bit width, it wasn't
possible for the DT to specify that fewer pins were used on the board
and a smaller width was necessary.
Change this so the width in the DT overrides whatever widths the
driver says it supports. There is no reason to have an incorrect
device tree and it makes far more sense for the DT to override the
driver default than for the driver default to override the DT.
The widths the driver puts in host_caps before calling mci_of_parse()
are considered the default if the DT doesn't specify bus-width. This
should cause the least amount of change to existing boards, as despite
a comment that no bus-width meant to use 1 bit, using the driver
default is what was really happening.
Unfortunately, half of existing drivers default to the largest width
they support while the other half default to the smallest. Boards
should just stick the width in the device tree.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Matching against driver's name before looking throught its id_table
can lead to a somewhat strange and unintuitive behaviour where a
device whose driver's name matches one of the lines in id_table (which
is not unheard of in Linux kernel) will be probed against said driver
with 'id_table' field set to NULL which in turn will result in
dev_get_drvdata erroring out with -ENODEV.
This patch changes the behaviour such that device_match() only tries
to match against driver's name only if id_table of that driver is not
present.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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unprotect(), erase() and protect() return EOPNOTSUPP errno code
for at24 I2C eeproms, so envfs_save() doesn't store data
to these eeproms without this patch.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Use an 'initramfs' file if it exists instead of nfsroot. This offers the
possibility to quickly boot complete filesystems as initramfs without
the need to flash an SD-card or similar. If the initramfs does not
exist, it uses the default nfsroot mechanism.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Wjatscheslaw Stoljarski <wjatscheslaw.stoljarski@kiwigrid.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Wrong type let state probe fail with ENOENT.
Signed-off-by: Jan Remmet <j.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Using a multi uimage stored in nand didn't work. Only one open for the
bb file is allowed. The file type detection after bootm_open_os_uimage
will fail. bootm_open_initrd_uimage and bootm_open_oftree_uimage already
check if they can reuse data->os.
Signed-off-by: Jan Remmet <j.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Separate oftree file and uimage oftree handling.
Make fie_type checks in bootm_boot
Signed-off-by: Jan Remmet <j.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sergey Koshechkin <serge.koshechkin@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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'crc32_no_comp', 'file_crc'
Signed-off-by: Sergey Koshechkin <serge.koshechkin@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Once ls is called with a non-existing directory it should exit with a
non-zero status. Fix that.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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maybe it is easier to press ctrl-l to clear the screen than type
'clear' command.
Signed-off-by: Du Huanpeng <u74147@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sergey Koshechkin <serge.koshechkin@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sergey Koshechkin <serge.koshechkin@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Use IOMEM() macro in all dev_request_mem_region_* routines to allow
the proper mapping on all platforms.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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10x performance gain according to simple test on QEMU malta:
barebox:/ time memcpy 0xa0000000 0xa0001000 0x100000
Signed-off-by: Aleksey Kuleshov <rndfax@yandex.ru>
Acked-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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TP-Link MR3020 has 4 MiB flash boot ROM.
Usually boot ROM is mapped to 0xbfc00000.
However, as AR9331 allows to remap boot ROM to 0xbf000000
it's better to assume that boot ROM starts at 0xbf000000.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Black Swift has 16 MiB flash boot ROM. The standard board's
bootloader (U-Boot_mod) remaps boot ROM to 0xbf000000.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Tested-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Barebox' PBL is able to initialize SoC's memory controller,
but it can be used only if PBL runs from ROM or on-chip SRAM.
MIPS architecture standard boot vector is 0xbfc00000
so on most MIPS SoCs all addresses higher than 0xbfc00000
belong to boot ROM or on-chip SRAM. Thus there's a
simple criterion to check if PBL runs from ROM: just
check if current PC is higher than 0xbfc00000.
Some MIPS boards have ROM start address lower than 0xbfc00000
so it's reasonable to make ROM start address checking board-dependant.
The pbl_blt macro checks if current pc is lower than
the first argument (ROM start address). If so then
next instruction executed is defined by the second argument
of the macro.
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Tested-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This commit makes it possible to handle exception on
incorrect data access so 'md' command just show 'xxxxxxxx'
instead of crashing the system.
barebox:/ md -l 0xa0000003+4
a0000003: xxxxxxxx ....
Without this commit we will get this
barebox:/ md -l 0xa0000003+4
a0000003:
Ooops, address error on load or ifetch!
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### ERROR ### Please RESET the board ###
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This commit clears ERL (ERror Level) flag on start.
If this flag is set then we get 'TLB miss on load or ifetch'
just after return from exception.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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In order for cdev_by_device_node() to be able to return approprate
character device for <&ocotp> phandle cdev->device_node needs to be
initialized with dev->device_node. This patche takes care of that
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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enable chipidea usb driver
Signed-off-by: Florian Vallee <fvallee@eukrea.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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OTG and HOST port are tested with a mass storage device.
Signed-off-by: Florian Vallee <fvallee@eukrea.fr>
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Florian Vallee <fvallee@eukrea.fr>
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Instead of writing one word to the txfifo and then wait until
one is received in the rxfifo we can write while the txfifos
are not full and read as long the rxfifos contain data. This
makes transfers for the m25p80 driver around 7 times faster
here.
Unlike the last version this time we only optimize the common
case with 8 bits per word and SPI_LSB_FIRST cleared. The other
cases would require more bit shuffling of the data.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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