| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
| |
Support for the SoC is still in progress, but lets document
what we have now.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Both STM32MP BootROM and TF-A first stage expect subsequent bootloader
stages to feature a specific STM32 file header. Generate this image
type by default.
If for some reason, the image without stm32 header is required, the
start_stm32mp157c_dk2.pblb can be used.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Both STM32MP BootROM and TF-A first stage expect subsequent bootloader
stages to feature a specific 256-byte long STM32 file header.
Add detection of the header to file_detect_type().
While there's only one version of the header so far, identify the new
header as v1 anyway, so new versions can be unambiguously added.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
|
| |
Both STM32MP BootROM and TF-A first stage expect subsequent bootloader
stages to feature a specific STM32 file header. Add a stm32image
utility to address this.
Signed-off-by: Marco Felsch <marco.felsch@gmail.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
| |
The arch was renamed to stm32mp, so it doesn't look out of place when
the stm32mp2 is released. Fix spotted comments/labels with the old
name. While at it, fix a typo about the SoC name on the DK2 board.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
| |
On the STM32MP, reset of the I2C, SPI and USB IPs occurs over the RCC.
This driver adds support for the controller, so it may be reused by
other drivers.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
| |
The pinctrl-stm32 driver uses the alias id to infer the index of the
first GPIO supported by a controller. Because gpioz' identifiers
start at ('Z' - 'A') * 0x10, change the id to 25.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
| |
The STM32MP1 GPIO bindings uses the range [400; 415] for the gpioz
controller, which exceeds the barebox-wide ARCH_NR_GPIOS of 256.
Therefore have the stm32mp define a subarch-specific max of 416.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Some architectures have non-contiguous GPIO ranges where some GPIOs can
have identifiers exceeding the hardcoded ARCH_NR_GPIOs of 256.
One such example is the STM32MP, whose gpioz controller has identifiers
that go up to ('Z' - 'A' + 1) * 0x10 - 1 = 415.
Instead of increasing the array size for all architectures or doing
some sort of packing, allow architecture to define their own overriding
CONFIG_ARCH_NR_GPIO like the kernel does.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ |
|
| |
| |
| |
| |
| |
| |
| | |
Add support for Remote Modem Unit i.MX7D board.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| | |
Now that it is availible, switch to using kernel DTS.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| | |
To prepare for addition of another ZII i.MX7D based board, i.MX7D
RMU2, rename zii-imx7d-rpu2 to zii-imx7d-dev to avoid any image naming
confusion.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Fix a buggy while loop expression, that, due to '==' operator's
precedence (higher than that of '&') was always evaluating to false
rendering busy loop into a no-op.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Reconcile DDR setup code with corresponding DCD line by line, to avoid
having any doubts if the two are identical (there wer some minor
differences).
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
As observed on CFU1 board, without this delay we interrupt mask ROM
code execution even before it sets up any PLLs correctly preventing
Barebox from correctly starting up. Fixing this by adding PLL setup
code to OpenOCD script helps somewhat and Barebox starts, howerver CPU
started this way ends up being unstable crashing randomly during
further Barebox use.
Adding a simple 100 ms post reset delay resolves all of the described
issues. This is also consistent with how other ZII boards are set up.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| | |
Add missing #address-cells and #size-cells to fix a warning
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| | |
Add missing #address-cells and #size-cells to fix a warning
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| | |
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| | |
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ \ |
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The reset reason part of the code is based on the i.MX6's and duplicated
a comment from there, which isn't applicable to the STM32. Delete it.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Current error path has two issues:
- PTR_ERR is applied to a NULL pointer, so even error conditions return
zero, which is a valid successful return.
- The return value is stored into an unsigned integer which is checked
to be less than zero, so the error is never handled.
Fix both issues.
Fixes: f4f933a64 ("pinctrl: add driver for STM32 GPIO and pin multiplexer")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
There's already a debug output whenever a pin is configured, extend this
by printing a "header" with the node name and how many pins configurations
will follow.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Incoming PSCI implementation for the STM32MP1 needs
to get_gicd_base_address as well, so move it to gic.h to
avoid code duplication.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Both psci_system_reset and psci_system_off call psci_ops->system_reset,
which seems like a copy-paste error as there is an unused ->system_off
as well.
Adjust psci_system_off to use ->system_off instead. This won't matter
for the existing i.MX7 PSCI implementation because it defines neither
callback, but it will for the upcoming STM32MP PSCI support.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Now with pinctrl/GPIO support, enable some useful GPIO-related
drivers and commands.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Now that we have GPIO support, add the red LED to the barebox
device tree and override the blue one's default state.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This adds driver support for the 12 GPIO banks on the STM32MP157.
As they are accessible to both the Cortex-A cores as well as the Cortex-M
core, modifications to these are protected by a hardware spinlock
and clocks are enabled/disabled as required.
All register fiddling done by the driver is collected in <soc/stm32/gpio.h>,
so future PBL code may make use of it as well to chainload barebox proper.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Some STM32MP Linux drivers, which could be ported to barebox as part of
improved second stage barebox support, are using hardware spinlocks to
coordinate access between the three processors. While barebox only
uses one of the two Cortex-A cores, spin locks may still be necessary
because of firmware loaded unto the Cortex-M.
To ease porting these drivers, without having to import the hw spinlock
driver now, add stubs for the functions.
The stubs will we be reused when CONFIG_HWSPINLOCK is introduced,
but is disabled in config. The API is oriented after the implementation
in U-Boot.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Pinctrl nodes adhering to the generic pinctrl bindings may contain
properties like input-low/input-high, which require pinctrl_ops.set_state
to have a handle on the relevant gpio chip.
Currently this would lead to code duplication: Both the pinctrl driver
and gpiolib will need to store a list of registered gpiochips.
Avoid this by providing a helper to query the registered gpio_chip
given a gpio's number.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The DK2 appears to be just the DK1 with a display, thus factor out the
barebox-specifics into a new stm32mp157a-dk1.dtsi, which we can include
in both device trees after including the upstream device tree.
As the updated device tree introduced new nodes, the now duplicates
(ðernet0, &uart4, /chosen and /aliases) are dropped from the barebox
device as part of this commit as well.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
To allow "stm32mp157c.dtsi" to extend nodes in <arm/stm32mp157c.dtsi>,
it should be included after it. Do this.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
With the IWDG driver implemented in barebox, have it be part of the
default configuration.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The driver supports setting watchdog timeout, system reset
and querying reset reason. Disabling watchdog isn't possible
in hardware, thus users should either only enable it before
boot or have the poller take care of feeding it.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Now that enum reset_src_type has been extended by BROWNOUT as a reason,
add it to the user documentation.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Other images/Makefile.${arch}s, e.g. images/Makefile.imx, populate
pblp-* with the entry points to build, not the pbl file that's
generated. Adjust the images/Makefile.stm32mp to do the same.
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This saves 23K with my configuration (from 250K to 227K).
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The STM32MP1 can report brown out as reason for a reset,
which doesn't fit into existing reasons. Thus add a new
one to the enumeration.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Serial and clk driver both depend on CONFIG_ARCH_STM32MP1,
so either the Kconfig symbol or their depend needs to change.
Patches posted by the vendor to Linux, U-Boot and their BSP
Yocto-Layer speak of a STM32MP-Family of which the STM32MP1
is the first series, thus rename the arch by dropping the 1.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ \ \ |
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Instead of jumping through hoops using the bsp-editor gui, just use the
underlying python script for importing.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | | |
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
iocsr_scan_chain3_table
Since commit a83c97f2a4065ef7209f123b837fa5103f984c6a SECT() macro is used to
reduces image size.
This patch add a missing SECT for iocsr_scan_chain3_table.
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
xload on de0nanosoc stop to boot after:
SDRAM setup...
SDRAM calibration...
This patch fix SDRAM configuration and updates handoff to quartus2 18.1
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ \ \ \ |
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
The patch fixes the following gcc-8.3.0 warning:
arch/sandbox/board/devices.c:13:5: warning: no previous prototype for ‘sandbox_add_device’ [-Wmissing-prototypes]
int sandbox_add_device(struct device_d *dev)
^~~~~~~~~~~~~~~~~~
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Tap network interface initialization in sandbox
barebox leads to segfault under Debian Buster/Sid.
The problem is that strcpy(dev, ifr.ifr_name) inside
tap_alloc() tries to alter read-only data passed
by tap_probe() and barebox receives SIGSEGV.
Nobody uses network interface name returned
by tap_alloc() so we can drop this strcpy().
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ \ \ \ \ |
|