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* firmware-zynqmp: port from linuxThomas Haemmerle2019-02-271-0/+1
| | | | | | | Port Xilinx Zynq MPSoC Firmware layer driver from linux. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: zynqmp: select macb driverThomas Haemmerle2019-01-301-0/+1
| | | | | | | macb supports Xilinx ZynqMP GEM, so select HAS_MACB by default. Signed-off-by: Thomas Haemmerle <thomas.haemmerle1988@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: zynqmp: add support for Xilinx ZCU104 boardMichael Tretter2018-12-101-0/+14
| | | | | | | | | | | | | | Add support for the Xilinx Zynq Ultrascale+ MPSoC architecture (ZynqMP) and the Xilinx ZCU104 board. Barebox is booted as BL33 in EL-1 and expects that a BL2 (i.e. the FSBL) already took care of initializing the RAM. Also for debug_ll, the UART is expected to be already setup correctly. Thus, you have to add the Barebox binary to a boot image as described in "Chapter 11: Boot and Configuration" of "Zynq Ultrascale+ Device Technical Reference Manual". Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* kconfig: include common Kconfig files from top-level KconfigAntony Pavlov2018-12-031-9/+0
| | | | | | | | | | | | | Based on this linux kernel commit: > commit 1572497cb0e6d2016078bc9d5a95786bb878389f > Author: Christoph Hellwig <hch@lst.de> > Date: Tue Jul 31 13:39:30 2018 +0200 > > kconfig: include common Kconfig files from top-level Kconfig Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2018-08-131-4/+0
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| * ARM: socfpga: Arria10: support programming FPGA in PBLSteffen Trumtrar2018-08-081-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Arria10 boards don't have the FPGA programmed externally. Instead barebox needs to do that. As the Arria10 has the SDRAM controller in the FPGA, the first thing we need to do is, configure the FPGA before the SDRAM can even be used. It works like this: 1. boot ROM fetches the PBL from MMC 2. read the MBR from MMC (this depends on the setup done by the boot ROM) 3. read the Bitstream from the MMC and program the FPGA 4. re-read the barebox image from MMC, this time with the full barebox that is appended to the PBL 5. jump into the full barebox Only supported boot device is eMMC. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Add code to support SMCCC on AArch64Andrey Smirnov2018-08-081-0/+4
|/ | | | | | | | | | | | | | Port SMCCC code from Linux kernel. To accomodate that: - Introduce CONFIG_ARM_SMCCC, to allow enabling the code independent of CONFIG_ARM_SECURE_MONITOR - Bring <linux/arm-smccc.h> in - Add necessary constants to arch/arm/asm-offsets.c Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2018-06-111-1/+1
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| * scripts: create a separate section for host toolsUwe Kleine-König2018-06-111-1/+0
| | | | | | | | | | | | | | | | | | | | This allows to enable host tools even if they are not needed for the current configuration to improve compile coverage and simplify packaging these tools. The conversion doesn't cover all tools available but can be extended later. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * Add builtin firmware supportSascha Hauer2018-06-081-0/+1
| | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [andrew.smirnov@gmail.com: Add dummy.o in case directory is empty] Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: lib64: Make string functions aware of MMU configurationAndrey Smirnov2018-06-111-0/+7
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimized version of memset() in memset.S if called as: memset(foo, 0, size) will try to explicitly zero out data cache with: dc zva, dst which will result in Alignement Exception (DABT) if MMU is not enabled. For more info see: - C4.4.8 "DC ZVA, Data Cache Zero by VA" - D5.2.8 "The effects of disabling a stage of address translation" in "ARM Architecture Reference Manual. ARMv8, for ARMv8-A architecture profile" In similar vein, using optimized version of memcpy() could lead to a unaligned 16-byte write (using 'stp'), which is not allowed for Device-nGnRnE type of memory (see D5.2.8) and would liead to Alignement Exception. To fix both problems expose non-optimized and optimzied versions of the function and created a wrapper to dispatch the call to either one based on if MMU is enabled or not. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: aarch64: hide some config optionsSascha Hauer2018-03-291-1/+2
| | | | | | | EABI and ATAGS have no meaning on aarch64, so hide the options from the user. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: For relocatable image force TEXT_BASE 0x0Sascha Hauer2018-03-211-1/+5
| | | | | | | Nothing else should be used for the relocatable image case, so force TEXT_BASE to 0x0 and do not show it in the menu. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: add arria10 supportSteffen Trumtrar2017-05-031-3/+3
| | | | | | | | | | | | | | | | | | Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that is already supported in barebox. Both a the same in some parts, but totaly different in others. Most of the hardware blocks are the same in the SoC parts. The OCRAM is larger on the Arria10 and the SDRAM controller is different. The serial core only supports 32bit accesses (different to the 8bit accesses on the Cyclone5). As Arria10 has 256KB of OCRAM, it is possible to fit a larger barebox (and/or use PBL) instead of the two stage bootprocess used on the Cyclone5 and its 64KB OCRAM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2017-04-071-3/+0
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| * ARM: mvebu: remove obsolete selectUlrich Ölmann2017-03-301-1/+0
| | | | | | | | | | | | | | | | This is a user choice now and has been removed for all other boards in commit 790980bf18af ("Make generic default environment type a use choice"). Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * poweroff: Allow to register poweroff handlersSascha Hauer2017-03-301-2/+0
| | | | | | | | | | | | | | | | | | | | Allow to register handlers for poweroff. This allows to have multiple poweroff implementations in a single binary. The implementation is close to the restart handlers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | at91sam9x5ek: Convert to mult-image buildAndrey Smirnov2017-03-301-1/+0
| | | | | | | | | | | | | | | | Convert AT91SAM9X5-EK board code to multi-image build process, similar to how majority of i.MX board code is built. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: at91: Port at91 DT clock codeAndrey Smirnov2017-03-301-0/+1
|/ | | | | | | | Port at91 DT clock code from Linux 4.9-rc3. Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/rpi'Sascha Hauer2017-03-131-17/+12
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| * ARM: rpi: switch to DT probe and multi-image buildLucas Stach2017-03-021-18/+12
| | | | | | | | | | | | | | | | This commit switches the RaspberryPi arch over to probe Barebox from the builtin DT and enables multi-image builds. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: rpi: always build relocatable imageLucas Stach2017-03-021-0/+1
| | | | | | | | | | | | | | | | Makes more space available for the malloc area and will allow to switch to multi-image later on. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/mvebu'Sascha Hauer2017-03-131-0/+1
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| * | mvebu: get initial position of register window from image headerUwe Kleine-König2017-03-021-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | A problem when using 2nd stage booting on mvebu is that the first bootloader already switched the register window location from 0xd0000000 to 0xf1000000 by writing to 0xd0000080. When the second bootloader also tries to do this switch it writes to the wrong location resulting in an exception and so a boot failure. For this reason the base address of the register window is passed in the barebox header and picked up from there by early code. In a further patch bootm is taught to put the actual position of the window there for the second bootloader to finally make second stage booting work. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
* / scripts: imx/mxs remove mxs-usb-loaderOleksij Rempel2017-03-091-0/+1
|/ | | | | | | ... and use imx-usb-loader instead Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Add PSCI supportSascha Hauer2017-02-131-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains the barebox implementation for the ARM "Power State Coordination Interface" (PSCI). The interface is aimed at the generalization of code in the following power management scenarios: * Core idle management. * Dynamic addition and removal of cores, and secondary core boot. * big.LITTLE migration. * System shutdown and reset. In practice, all that's currently implemented is a way to enable the secondary core one some SoCs. With PSCI the Kernel is either started in nonsecure or in Hypervisor mode and PSCI is used to apply power to the secondary cores. The start mode is passed in the global.bootm.secure_state variable. This enum can contain "secure" (Kernel is started in secure mode, means no PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available) or "hyp" (Kernel is started in hyp mode, meaning it can support virtualization). We currently only support putting the secure monitor code into SDRAM, which means we always steal some amount of memory from the Kernel. To keep things simple for now we simply keep the whole barebox binary in memory The PSCI support has been tested on i.MX7 only so far. The only supported operations are CPU_ON and CPU_OFF. The PSCI and secure monitor code is based on the corresponding U-Boot code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm64: disable PBL supportLucas Stach2017-01-091-1/+0
| | | | | | | PBL is another feature, which needs some love to work on ARM64. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mvebu'Sascha Hauer2016-10-101-0/+1
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| * ARM: mvebu: select HAVE_DEFAULT_ENVIRONMENT_NEWUwe Kleine-König2016-09-161-0/+1
| | | | | | | | | | | | | | | | None of the available boards for mvebu has any environment additions, so this is safe. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/defenv'Sascha Hauer2016-10-101-1/+0
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| * | Make generic default environment type a use choiceSascha Hauer2016-10-101-1/+0
| |/ | | | | | | | | | | | | | | So far it was hardcoded for each board if defenv-1 or defenv-2 is used. Make this a user choice so that a particular board no longer enforces a defenv type. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | arm: semihosting support is not implemented for ARM64Lucas Stach2016-10-041-0/+1
| | | | | | | | | | | | | | Don't allow it to be selected in a ARM64 build. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | arm(64): move HAS_DMA and HAS_MODULES to CPU_32Lucas Stach2016-10-041-2/+0
|/ | | | | | | | We don't yet have an implementation for those two features on ARM64, so move them to a place where they are only selected for a 32bit barebox. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2016-07-111-0/+10
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| * ARM: boot: add prepend option for board specific ATAGsAlexander Kurz2016-06-291-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Board specific ATAGs might be passed to vendor provided kernels via the ARM_BOARD_APPEND_ATAG option. In this case, the board specific ATAGs will be appended to the end of the ATAG list. Anyway, some vendor provided kernels might crop the ATAG list at ATAG_MEM, also chopping off the board specific ATAGs, see linux squash_mem_tags() as reference. The Kindle-3 kernel is one example. This conflict might be solved by a) making ATAG_MEM optional which might break the existing behavour around squash_mem_tags() or b) by allowing the insertion of board specific ATAGs in front of ATAG_MEM which violates the requirement from Documentation/arm/Booting to order ATAGs by increasing address. Add option to insert board specific ATAGs in front of ATAG_MEM. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | arm: boards: add mach-qemu and virt64 boardRaphael Poggi2016-07-061-0/+5
| | | | | | | | | | | | | | Introduce mach-qemu and add qemu virt64 board which emulates arm64 board. Signed-off-by: Raphael Poggi <poggi.raph@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | arm64: add armv8 Kconfig entriesRaphael Poggi2016-07-061-0/+23
|/ | | | | Signed-off-by: Raphael Poggi <poggi.raph@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: PXA: move HAVE_CLK selectLucas Stach2016-01-191-1/+0
| | | | | | | | | | | | Claiming that all of PXA has CLK implemented, while only PXA3XX selects the relevant clock implementations causes lots of build failures for the other PXA architectures. Fix it by moving the HAVE_CLK select to the one PXA arch, that actually has it. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: bcm283x: add rpi2 supportAlexander Aring2016-01-071-0/+5
| | | | | | | | This patch adds Raspberry Pi 2 support in barebox. The features should be the same like the current RPi status in barebox. Signed-off-by: Alexander Aring <alex.aring@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* bcm2835: introduce mach-bcm283xAlexander Aring2016-01-041-7/+11
| | | | | | | | | | | | This patch changes the most part of mach-bcm2835 to mach-bcm283x. This prepares to add RPi2 support which is a bcm2836. This patch changes the Kconfig entry namens to BCM283X for drivers only. These drivers should working the same in bcm2836. While updating defconfig I added LED support/trigger option. Signed-off-by: Alexander Aring <alex.aring@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mtd'Sascha Hauer2015-12-081-0/+1
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| * arm: pxa: Prepare for NAND clkdev lookup on PXA3xxSebastian Hesselbarth2015-11-231-0/+1
| | | | | | | | | | | | | | | | | | | | To allow PXA3xx nand driver to be reused on Marvell Armada 370/XP, prepare to provide a common clock for the NAND driver on PXA3xx. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: don't let the unwinder depend on exception handlingUwe Kleine-König2015-11-091-1/+0
|/ | | | | | | | | | To be able to use dump_stack() without support exception handling the definition of dump_stack has to move to a file that is actually compiled without ARM_EXCEPTIONS. Fixes: d332597c7c16 ("ARM: make exception handling optional") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2015-11-061-0/+5
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| * ARM: Allow compressed dtb binariesSascha Hauer2015-10-271-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the current multi image build process the DTBs end up uncompressed in the PBL. This can be annoying because the PBL is often very size constrained. This patch allows to put the DTBs in as lzo compressed binary into the PBL. Since lzo offers quite good compression ratios for DTBs no other compression algorithm has been implemented for now. Boards which want to use the compressed DTBs only have to change the __dtb_ prefix in the DTB name to __dtb_z_. Also they should select ARM_USE_COMPRESSED_DTB to make sure barebox supports uncompressing the DTB. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: Add support for semihostingAndrey Smirnov2015-10-301-0/+9
|/ | | | | | | | | | Add semihosting API implementation and implement a filesystem driver to access debugging host filesystem using it. Tested on Freescale SabreSD board (i.MX6Q) using OpenOCD Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: select OFTREE and OFDEVICELucas Stach2015-08-261-0/+2
| | | | | | | | | SoCFPGA is completely multi-image enabled and probes the barebox from a built-in DT, so there is no point in building a barebox image that isn't able to probe from DT. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: don't allow Thumb2 on AT91Lucas Stach2015-07-241-1/+1
| | | | | | | AT91 has a custom barebox head that doesn't support Thumb2. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: rockchip: depend on OFTREELucas Stach2015-07-241-0/+1
| | | | | | | | | | | The current supported Rockchip board is initialized from a builtin DTB and I suppose all future boards will do the same. Fixes various missing functions and prototypes in Rockchip clk driver. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/rockchip'Sascha Hauer2015-03-091-0/+1
|\ | | | | | | | | Conflicts: arch/arm/Kconfig
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