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* arm: boards: Add support for PRTT1x STM32MP151 based boardsDavid Jander2021-11-221-0/+7
| | | | | | | | | | | | | | - PRTT1A is a very simple 10Base-T1L Ethernet to 0-10V output converter module. - PRTT1S is a CO2- and RH measurement module with 10Base-T1L and PoDL power sink. - PRTT1C is a "white box switch" device, meant to control the other members of the PRTT1L family of devices, connected via 10Base-T1L and PoDL power. Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.barebox.org/20211118134125.408959-1-o.rempel@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: ddrctrl: add deep-probe supportMarco Felsch2021-06-251-1/+11
| | | | | | | | | | | In case of deep-probe we have to ensure that the memory device is available after the mem_initcall(). Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.pengutronix.de/20201021115813.31645-10-m.felsch@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210625072540.32717-16-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: report probe error at arm_add_mem_device() callsites on failureAhmad Fatoum2021-06-021-3/+1
| | | | | | | | | | | Failure to add one memory bank shouldn't prevent the driver from trying to add other memory banks, but the user should be informed as this points at a misconfiguration. Have the probe functions eventually fail with -EBUSY in such a case. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210531071239.30653-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: add support for STM32MP157-EV1 boardAhmad Fatoum2021-03-171-0/+8
| | | | | | | | | | | | The STM32MP157A-EV1 and STM32MP157C-EV1 Evaluation boards are the full-feature demonstration and development platforms for STMicroelectronics Arm®-based dual Cortex®-A7 32 bits and Cortex®-M4 32 bits MPUs in the STM32MP1 Series. Add support for running barebox as SSBL on either of them. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/reboot-mode' into masterSascha Hauer2020-10-142-26/+2
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| * ARM: stm32mp: remove custom reboot mode logic from arch codeAhmad Fatoum2020-09-292-26/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was ported from U-Boot to support st32mp_get_forced_boot_mode(), which allows board code to customize boot according to values the kernel places in the reboot mode region on the TAMP syscon. We no have a syscon-reboot-mode driver, a device node in the stm32mp151.dtsi, a ${global.system.reboot_mode} variable and a common reboot_mode_get(), which together achieve the same, but in a generic manner. Drop the now duplicate code. There has been no in-tree users so far, so we don't need to touch anything else. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc' into masterSascha Hauer2020-10-144-57/+60
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| * | ARM: stm32mp: dk2: rename to dkx to make dk1 support clearerAhmad Fatoum2020-10-071-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we now support both the stm32mp157a-dk1 and stm32mp157c-dk2 with the same barebox image, we should call the board stm32mp15xx-dkx instead. That's also how the upstream DTSI is named. Suggested-by: Holger Assmann <has@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | bootm: propagate register_image_handler return valueAhmad Fatoum2020-10-071-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | While register_image_handler can't currently fail, it still returns an error code. Propagate that error code along instead of having a blanket return 0. This makes the code a little more compact. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: stm32mp: revision: make CPU type accessible to PBLAhmad Fatoum2020-10-022-51/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is nothing holding holding us back from reading SoC type in the PBL. Migrate the necessary definitions to the header to allow for this. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: stm32mp: init: set up CPU and bootsource at core init levelAhmad Fatoum2020-10-021-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM device tree is unflattened at core init level and banner with model extracted from device tree is printed at console init level. The only init level between is postcore, so board code seeking to modify the device tree machine model should run then. On the STM32MP1, we query SoC type at postcore initcall, so we can't have the board code fixing up the compatible on postcore as well. Resolve this by moving stm32mp_init to core_initcall. This is allowed as the code has no dependency that requires it to run postcore. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / treewide: Use driver macroSascha Hauer2020-09-291-5/+1
|/ | | | | | | We have several macros for a oneline driver registration. Add some missing and use them consistently where possible througout the tree. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: add support for Seeed Odyssey boardAhmad Fatoum2020-08-031-0/+4
| | | | | | | | | | | | | | | | | | Board consists of SoM with stm32mp157c with 4G eMMC and 512M DDR3 RAM. Carrier board features USB and ETH interfaces and SD card connector. USB and ETH interfaces not yet operational. Boot from eMMC requires boot ack bit set. Device Tree taken from v5 of kernel device tree off mailing list[1]. [1]: https://lore.kernel.org/linux-arm-kernel/20200724145107.35772-3-marcin.sloniewski@gmail.com/ Tested-by: Jookia <contact@jookia.org> Tested-by: Xogium <contact@xogium.me> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* stm32mp: init: fix up st, package into stm32mp pinctrl nodesAhmad Fatoum2020-05-121-15/+48
| | | | | | | | | | | Since Linux v5.1, the pinctrl driver can use the st,package property if provided to validate whether the ball to be configured exists on the package. The upstream device trees provide this property, but if we'll want barebox to supply it instead, so we can use the same barebox binary for different SoC variants. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* nvmem: bsec: remove wrongly named bsec_field typeAhmad Fatoum2020-05-081-3/+3
| | | | | | | | | BSEC_SMC_READ_SHADOW and BSEC_SMC_WRITE_SHADOW aren't fields, but operations to apply on fields. Rename it accordingly and fix up instances where it was used wrongly. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: init: fix up CPU device tree nodesAhmad Fatoum2020-05-081-0/+45
| | | | | | | | To facilitate using the same barebox binary for multiple variants of the STM32MP15x, have it fix up the CPU device tree nodes. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: init: detect Revision Z and 800 MHz profilesAhmad Fatoum2020-05-082-6/+53
| | | | | | | | | | | | | | | | | Revision A was 0x1000 and B was 0x2000, so I assumed the next would be revision C valued 0x3000. Alas, it's revision Z with 0x2001... Change the code accordingly and add detection for the new 800Mhz profiles. Code taken from U-Boot commit cf0818b477 ("stm32mp1: support of STM32MP15x Rev.Z") and Patch[1] "stm32mp1: add 800 MHz profile support". [1]: https://st-md-mailman.stormreply.com/pipermail/uboot-stm32/2020-February/002170.html Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: init: don't cast signed error to unsignedAhmad Fatoum2020-05-081-2/+2
| | | | | | | | | bsec_read_field returns a negative value on error, pass it along signed. This doesn't matter now, because we ignore the error code, but it's the correct thing to do. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: add Linux Automation MC-1 supportAhmad Fatoum2020-04-281-0/+4
| | | | | | | | | | | | | | | | | | This adds support for the Linux Automation GmbH MC-1 board built around the Octavo Systems OSD32MP157C-512M SiP. The device tree is based on the one in linux-stm32/stm32-next, which will probably be merged for Linux v5.8-rc1. Instead of waiting that long, we import it here with some stuff removed/changed, so it's usable for both barebox and Linux, without the prerequisite patches. The non-barebox specific parts have been moved into separate DTSIs (arch/arm/dts/stm32mp{157c-lxa-mc1,15xx-osd32}.dtsi), so both can be dropped after the v5.8-rc1 sync with only include path change necessary in arch/arm/dts/stm32mp157c-lxa-mc1.dts. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: add stm32mp_cpu_lowlevel_init with stack set upAhmad Fatoum2019-11-131-1/+12
| | | | | | | | | | | | | | | When barebox is invoked out of the TF-A v2.1, it's started with sp, r0, r1, r2 all equal to zero. To use the new RAM size calculating stm32mp1_barebox_entry, we need to have a stack to handle spillage. Add a stm32mp_cpu_lowlevel_init wrapper around arm_cpu_lowlevel_init, which additionally configures a 64 byte stack after the end of the barebox binary. This should be enough to help us through the RAM size calculation. If not, compression will fail because of data corruption and stack size can be increased as necessary. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: add basic DDR controller driverAhmad Fatoum2019-11-131-0/+34
| | | | | | | | | | | | | | | | The STM32MP DDR Controller has a very flexible way of mapping address bits to columns/rows/banks. This is so far configured by the ARM TF-A as part of the SDRAM setup, so we don't need to do this in barebox. Nevertheless reading it out in barebox, allows us to determine unused address bits and thus the total size of SDRAM configured. Add a simple driver that parses the ddrctrl node and adds an appropriate memory bank. This can later be used to remove explicit calls to arm_add_mem_device in board code. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: add helper for querying ram sizeAhmad Fatoum2019-11-135-0/+500
| | | | | | | | | | | | | | The STM32MP DDR Controller has a very flexible way of mapping address bits to columns/rows/banks. This is so far configured by the ARM TF-A as part of the SDRAM setup, so we don't need to do this in barebox. Nevertheless reading it out in barebox, allows us to determine unused address bits and thus the total size of SDRAM configured. Add a barebox_arm_entry wrapper that computes the SDRAM size internally, so boards may drop their hard-coded RAM size specifications. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: dts: stm32mp: report psci v0.2 at leastAhmad Fatoum2019-11-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | ARM TF-A reports compatibility with PSCI v1.1 since v1.5. Upstream ARM TF-A support for STM32MP was introduced with v1.6. It's thus safe to assume that the STM32MP barebox will never have to interact with a secure monitor implementing PSCI v0.1. Overwrite the psci device tree compatible to specify v0.2. This is the first version that implements PSCI_VERSION, which allows the barebox psci client driver selected in this commit to query the actual PSCI version and fix it up into the device tree. This fixes an issue where resetting via PSCI fails in Linux because the upstream device tree compatible: reboot: Restarting system Reboot failed -- System halted Reported-by: Michael Olbrich <mol@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: select ARM_USE_COMPRESSED_DTB for the whole archAhmad Fatoum2019-11-071-1/+0
| | | | | | | | We'll probably be using compressed DTBs for all new boards as well, thus move the ARM_USE_COMPRESSED_DTB, so it's always selected for STM32MP. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: dk2: add barebox SD-Card update handlerAhmad Fatoum2019-11-061-0/+14
| | | | | | | | Now with the SD/MMC controller supported, lets add a bbu handler, so we can use it to update the second stage boot loader partition. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: implement SoC and boot source identificationAhmad Fatoum2019-11-064-1/+327
| | | | | | | | | | | | | | The BSEC OTP holds information about SoC type and package. The Tamp registers hold information from the BootROM about boot source. Add support for both. Additionally, the tamp registers can also hold a request from the operating system about what mode to enter after boot, e.g. boot-into-recovery. A global function is exported for this, but unused so far. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* nvmem: add read support for STM32MP1 bsec OTPAhmad Fatoum2019-11-062-0/+69
| | | | | | | | | The bsec on the STM32MP157C provides a 380 byte OTP. Add initial support for reading and writing the shadow copy of the fuses. Direct fuse access is not yet supported. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: add bootm handler for imagesAhmad Fatoum2019-10-142-1/+51
| | | | | | | | | | | | STM32 images are preceded by a fixed-size 256 byte header, which is interpreted by the TF-A first stage bootloader and isn't executable as ARM code. To maintain the ability to network boot them, add a bootm handler that skips the header. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: fix some misnomers/typosAhmad Fatoum2019-07-151-2/+2
| | | | | | | | | The arch was renamed to stm32mp, so it doesn't look out of place when the stm32mp2 is released. Fix spotted comments/labels with the old name. While at it, fix a typo about the SoC name on the DK2 board. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: set CONFIG_ARCH_NR_GPIO = (26 * 16)Ahmad Fatoum2019-07-151-0/+4
| | | | | | | | | The STM32MP1 GPIO bindings uses the range [400; 415] for the gpioz controller, which exceeds the barebox-wide ARCH_NR_GPIOS of 256. Therefore have the stm32mp define a subarch-specific max of 416. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp: stm32mp157c-dk2: compress the DTBAhmad Fatoum2019-06-191-0/+1
| | | | | | | This saves 23K with my configuration (from 250K to 227K). Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: stm32mp1: rename to stm32mpAhmad Fatoum2019-06-134-0/+74
Serial and clk driver both depend on CONFIG_ARCH_STM32MP1, so either the Kconfig symbol or their depend needs to change. Patches posted by the vendor to Linux, U-Boot and their BSP Yocto-Layer speak of a STM32MP-Family of which the STM32MP1 is the first series, thus rename the arch by dropping the 1. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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