barebox - barebox master repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	tegra: set AHB clock rate early	Lucas Stach	2014-02-27	1	-0/+4
\| \| \| \| \| \| \|	Avoids glitches in later starup phases. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	tegra: add lowlevel DVC	Lucas Stach	2014-02-27	1	-0/+8
\| \| \| \| \| \| \|	Allows to talk to external PMIC devices to bring up CPU rail. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	tegra: switch main CPU complex to PLLX early	Lucas Stach	2013-12-04	1	-0/+32
\| \| \| \| \| \| \|	Running at 1GHz, rather than 13MHz certainly makes things a bit faster. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	tegra: speed up system bus	Lucas Stach	2013-12-04	1	-0/+12
\| \| \| \| \| \| \| \| \|	We run the system bus from the OSC clock during init, to avoid crashing the system while reconfiguring the PLLs. Switch to a more reasonable clock when we are done with this. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	tegra: add peripheral clocks	Lucas Stach	2013-07-02	1	-0/+49
\| \| \| \| \| \| \| \|	Only UART clocks are included for now, but the code should cover other peripherals needs, too. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	tegra: add new clock framework driver	Lucas Stach	2013-07-02	1	-0/+36
\| \| \| \| \| \| \| \| \| \| \|	This removes the existing Tegra CAR driver and replaces it with code ported from the Linux clock framework. In the current state only the relevant PLLs are supported, but this is no functional regression from the existing code. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	tegra: deduplicate clk defines	Lucas Stach	2013-07-02	1	-60/+30
\| \| \| \| \|	Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	tegra: add common lowlevel startup	Lucas Stach	2013-04-14	1	-0/+157
\| \| \| \| \| \| \| \| \| \| \| \| \| \|	All Tegra20 boards have a common startup sequence. Also there is an agreement on how to find out about the installed amount of RAM and other information needed by early startup. So as there is really no need to do any lowlevel stuff per board, we can just do it at the ARCH level. This also enables the first stage loading of barebox by detecting the currently running CPU and booting the main CPU cluster if neccesary. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	tegra: add driver for the clock and reset module	Lucas Stach	2013-04-14	1	-0/+22
	Only a basic set of clocks is supported. This is a temporary solution and will go away as soon as the port of the Tegra common clock code from the Linux kernel is ready to go. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>