barebox - barebox master repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	ARM: zynqmp: add update handler	Michael Tretter	2021-06-25	3	-0/+70
\| \| \| \| \| \| \| \| \| \| \| \|	The ZynqMP boots from an SDHCI device by reading a boot.bin file from the FAT16/32 partition, which is the first partition in the MBR. The update handler copies a boot.bin image to this partition, which might be board specific. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20210624150054.1205422-5-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM: zynqmp: set reset source	Michael Tretter	2021-06-25	2	-0/+73
\| \| \| \| \| \| \| \| \| \| \| \|	The reset reason is available in the APB register set on the ZynqMP. Read the reset reason and set the reset source accordingly. There might be multiple bits set in the APB register. Use the MSB for determining the actual reset source. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20210624150054.1205422-2-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	treewide: Use driver macro	Sascha Hauer	2020-09-29	1	-5/+1
\| \| \| \| \| \| \|	We have several macros for a oneline driver registration. Add some missing and use them consistently where possible througout the tree. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	firmware-zynqmp: extend driver with fpga relavant functions	Thomas Haemmerle	2019-10-28	2	-2/+60
\| \| \| \| \| \| \| \|	Port functions from xlnx-linux to get FPGA status and invoke bitstream loading. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	firmware-zynqmp: add macros for PMU and trustzone firmware versions	Thomas Haemmerle	2019-10-28	1	-12/+10
\| \| \| \| \|	Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM: zynqmp: move PAYLOAD_ARG_CNT to firmware header	Michael Tretter	2019-03-18	2	-2/+2
\| \| \| \| \| \| \| \|	In order to use the query() call, the users of the firmware driver need to know the number of arguments. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM: zynqmp: populate zynqmp_firmware dt node	Thomas Haemmerle	2019-03-18	1	-0/+1
\| \| \| \| \| \| \| \| \| \|	The zynqmp_firmware node has sub-nodes for the various APIs to expose the platform management, as e.g. clock management. Therefore, the driver must populate the subnodes to initialize these drivers. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	firmware-zynqmp: port from linux	Thomas Haemmerle	2019-02-27	3	-1/+668
\| \| \| \| \| \| \|	Port Xilinx Zynq MPSoC Firmware layer driver from linux. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM: zynqmp: add support for Xilinx ZCU104 board	Michael Tretter	2018-12-10	3	-0/+43
	Add support for the Xilinx Zynq Ultrascale+ MPSoC architecture (ZynqMP) and the Xilinx ZCU104 board. Barebox is booted as BL33 in EL-1 and expects that a BL2 (i.e. the FSBL) already took care of initializing the RAM. Also for debug_ll, the UART is expected to be already setup correctly. Thus, you have to add the Barebox binary to a boot image as described in "Chapter 11: Boot and Configuration" of "Zynq Ultrascale+ Device Technical Reference Manual". Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>