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* ARM: dts: phycore-imx6: change mtd-partition names for compatibility with kernelYunus Bas2020-03-051-5/+5
| | | | | | | | | | | | | | The NVMEM-subsystem in newer kernels does not allow identical partition names on different subdevices. According to the recommendation, we have to rename the partition names to be compatible with actual kernel versions. To minimize the problems which could possibly arise, the nand device is not changed. For all other devices, we prepend the device name to the partitions. Signed-off-by: Yunus Bas <y.bas@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: dts: Add missing #size/address-cells propertiesSascha Hauer2020-03-022-0/+4
| | | | | | | Some boards lack the #address-cells/#size-cells properties for the i.MX6 GPMI nand controller. Add them. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: vf610-zii-scu4-aib: Remove non effective propertiesSascha Hauer2020-03-021-8/+0
| | | | | | | | | The vf610-zii-scu4-aib dts contains a fixup for nodes which do not exist anymore, so instead of fixing up the nodes new ones are created which is surely not intentional. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
* arm: dts: Fix node namesSascha Hauer2020-03-027-11/+11
| | | | | | | | | | - Remove leading zeroes from the addresses in the node names of i2c/spi devices - Remove leading 0x from the addresses in the node names of i2c/spi devices - Add missing reg address in node names. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: update imx_v8_defconfig for i.MX8MMSascha Hauer2020-02-191-2/+16
| | | | | | Enable support for the i.MX8MM EVK and some of its peripherals. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: Add i.MX8MM EVK board supportSascha Hauer2020-02-199-0/+2322
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: Add i.MX8MM supportSascha Hauer2020-02-1913-25/+215
| | | | | | This adds support for the i.MX8MM. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: Add TF-A loading support for i.MX8MMSascha Hauer2020-02-193-10/+27
| | | | | | | Basically the same as for i.MX8MQ, just some function split up needed to account for different base addresses for the TF-A on both SoCs. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: Add DDR controller supportSascha Hauer2020-02-1911-184/+8
| | | | | | | | | | | | | | | This adds the DDR driver for the i.MX8MQ/i.MX8MM. It's taken from U-Boot v2020.04-rc1 with slight modifications for barebox The i.MX8MQ boards in the tree currently use the output of an earlier version of the NXP i.MX8M DDR Tool which doesn't use a controller driver but instead does most stuff in board code. It seems this can coexist with the new driver, only a few helper functions that previously lived in arch/arm/mach-imx/imx8-ddrc.c are now provided by the new driver. Tested on an i.MX8MM EVK Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8MQ boards: Add missing includesSascha Hauer2020-02-193-0/+3
| | | | | | | | The i.MX8MQ board files all use get_builtin_firmware(), thus need include/firmware.h. This is currently only indirectly included, include it directly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: Add and use function for early UART clock setupSascha Hauer2020-02-195-24/+30
| | | | | | | | The i.MX8M boards all have the same code for setting up the UART clock. Add a common helper for it. In the helper just setup the clocks for all UARTs as it's not worth it to have separate functions for each UART. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX7: Add and use function for early UART clock setupSascha Hauer2020-02-193-16/+14
| | | | | | | The i.MX7 boards have the same code for setting up the UART clock. Add a common helper function for it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: Add some lowlevel clock functionsSascha Hauer2020-02-192-0/+28
| | | | | | | | U-Boot has some lowlevel clock functions which take a clock slice index as argument. Add them for barebox as well to make the code better comparable to U-Boot. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: rename imx8-ccm-regs.h to imx8m-ccm-regs.hSascha Hauer2020-02-194-3/+3
| | | | | | | i.MX8 is something different than the i.MX8M and both will not share this header file, so rename it to imx8m-ccm-regs.h Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Add some CCM defines for i.MX8MSascha Hauer2020-02-191-2/+23
| | | | | | | This adds some clock slice indices and CCGR defines needed for the lowlevel i.MX8M code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: Add SoC namespace to imx7/8m CCM definesSascha Hauer2020-02-197-44/+74
| | | | | | | | | The CCM defines used on i.MX7 and i.MX8M do not have any SoC namespace. Add it to make clear where they are supposed to be used. Since it looks confusing to call i.MX7 specific defines on i.MX8M and vice versa, duplicate them for both SoCs. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: rename functions to be i.MX8M specificSascha Hauer2020-02-194-4/+4
| | | | | | | imx8_esdhc_load_image() and friends can't be used on the big variants of the i.MX8, so rename to imx8m_esdhc_load_image() Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: rename i.MX8M specific functionSascha Hauer2020-02-194-5/+5
| | | | | | | The big i.MX8 variants have completely other UARTs than the i.MX8M variants, so rename imx8_uart_setup_ll() to imx8m_uart_setup_ll(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: Detect serial downloader mode correctlySascha Hauer2020-02-191-3/+16
| | | | | | | | like the i.MX6 the i.MX7 and i.MX8M also have a SBMR2 register which must be consulted for the BOOT_MODE[01] pins before internal bootmode can be assumed. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: rename imx8_* bootsource functions to imx8mq_*Sascha Hauer2020-02-196-9/+9
| | | | | | | Those will differ between i.MX8MQ and i.MX8MM, so give them the appropriate prefix before introducing i.MX8MM support. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: Use imx8mq.c for other i.MX8M as wellSascha Hauer2020-02-192-1/+1
| | | | | | | Most of the code in imx8mq.c can be reused for i.MX8MM, so rename it and compile depending on CONFIG_ARCH_IMX8M. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: esdctl: rename functions to imx8m_*Sascha Hauer2020-02-191-10/+15
| | | | | | | The imx8mq_* functions can be reused for all i.MX8M SoCs, so rename them accordingly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: Add ARCH_IMX8M symbolSascha Hauer2020-02-191-1/+5
| | | | | | | Several things are common between the different i.MX8M variants. Add a Kconfig symbol for it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: Add imx8mm-regs.hSascha Hauer2020-02-191-0/+46
| | | | | | Add various base addresses for the i.MX8MM. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: Add iomux header for i.MX8MMSascha Hauer2020-02-191-0/+701
| | | | | | | This adds the iomux definitions for the i.MX8MM, taken from U-Boot 2020-rc1. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: Drop iomux argument from mx7_setup_pad()Sascha Hauer2020-02-193-5/+5
| | | | | | | | | The name mx7_setup_pad already implies the SoC where it runs on, so we do not have to pass the iomux base address but can hardcode it in the function. While at it rename it to imx7_setup_pad() which is more consistent to other i.MX specific functions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: add and use imx8mq_setup_pad()Sascha Hauer2020-02-194-6/+11
| | | | | | | | | | We already have a mx8_setup_pad() function for early iomux setup, but it is unused. Add a i.MX8MQ specific wrapper for the function which passes the correct base address to mx8_setup_pad(). Let the boards use this function. While at it rename mx8_setup_pad() to imx8_setup_pad() which is more consistent to other i.MX specific functions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8M: Add base addresses common to i.MX8MSascha Hauer2020-02-192-0/+39
| | | | | | | | | | This adds defines for the base addresses common to all currently existing i.MX8M SoCs. Only the base addresses that are known to be needed for the early SoC code are added. With this we can reuse the early code for all variants without guessing that the base addresses are the same for the other variants. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8: Move iomux header to make space for i.MX8MMSascha Hauer2020-02-195-24/+31
| | | | | | | | Parts of iomux-mx8.h are for i.MX8M and others for i.MX8MQ only, but never for i.MX8 in general. Split this up into different file and avoid the imx8_ prefix. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: scb9328: Add missing machine protectionSascha Hauer2020-02-181-0/+3
| | | | | | | Make sure scb9328_devices_init() is only executed on the correct machine. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/optee'Sascha Hauer2020-02-189-10/+172
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| * ARM: mach-imx: test PL310 write accessRouven Czerwinski2020-01-301-0/+20
| | | | | | | | | | | | | | | | | | | | If OP-TEE early loading is performed, OP-TEE will configure the PL210 and lock write access to the controller from the normal world. Test this by trying to write the same value back and do not configure if we can not write to the PL310. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: add optee early loading functionRouven Czerwinski2020-01-303-1/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a OP-TEE early loading function which expects a pointer to a valid tee binary and the device tree. OP-TEE will then be started and barebox will continue to run in normal mode. The function start_optee_early should be used in a boards lowlevel.c file. Ensure that barebox has been relocated and a proper c environment has been setup beforehand. Depending on the OP-TEE configuration, the fdt will be modified. If the internal barebox device tree is passed, OP-TEE will overwrite barebox PBL memory during this modification. Copy the fdt to a save memory location beforehand to avoid a corruption of barebox PBL memory. This also moves the OP-TEE Kconfig symbols into a separate menu. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: import setjmp implementation from U-BootRouven Czerwinski2020-01-305-0/+108
| | | | | | | | | | Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * optee: move optee_verify_header() to commonRouven Czerwinski2020-01-281-9/+3
| | | | | | | | | | | | | | | | Subsequent patches will use this to verify the header in the PBL, move it to common to make it potentially available for both. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2020-02-182-0/+9
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| * | ARM: stm32mp: dk2: barebox_set_model to shorter nameAhmad Fatoum2020-02-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The full "STMicroelectronics STM32MP157C-DK2 Discovery Board" is a tad too long. Abbreviate it to STM32MP157C-DK2 instead. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | images: Use separate LDFLAGS for PBLChristian Eggers2020-02-101-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When setting CONFIG_PBL_RELOCATABLE=y (selected by PBL_MULTI_IMAGES) and CONFIG_RELOCATABLE=n (trying to reduce image size), the PBL is also linked with "-static" instead of "-pie". The result is a non-working PBL. As a side effect, also get rid of erroneous "-Map barebox.map" when linking the PBL. Only changed for ARM, are any other platforms affected? Signed-off-by: Christian Eggers <ceggers@arri.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/imx'Sascha Hauer2020-02-184-12/+50
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| * | | ARM: phyCORE-i.MX8M SOM: add pmic initialisation for power goodMichael Grzeschik2020-02-031-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is adding the same PMIC handling as the u-boot spl does for this Board. It ensures sane defaults. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | regulator: pfuze: add support to other architecturesMichael Grzeschik2020-02-032-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the pfuze driver is build dependent to ARCH_IMX6. To make it possible to work with ARCH_IMX8 we move the imx6_poweroff call to an own poweroff handler. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | imx25: drop global over-current setting for USBUwe Kleine-König2020-01-161-8/+0
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no mx25 board in mainline that actually uses USB. My (out-of-tree) board has active low polarity which makes it necessary to have /delete-property/ over-current-active-high; over-current-active-low; in the board's dts which is ugly. In the absence of this property Linux defaults to active-high and encourages explicit configuration (see commit 1bf4743f641d ("usb: chipidea: imx: Warn if oc polarity isn't specified")), so other external board dts files likely already have this setting anyhow. (OK, maybe a bit optimistic here :-) Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | / dts: update to v5.6-rc1Sascha Hauer2020-02-181-8/+0
| |/ |/| | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: imx6: properly check for IPU presenceLucas Stach2020-01-271-2/+11
|/ | | | | | | | | | | | | Since a73850bd76d0 (ARM: imx: disable IPU QoS setup for correct SoCs), which fixed the condition to not execute the IPU QoS fixups on SoCs that don't have a IPU, the fixups aren't applied on i.MX6Q/DP anymore, since those SoCs were missing from the whitelist. Add a function to make it a bit more clearer what we are checking here and add the Q/DP SoCs. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: qemu-virt64: convert to assembly entryLucas Stach2020-01-163-2/+16
| | | | | | | | | | The C entry function isn't naked, so tries to push to the stack in the function prologue. This doesn't work on QEMU where there is no valid SP on entry. Convert the lowlevel entry to the assembly facilities provided for this case. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/zynq'Sascha Hauer2020-01-157-4/+150
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| * ARM: zynq: zedboard: add PBL console supportLucas Stach2020-01-141-0/+16
| | | | | | | | | | | | | | Allows for significantly easier debugging of PBL functions. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: zed: partially revert zynq_cpu_lowlevel_init() chnagesLucas Stach2020-01-142-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Calling arm_cpu_lowlevel_init() from zynq_cpu_lowlevel_init() adds a stack push/pop to the latter function which doesn't work this early in the boot. As the BootROM apparently hands proccessor control to us in abort(!?!) mode, setting up a stack requires duplicating most of arm_cpu_lowlevel_init(). To get around this catch-22 move the call to arm_cpu_lowlevel_init back into the board lowlevel start function, so we don't need a stack at all. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: zed: use zynq_cpu_lowlevel_init()Lucas Stach2020-01-081-1/+2
| | | | | | | | | | | | | | Make sure the required workarounds for CPU errata are applied. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: add Zynq specific lowlevel CPU init functionLucas Stach2020-01-083-0/+24
| | | | | | | | | | | | | | | | This adds a Zynq specific CPU lowlevel init function, which applies the required workarounds for the Cortex A9 r3p0 core. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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