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* ARM: mvebu: remove obsolete selectUlrich Ölmann2017-03-301-1/+0
| | | | | | | | This is a user choice now and has been removed for all other boards in commit 790980bf18af ("Make generic default environment type a use choice"). Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* poweroff: Allow to register poweroff handlersSascha Hauer2017-03-305-16/+37
| | | | | | | | | | Allow to register handlers for poweroff. This allows to have multiple poweroff implementations in a single binary. The implementation is close to the restart handlers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mvebu: only build kwbootimage support if BOOTM is enabledLucas Stach2017-03-221-1/+1
| | | | | | | | As this is the bootm image handler implementation for the kwbootimage it is of no use if BOOTM is missing and fails to link. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: add AFLAGS for secure monitor filesLucas Stach2017-03-221-0/+2
| | | | | | | The instructions used in those files are only supported on ARMv7. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: dts: i.MX7 WaRP7: remove wdog1 pinctrl workaroundAlexander Kurz2017-03-201-17/+0
| | | | | | | | | The wdog1 pinctrl got fixed with linux upstream commit 213e51ca8df1 ("ARM: dts: imx7: Add "LPSR" to LPSR iomux pin names"). Remove the old workaround, since it triggers a build error. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX7: Kconfig: ARCH_IMX7 selects PINCTRL_IMX_IOMUX_V3Alexander Kurz2017-03-201-0/+1
| | | | | | | | fsl,imx7d-iomuxc is provided by selecting PINCTRL_IMX_IOMUX_V3. Select it since a system without it will not be very usefull. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: baltos: define baltos_sram_init() return type as voidYegor Yefremov2017-03-131-1/+1
| | | | | | | | As stated in the routine's description this routine is to return void, hence fix its declaration to remove compiler warning. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/rpi'Sascha Hauer2017-03-1322-280/+283
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| * ARM: rpi: switch to DT probe and multi-image buildLucas Stach2017-03-0212-173/+75
| | | | | | | | | | | | | | | | This commit switches the RaspberryPi arch over to probe Barebox from the builtin DT and enables multi-image builds. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: rpi: move debug UART base selection to KconfigLucas Stach2017-03-022-1/+25
| | | | | | | | | | | | | | To let the user select the right base, when building multi-image. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: rpi: always build relocatable imageLucas Stach2017-03-022-1/+2
| | | | | | | | | | | | | | | | Makes more space available for the malloc area and will allow to switch to multi-image later on. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: rpi: convert watchdog/reset to regular driverLucas Stach2017-03-026-21/+85
| | | | | | | | | | | | | | This way it can be probed from DT later on. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: rpi: convert mailbox interface to regular driverLucas Stach2017-03-025-20/+63
| | | | | | | | | | | | | | In prepareation for devicetree probing. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: rpi: move model detection before console initLucas Stach2017-03-021-2/+2
| | | | | | | | | | | | | | This way we can print the correct model in the Barebox banner. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: rpi: move model initialisation to rpi-commonEnrico Joerns2017-03-025-79/+48
| | | | | | | | | | | | | | | | | | | | | | The Raspberry PIs use different versions schemes for the older and newer variants. The decoding arrays for these schemes were split up in rpi.c and rpi2.c. This is not required, as the appropriate versioning scheme can be determined programmatically. Signed-off-by: Enrico Joerns <ejo@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/mvebu'Sascha Hauer2017-03-1321-261/+333
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| * | mvebu: netgear-rn2120: make use of mvebu_get_initial_int_reg_baseUwe Kleine-König2017-03-021-5/+7
| | | | | | | | | | | | | | | | | | | | | This is necessary to make second stage booting work when the register window is already moved. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
| * | kwbimage_v1: add support to boot a mvebu imageUwe Kleine-König2017-03-022-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | This just starts the main image of the mvebu image assuming that the header images just setup the RAM. The position of the internal register window is provided in the header as introduced in the previous commit. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
| * | mvebu: get initial position of register window from image headerUwe Kleine-König2017-03-024-3/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A problem when using 2nd stage booting on mvebu is that the first bootloader already switched the register window location from 0xd0000000 to 0xf1000000 by writing to 0xd0000080. When the second bootloader also tries to do this switch it writes to the wrong location resulting in an exception and so a boot failure. For this reason the base address of the register window is passed in the barebox header and picked up from there by early code. In a further patch bootm is taught to put the actual position of the window there for the second bootloader to finally make second stage booting work. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
| * | mvebu: rn2120: Make available all RAMUwe Kleine-König2017-03-021-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | binary.0 sets up all RAM but the address decoding isn't adapted accordingly which makes barebox assume that there are only 512 MiB of RAM on a single bank instead of two banks with 1 GiB each. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
| * | mvebu: kirkwood: simplify soc init code flowUwe Kleine-König2017-03-021-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to the two previous commits, this gets rid of a of-fixup which is strange because the soc init stuff is rerun then when a new dt for booting into Linux is loaded. The initcall must be postponed to post-core to ensure of_machine_is_compatible is working correctly. The call to mvebu_mbus_add_range is moved to drivers/bus/mvebu-mbus.c to ensure it's registered early enough. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mvebu: dove: simplify soc init code flowUwe Kleine-König2017-03-021-11/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to the previous commit, this gets rid of a of-fixup which is strange because the soc init stuff is rerun then when a new dt for booting into Linux is loaded. The initcall must be postponed to post-core to ensure of_machine_is_compatible is working correctly. The call to mvebu_mbus_add_range is moved to drivers/bus/mvebu-mbus.c to ensure it's registered early enough. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mvebu: armada-370-xp: simplify soc init code flowUwe Kleine-König2017-03-021-23/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This gets rid of a of-fixup which is strange because the soc init stuff is rerun then when a new dt for booting into Linux is loaded. The initcall must be postponed to post-core to ensure of_machine_is_compatible is working correctly. The call to mvebu_mbus_add_range is moved to drivers/bus/mvebu-mbus.c to ensure it's registered early enough. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mvebu: rework how memory is detectedUwe Kleine-König2017-02-1618-192/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Status quo is that initially a size of 64 MiB is assumed (which is also used to determine the size of the malloc area) and then later the dtb is fixed up with the actually available RAM which is then used. Instead detect the real RAM size earlier and don't fixup the device tree. The device tree is fixed up instead by generic code. This way the malloc area is more appropriately sized and RAM detection is more similar to mach-imx which is both nice. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mvebu: remove unused function barebox_arm_reset_vectorUwe Kleine-König2017-02-161-6/+0
| | | | | | | | | | | | | | | | | | | | | This isn't needed since mvebu was converted to multi-pbl Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mvebu: simplify detection and fixup of MV78230-A0Uwe Kleine-König2017-02-161-19/+12
| | | | | | | | | | | | | | | Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/imx'Sascha Hauer2017-03-136-40/+30
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| * | | scripts: imx/mxs remove mxs-usb-loaderOleksij Rempel2017-03-093-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ... and use imx-usb-loader instead Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | arm: boards: phytec-som-am335x: Remove 1GB RAM typeDaniel Schultz2017-03-012-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This machine was a prototype and was never shipped to customers. Since it has no dependencies to any image, it can be removed. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | arm: imx: don't let MACH_SABRELITE select HAVE_PBL_MULTI_IMAGESUwe Kleine-König2017-02-161-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MACH_SABRELITE is only selectable if IMX_MULTI_BOARDS is enabled. The latter already selects HAVE_PBL_MULTI_IMAGES. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX: iim: Only register actually equipped fusesSascha Hauer2017-02-141-3/+29
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | The IIM unit in defferent i.MX SoCs is always the same, but the number of actually equipped fuses differs between the SoCs. Reading nonexistent fuses oopses, so only register the fuses we can actually read. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/at91'Sascha Hauer2017-03-1313-213/+95
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| * | | clocksource: at91: Move to 'drivers/clocksource'Andrey Smirnov2017-03-093-120/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move PIT driver code to 'drivers/clocsource' and accomodate it by adjusting Kconfig variables. Rename the file to 'timer-atmel-pit.c' to re-align the driver with code in Linux kernel. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | at91: Fix bug/typo in debug_ll.hAndrey Smirnov2017-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct "COFNIG" to "CONFIG". Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | at91: serial: pullup RX pins, do not pullup TX pinsPeter Rosin2017-02-149-92/+92
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have a number of sama5d3 devices that sometimes hangs at the barebox prompt during boot due to floating RX pins. This patch fixes the problem for us (and probably others). It is similar in nature to linux kernel commit 138c2b2f175b ("ARM: dts: at91: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx") While at it, remove pointless waste of power that the pullup of the TX pins causes and fix the signal comments for SAMA5D4. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | ARM: imx233-olinuxino: add CONFIG_CONSOLE_ACTIVATE_ALLOleksij Rempel2017-03-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | if not set, barebox will use first console by default. On this board first console is KEYBOARD_GPIO, so we will end in unusable state. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | ARM: execute DMB before trying to flush cacheLucas Stach2017-03-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU write buffer needs to be coherent with the cache, otherwise we might flush stale entries with the actual data stuck in the cache. This is really important on newer CPU core with bigger write buffers. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | ARM: correctly identify ARMv6 K/ZLucas Stach2017-03-032-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARMv6 K/Z derivatives have a v7 compatible MMU, but all other parts (including the cache handling) is still at v6. As we don't make use of the more advanced features of the v7 MMU in Barebox, it's okay to just override this to properly identify the CPU as ARMv6. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | ARM: align exception vectors to 32 byteLucas Stach2017-03-031-1/+1
| |/ |/| | | | | | | | | | | | | | | | | | | On ARMv7 the exception vectors inside the barebox binary are used directly by remapping the vectors base through the VBAR register. While VBAR allows to remap the exception vectors freely, it still imposes a minimum alignment of 32 byte, as the lower bits are treated as the exception vector offset. Enforce this alignment inside the barebox binary. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: i.MX50: do not pass base address to imx53_boot_save_locAlexander Kurz2017-02-221-1/+1
|/ | | | | | | This is a follow-up on commit cf3dfafff4cb. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2017-02-1376-104/+6272
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| * ARM: i.MX7: Add PSCI supportSascha Hauer2017-02-132-0/+90
| | | | | | | | | | | | | | This adds the SoC specific PSCI bits for i.MX7. Based on the corresponding U-Boot code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add PSCI supportSascha Hauer2017-02-1317-6/+1092
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains the barebox implementation for the ARM "Power State Coordination Interface" (PSCI). The interface is aimed at the generalization of code in the following power management scenarios: * Core idle management. * Dynamic addition and removal of cores, and secondary core boot. * big.LITTLE migration. * System shutdown and reset. In practice, all that's currently implemented is a way to enable the secondary core one some SoCs. With PSCI the Kernel is either started in nonsecure or in Hypervisor mode and PSCI is used to apply power to the secondary cores. The start mode is passed in the global.bootm.secure_state variable. This enum can contain "secure" (Kernel is started in secure mode, means no PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available) or "hyp" (Kernel is started in hyp mode, meaning it can support virtualization). We currently only support putting the secure monitor code into SDRAM, which means we always steal some amount of memory from the Kernel. To keep things simple for now we simply keep the whole barebox binary in memory The PSCI support has been tested on i.MX7 only so far. The only supported operations are CPU_ON and CPU_OFF. The PSCI and secure monitor code is based on the corresponding U-Boot code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add smc call supportSascha Hauer2017-02-083-0/+170
| | | | | | | | | | | | Taken from the Kernel: A wrapper to make a smc call from C. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Add UNWIND macroSascha Hauer2017-02-081-0/+6
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: vf610: Add support for ZII VF610 Dev FamilyAndrey Smirnov2017-02-0717-0/+2848
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for ZII VF610 Dev based designs such as: - VF610 Dev, revision B - VF610 Dev, revision C - CFU1, revision A - SPU3, revision A - SCU4 AIB, revision C Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX7: Initialize CSUSascha Hauer2017-02-061-0/+14
| | | | | | | | | | | | | | The CSU needs to be initialized, otherwise we cannot access memory in non secure mode. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: i.MX7: Add imx7s.dtsiSascha Hauer2017-02-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | Needed for compiling the i.MX7 warp board which already includes this file. This file is necessary because the upstream dtsi file currently assigns MX7D_CLK_DUMMY to the gpt1 clock we use, so we won't get a meaningful clock rate. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * pinctrl: i.MX7: Fix LPSR sel_imput settingSascha Hauer2017-02-061-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX7 has two pinmux controllers, the regular and the LPSR controller. The LPSR pinmux controller doesn't have any sel_input registers, instead they can be found in the regular pinmux controller. This means whenever we want to apply the the sel_input setting for the LPSR controller, we have to apply them to the regular controller instead. In barebox take the easy way out and just add the difference of the two base addresses to the register offset. The same issue is present in the Kernel aswell, but when the bootloader already configured the pins correctly nobody notices when the Kernel sel_input setup effectively is a no-op. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM i.MX: Add i.MX6SL supportAlexander Kurz2017-02-022-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Most i.MX6SL infrastructure is already covered in barebox by general i.MX6 support. Missing infrastructure provided in separate commits are * SoC type detection * Clock infrastructure Add the missing fsl,imx6sl-mmdc, so it will not be catched by fsl,imx6q-mmdc and the remaining bits and pieces to provide barebox i.MX6SL SoC support. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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