| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | RISC-V: cpu: fix build with CONFIG_RISCV_EXCEPTIONS=n | Ahmad Fatoum | 2022-01-05 | 1 | -0/+2 |
| * | RISC-V: interrupts: fix Zifencei emulation on rv64 | Ahmad Fatoum | 2021-12-13 | 1 | -1/+1 |
| * | serial: implement riscv SBI console support | Marcelo Politzer | 2021-10-05 | 1 | -0/+12 |
| * | RISC-V: support incoherent I-Cache | Ahmad Fatoum | 2021-06-24 | 2 | -0/+16 |
| * | RISC-V: add exception support | Ahmad Fatoum | 2021-06-24 | 4 | -0/+193 |
| * | RISC-V: dma: support multiple dma_alloc_coherent backends | Ahmad Fatoum | 2021-06-24 | 2 | -0/+75 |
| * | RISC-V: S-Mode: propagate Hart ID | Ahmad Fatoum | 2021-06-24 | 1 | -1/+33 |
| * | RISC-V: cpu: request stack memory region | Ahmad Fatoum | 2021-03-29 | 1 | -0/+12 |
| * | clocksource: add driver for RISC-V and CLINT timers | Ahmad Fatoum | 2021-03-23 | 3 | -0/+91 |
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index : barebox | |
| barebox master repository | Pengutronix |
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