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* Merge branch 'for-next/spdx'Sascha Hauer2022-01-199-0/+18
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| * arch: add SPDX-License-Identifier to all headersAhmad Fatoum2022-01-059-0/+18
* | RISC-V: add stacktrace support via frame pointer walkingAhmad Fatoum2022-01-123-6/+13
* | RISC-V: don't use x8/s0/fp in assemblyAhmad Fatoum2022-01-123-35/+35
* | RISC-V: virt: riscvemu: add HTIF DEBUG_LL supportAhmad Fatoum2022-01-122-0/+20
* | power: reset: add RISC-V/UC Berkely HTIF poweroff driver supportAhmad Fatoum2022-01-121-0/+31
* | include: <asm/csr.h>: sync with upstreamAhmad Fatoum2022-01-101-52/+161
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* Merge branch 'for-next/misc'Sascha Hauer2021-12-152-2/+15
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| * RISC-V: virt: add DEBUG_LL supportAhmad Fatoum2021-12-071-2/+8
| * RISC-V: enable HW_HAS_PCIAhmad Fatoum2021-11-251-0/+7
* | Merge branch 'for-next/efi'Sascha Hauer2021-12-152-4/+8
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| * | asm-generic: move sync_caches_for_execution declaration to <asm/cache.h>Ahmad Fatoum2021-11-252-4/+8
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* / RISC-V: nmon: fix SiFive DEBUG_LL buildAhmad Fatoum2021-11-301-1/+1
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* RISC-V: add LiteX SoC and linux-on-litex-vexriscv supportAntony Pavlov2021-10-072-0/+126
* RISC-V: make it possible to run nmon from PBL C codeAntony Pavlov2021-07-091-17/+32
* RISC-V: StarFive: add board support for BeagleV StarlightAhmad Fatoum2021-06-241-0/+3
* net: designware: fix non-1:1 mapped 64-bit systemsAhmad Fatoum2021-06-241-0/+10
* drivers: soc: sifive: add basic L2 cache controller driverAhmad Fatoum2021-06-241-0/+27
* RISC-V: support incoherent I-CacheAhmad Fatoum2021-06-242-0/+18
* RISC-V: add exception supportAhmad Fatoum2021-06-244-0/+260
* RISC-V: dma: support multiple dma_alloc_coherent backendsAhmad Fatoum2021-06-241-35/+13
* RISC-V: erizo: make it easier to reuse ns16550 debug_llAhmad Fatoum2021-06-241-2/+5
* RISC-V: S-Mode: propagate Hart IDAhmad Fatoum2021-06-242-2/+24
* RISC-V: cpuinfo: return some output for non-SBI systems as wellAhmad Fatoum2021-06-211-6/+2
* RISC-V: extend multi-image to support both S- and M-ModeAhmad Fatoum2021-06-212-1/+50
* RISC-V: asm: barebox-riscv-head: use load-offset of 0Ahmad Fatoum2021-05-171-1/+1
* RISC-V: sifive: add HiFive board supportAhmad Fatoum2021-05-171-0/+14
* RISC-V: add SBI based cpuinfoAhmad Fatoum2021-05-101-6/+26
* RISC-V: erizo: drop mach-erizo directoryAhmad Fatoum2021-05-102-0/+35
* RISC-V: debug_ll: ns16550: split off debug_ll from generic partsAhmad Fatoum2021-05-032-32/+65
* RISC-V: boot: uncompress: determine piggy data bounds before relocationAhmad Fatoum2021-04-131-1/+3
* RISC-V: boot: move stack top to very end of memoryAhmad Fatoum2021-03-291-1/+1
* RISC-V: board-dt-2nd: ensure FDT doesn't overlap with early mem regionsAhmad Fatoum2021-03-291-0/+9
* clocksource: add driver for RISC-V and CLINT timersAhmad Fatoum2021-03-233-0/+373
* RISC-V: add 64-bit supportRouven Czerwinski2021-03-232-8/+1
* RISC-V: erizo: migrate to PBLAhmad Fatoum2021-03-231-0/+1
* RISC-V: implement PBL and relocation supportAhmad Fatoum2021-03-235-1/+139
* RISC-V: implement PBL image headerAhmad Fatoum2021-03-232-0/+101
* RISC-V: import Linux' optimized string functionsAhmad Fatoum2021-03-231-1/+20
* RISC-V: add cacheless HAS_DMA supportAhmad Fatoum2021-03-231-0/+44
* RISC-V: debug_ll: ns16550: align C access size with assembly'sAhmad Fatoum2021-03-231-6/+10
* RISC-V: <asm/unaligned.h>: don't do unaligned accessesAhmad Fatoum2021-03-231-12/+4
* riscv: Implement setjmp/longjmp/initjmp for RV32ISascha Hauer2021-03-171-0/+27
* riscv: Add asm/linkage.hSascha Hauer2021-03-171-0/+12
* riscv: Add asm/asm.hSascha Hauer2021-03-171-0/+69
* asm/debug_ll_ns16550.h: add divisor parameterduhuanpeng2020-09-291-2/+2
* arch: include <asm-generic/int-ll64.h> from <asm/types.h>Masahiro Yamada2020-05-181-40/+2
* Kconfig: retire empty <asm/barebox.h>Ahmad Fatoum2019-08-301-1/+0
* riscv: use generic bitsperlong.hMasahiro Yamada2019-08-121-10/+1
* move umode_t typedef from asm/types.h to linux/types.hAntony Pavlov2019-01-181-2/+0
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