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* serial: implement riscv SBI console supportMarcelo Politzer2021-10-052-0/+22
| | | | | | | | Implement a console over legacy SBI (version 0.1.0). There is a tiny ringbuffer to simplify checking for presence and reading characters as separate steps. Link: https://lore.barebox.org/20210927200521.7996-1-marcelo.politzer@cartesi.io Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* x86: define phys_to_virt and virt_to_physAhmad Fatoum2021-08-231-0/+10
| | | | | | | | Some PCI drivers use those, so provide 1:1 implementations. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210812121944.4419-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* asm-generic: include bitio.h from io.hAhmad Fatoum2021-08-233-2/+10
| | | | | | | | | | | | | | This is currently used on ARM and sandbox, but it's relevant for other platforms like x86 as well if driver code wants to make use of the functions defined within. MIPS and PowerPC already defines the symbols, but that's ok because <bitio.h> doesn't override existing macros. This works for MIPS, but not PowerPC, where those aren't macros. Fix that up. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210812121944.4419-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: rockchip-rk3568-evb: add hardware id detectionMichael Riesch2021-08-231-0/+62
| | | | | | | | | | | | The RK3568 EVB uses a voltage divider to determine the hardware ID of the board. At the moment, the voltage levels for seven EVB variants are defined. This commit adds a late_initcall to the board code that reads out the voltage and populates the hardware ID as environment variable. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210705160457.7346-1-michael.riesch@wolfvision.net Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: mxs: Replace license and copyright boilerplate by SPDX identifiersUwe Kleine-König2021-08-0922-283/+60
| | | | | | | | | | | Converts the files that licensecheck can determine to be licensed under GPL-2.0-only or GPL-2.0-or-later and also convert their copyright statements to SPDX. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Roland Hieber <rhi@pengutronix.de> Link: https://lore.barebox.org/20210730192802.1457345-1-u.kleine-koenig@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm/mvebu: sync barebox-arm-head.h to generic variantUwe Kleine-König2021-08-091-1/+24
| | | | | | | | | | | En passant this adds support for PBL_BREAK. While there is no 64 bit support available for mvebu, keeping the difference between arch/arm/mach-mvebu/include/mach/barebox-arm-head.h and arch/arm/include/asm/barebox-arm-head.h minimal is a good thing. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.barebox.org/20210730070001.1441742-1-u.kleine-koenig@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Revert "sandbox: hostfile: move initcall to earlier postcore level"Ahmad Fatoum2021-07-181-1/+1
| | | | | | | | | | | | | | The hostfile driver provides nvmem cells, which are consumed optionally by power and watchdog driver. Without deep probe there was no way to differentiate between a nvmem cell that has no provider at all and one with a provider that wasn't yet probed. The workaround is to move hostfile driver probe to an earlier initcall level. Now with deep probe support, this is no longer needed, thus revert commit 33be33ea617514df622a2a468b426e8a628c87e8. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210628064517.28636-8-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* sandbox: turn into deep probe platformAhmad Fatoum2021-07-181-2/+14
| | | | | | | | | With previous commits sorting out the few remaining issues holding sandbox back from using deep probe, we can now enable it. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210628064517.28636-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* sandbox: fix probe order dependency between watchdog and powerAhmad Fatoum2021-07-181-8/+6
| | | | | | | | | | | | | | | | With incoming changes to enable deep probe for sandbox, watchdog driver may be probed before power driver, which so far didn't happen. Because the watchdog driver writes the same NVMEM cell read by the power driver, the original value of the nvmem cell (used for $global.system.reset) will be lost. Work around this by writing the WDG reset reason only at first watchdog enable which is guaranteed to happen after power driver probe. We don't need to reset the nvmem cell on watchdog disable, because all other reset methods will already overwrite the cell with the correct value. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210628064517.28636-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* sandbox: power: set $global.system.reset=POR on poweroffAhmad Fatoum2021-07-181-3/+11
| | | | | | | | | | | | | | | | Now that the stickypage is a regular hostfile, it survives poweroff. This $global.system.reset will only be POR on first boot. For subsequent boots, the power driver must itself take care to write POR to the nvmem cell. While at it remove two minor issues: - src_offset is unused - len is used to store a length into. Its original value is unused Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210628064517.28636-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/zynqmp'Sascha Hauer2021-07-188-0/+195
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| * ARM: zynqmp: defconfig: enable more featuresMichael Tretter2021-06-251-0/+23
| | | | | | | | | | | | | | | | | | Enable network, file system, and PSCI support in the defconfig to get a Barebox with a useful feature set when building the ZynqMP defconfig. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20210624150054.1205422-7-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: zcu104: register update handlerMichael Tretter2021-06-252-0/+19
| | | | | | | | | | | | | | | | | | | | | | As the zcu104 stores the environment in the same partition as the barebox image, the partition is already mounted in ENV_MNT_DIR ("/boot"). Therefore, the update handler has to use the already existing mount point for the update. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20210624150054.1205422-6-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: add update handlerMichael Tretter2021-06-253-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | The ZynqMP boots from an SDHCI device by reading a boot.bin file from the FAT16/32 partition, which is the first partition in the MBR. The update handler copies a boot.bin image to this partition, which might be board specific. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20210624150054.1205422-5-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * dts: zcu104: add Barebox environmentMichael Tretter2021-06-251-0/+10
| | | | | | | | | | | | | | | | | | | | Use the same partition on the SD-card that is used by the ROM loader to find the BOOT.BIN (which contains the FSBL and Barebox) to store the Barebox environment. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20210624150054.1205422-4-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: set reset sourceMichael Tretter2021-06-252-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | The reset reason is available in the APB register set on the ZynqMP. Read the reset reason and set the reset source accordingly. There might be multiple bits set in the APB register. Use the MSB for determining the actual reset source. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20210624150054.1205422-2-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/rockchip'Sascha Hauer2021-07-1829-7/+6170
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| * | arm: rk3568-evb1: add support for Rockchip SARADCMichael Riesch2021-06-282-1/+17
| | | | | | | | | | | | | | | | | | Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.barebox.org/20210624160915.21897-3-michael.riesch@wolfvision.net Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: rockchip_v8_defconfig Disable ARC_EMAC driverSascha Hauer2021-06-281-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | The ARC_EMAC driver uses 32bit DMA pointers and is not ready for compilation on 64bit platforms. It is not needed in the rockchip_v8_defconfig, so disable it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Rockchip: rk3568 EVB: Add eMMC pinmuxSascha Hauer2021-06-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The eMMC relied on reset default pinmux. This doesn't work when not booting from eMMC, so add pinmux. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210625065722.26149-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM64: Implement mem*_*io()Sascha Hauer2021-06-282-1/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds memset_io(), memcpy_fromio() and memcpy_toio(). These have not been defined for ARM64 previously. The code is directly taken from the Kernel. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210622075413.6659-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Rockchip: rk3568 EVB: Add USB supportSascha Hauer2021-06-281-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | Enable the USB nodes for the ports found on the rk3568 EVB board. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210622064711.14058-5-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Rockchip: rk3568: Add USB nodesSascha Hauer2021-06-281-0/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | The RK3568 has two DWC3 cores and two EHCI/OHCI cores. Add these nodes to the dtsi file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210622064711.14058-4-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | Add rockchip_v8_defconfigSascha Hauer2021-06-281-0/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a defconfig for the arm64 based Rockchip SoCs, currently only RK3568 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210615141641.31577-12-s.hauer@pengutronix.de Link: https://lore.barebox.org/20210621092802.27275-12-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Rockchip: Add rk3568 evb board supportSascha Hauer2021-06-287-0/+582
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the rk3568 evb board. Tested features so far are: - 1st stage booting - Network - SD card - eMMC The dts files are based on the ones posted on the mailing lists, they should be rebased on the upstream files once they show up in barebox. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210615141641.31577-11-s.hauer@pengutronix.de Link: https://lore.barebox.org/20210621092802.27275-11-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: rockchip: Add bootm handler for RKNS imagesSascha Hauer2021-06-282-0/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rk3568 utilizes boot images starting with the magic 'RKNS'. Add a bootm handler for these to allow them to be chainloaded. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210615141641.31577-10-s.hauer@pengutronix.de Link: https://lore.barebox.org/20210621092802.27275-10-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Rockchip: Add rk3568 supportSascha Hauer2021-06-2811-3/+329
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds basic support for the Rockchip rk3568 SoC. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210615141641.31577-8-s.hauer@pengutronix.de Link: https://lore.barebox.org/20210621092802.27275-8-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Add atf common supportSascha Hauer2021-06-244-0/+247
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM trusted firmware has some common data structures passed to bl31. This patch imports the code supporting this taken from U-Boot. The defines and data structures are taken directly from U-Boot, the support code is heavily modified for the sake of readability. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210615141641.31577-9-s.hauer@pengutronix.de Link: https://lore.barebox.org/20210621092802.27275-9-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Rockchip: Add rk3568 dtsi filesSascha Hauer2021-06-213-0/+4340
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the rk3568 dtsi files, taken from the mailing list. They should hit upstream soon and can be removed then. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210615141641.31577-7-s.hauer@pengutronix.de Link: https://lore.barebox.org/20210621092802.27275-7-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Add relocate_to_adr_full()Sascha Hauer2021-06-212-3/+11
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | relocate_to_adr() currently relocates the PBL code to another address, but doesn't move the piggy data (compressed barebox image). This patch adds relocate_to_adr_full() which moves the full image including the piggy data. This is needed for upcoming Rockchip RK3568 support. Here we are started at address 0x0, but must move away from that address as this is where the ATF/OP-Tee binaries are expected to be loaded. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210615141641.31577-6-s.hauer@pengutronix.de Link: https://lore.barebox.org/20210621092802.27275-6-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/riscv'Sascha Hauer2021-07-1848-108/+2428
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| * | RISC-V: boards: beaglev: make it possible to use nmonAntony Pavlov2021-07-092-0/+3
| | | | | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Link: https://lore.barebox.org/20210708083035.40814-4-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: boards: erizo: make it possible to use nmonAntony Pavlov2021-07-091-0/+2
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210708083035.40814-3-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: make it possible to run nmon from PBL C codeAntony Pavlov2021-07-093-17/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After migrating to PBL we can't use nmon assembler macro in C code anymore. Some changes are introduced to invoke nmon from PBL C code: * use 'lla' macro instruction instead of 'la'; * don't touch the 'ra' register, use 'a2' instead; * add wrapper C function for nmon. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210708083035.40814-2-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: StarFive: add board support for BeagleV StarlightAhmad Fatoum2021-06-2414-0/+1458
| | | | | | | | | | | | | | | | | | | | | | | | | | | With the different drivers now in place, we have everything to start a barebox image. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-30-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | reset: add StarFive reset controller driverAhmad Fatoum2021-06-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The StarFive SoC has a single reset controller, which seems to control reset of all clocks and peripherals. It differs from the ones supported by the Linux reset-simple driver in that it has a dedicated status registers that needs to be polled to verify the reset has completed. Also special is that most resets (> 70) are synchronous. As the reset status poll would just time out without the clock, have the reset controller enable the clock as part of the reset. OS can decide later, which clocks to disable again. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-24-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | net: designware: fix non-1:1 mapped 64-bit systemsAhmad Fatoum2021-06-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/net/designware.c handles the older Designware < 4.x MAC IPs, which do not support DMA beyond 32-bit. They are still being integrated into SoCs with 64-bit CPUs like the StarFive JH7100, which additionally needs a non 1:1 mapping for coherent DMA. Fix the driver to support such usage. The driver still has the assumption that barebox core will only pass it 32-bit pointers. This is now made explicit by returning error codes when the DMA mask is violated. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-16-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | soc: starfive: add support for JH7100 incoherent interconnectAhmad Fatoum2021-06-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The preproduction JH7100 used in the BeagleV beta does not ensure cache coherence between CPU and some DMA masters like the Ethernet MAC. Fix this for streaming DMA mappings by implementing cache cleaning and discarding. The Flush64 primitive can be used for both as it will invalidate after flushing and not write-back clean lines. Coherent DMA mapping will be implemented using allocation from uncached SRAM in a follow-up commit. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-14-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | drivers: soc: sifive: add basic L2 cache controller driverAhmad Fatoum2021-06-242-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SiFive SoCs are cache coherent with respect to other DMA masters, so there is no need to explicitly flush cache lines. Incoming StarFive SoC uses SiFive CPU and L2 cache controller, but is cache-incoherent and thus needs the maintenance for DMA. Add a basic driver that exports the cache flush function for SoC-specific drivers to use. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-13-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: support incoherent I-CacheAhmad Fatoum2021-06-248-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SiFive SoCs have separate I-Caches that require self-modifying code like barebox' relocation and PBL extraction code to do cache maintenance. Implement sync_caches_for_execution and use it where appropriate. The underlying fence.i primitive is part of the Zifencei (load/store fence) ISA extension. As we can't be sure it's always available, the exception handler will skip over the instruction if the CPU trips over it. Alternatively, if CONFIG_HAS_CACHE=n, the instruction won't be emitted at all. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-12-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: add exception supportAhmad Fatoum2021-06-2412-0/+510
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add S- and M-Mode support for dumping registers when catching unexpected CPU exceptions. Load access faults when data_abort_mask is active will be skipped over. This allows outputting xxx when doing md /dev/mem for non-accessible space. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-11-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: dma: support multiple dma_alloc_coherent backendsAhmad Fatoum2021-06-243-35/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | StarFive JH7100 is incoherent between CPU and dma masters like GMAC. It has an uncached alias though similar to what we have on MIPS. StarFive JH7110 will fix this and be cache coherent like other SiFive SoCs. Support both by allowing driver to define their own dma_alloc_coherent implementations. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-10-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: socs: add Kconfig entry for StarFive JH7100Ahmad Fatoum2021-06-241-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The JH7100 is the StarFive SoC with SiFive CPUs in the pre-production BeagleV. Th JH7110 in later boards will be cache-coherent, but the JH7100 will need some workarounds. Add Kconfig symbols, so newly introduced symbols can depend on them. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-8-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: erizo: make it easier to reuse ns16550 debug_llAhmad Fatoum2021-06-241-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Incoming StarFive support also uses ns16550 compatibles as UART IP. Make reuse easier by making the two most likely parameters to change SoC-specific (base address and baud clock frequency) and move the rest behind the new CONFIG_DEBUG_LL_NS16550. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: S-Mode: propagate Hart IDAhmad Fatoum2021-06-247-10/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike other architectures we support, Linux must apparently be booted on all cores by the bootloader. To achieve this, the bootloaders running on the multiple cores synchronize via IPIs. We will get there eventually, but for now, let's restrict barebox to boot Linux on a single core. S-Mode firmware is passed hart (core) id in a0. This is propagated via the thread pointer register, which is unused by GCC and made available as: - cpuinfo output when running in S-Mode - $global.hartid - a0 when booting via bootm - /chosen/boot-hartid fixup: will come in handy when we gain EFI loading support - single /cpus/*/reg: All other CPU nodes are deleted via fixup For M-Mode, we can query hart id via CSR. It's unknown whether erizo supports it and we don't yet have exception support to handle it not being available, so changes are only done for S-Mode for now. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: cpuinfo: return some output for non-SBI systems as wellAhmad Fatoum2021-06-212-22/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If barebox managed to actually execute the cpuinfo command, it probably means that it's assumption which instructon set is being used and whether it runs in machine or supervisor mode is correct. Add that output to cpuinfo, so it shows at least something for non-SBI configurations. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-5-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: extend multi-image to support both S- and M-ModeAhmad Fatoum2021-06-2112-28/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can't currently mix S-Mode and M-Mode images in the same build and there's no straight-forward way to determine which mode we are in. Move the decision on which mode barebox is targeted at out of Kconfig and into the PBL. PBL code can call either barebox_riscv_supervisor_entry or barebox_riscv_machine_entry to signal to barebox proper which mode it's running in. Currently the only user of this information is the RISC-V timer clocksource driver. Any new code that does IS_ENABLED(CONFIG_RISCV_SBI) or IS_ENABLED(CONFIG_RISCV_M_MODE) should also be adapted to use riscv_mode(). Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | RISC-V: virt: select only one timerAhmad Fatoum2021-06-211-1/+0
| |/ | | | | | | | | | | | | | | | | S-Mode should use the riscv timer, so no need to select CLINT timer for virt. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/nvmem'Sascha Hauer2021-07-1811-104/+140
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| * | sandbox: ship sample environmentAhmad Fatoum2021-07-039-70/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea of the stickypage was to have a 4K memory region persistent over resets. This region was implemented as mmap of a temporary hostfile, which was created on first barebox start and maintained over resets. Usability was a bit lacking however: - The temporary files weren't deleted - state always showed warnings and errors on first boot. The banner telling users to ignore this wasn't best user experience - In the same vein, the power driver had logic to handle a fresh (zeroed) stickypage and interpret that as POR boot We can avoid all that, by just shipping a default stickypage and referencing that from DT. Do that. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210629063730.7001-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-20 15:16:04 +0000