summaryrefslogtreecommitdiffstats
path: root/arch
Commit message (Collapse)AuthorAgeFilesLines
...
| * | | ARM: at91: microchip-ksz9477-evb: add debug_ll UARTAhmad Fatoum2019-10-141-2/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EVB has the dbgu TX on PB31. Pinmux and set up the UART on it when DEBUG_LL is enabled, so early barebox boot messages can be printed. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: import lowlevel dbgu UART init code from at91bootstrapAhmad Fatoum2019-10-141-1/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For use in PBL, import dbgu init code from: https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/at91_usart.c The brgr calculation at the beginning is a untangled version of the BAUDRATE macro from the usart.h header: #define BAUDRATE(mck, baud) \ (((((mck) * 10) / ((baud) * 16)) % 10) >= 5) ? \ (mck / (baud * 16) + 1) : ((mck) / (baud * 16)) Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: import lowlevel clock initialization from at91bootstrapAhmad Fatoum2019-10-145-4/+287
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For use by future at91 first stage bootloaders, this commit imports https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/pmc.c Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: use compressed DTB for AT91_MULTI_BOARDSAhmad Fatoum2019-10-144-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To offset the size increase by using multi-image have the DTBs be compressed. This reduces e.g. the microchip_ksz9477_evb_defconfig by about 22K from 244K to 222K. This will also come in handy when implementing first stage support later on. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: build for all SoCs when AT91_MULTI_BOARDS is selectedAhmad Fatoum2019-10-143-43/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the addition of 15afd9d25 ("ARM: at91: Add initial support for the EVB-KSZ9477 eval board"), we now have two multi-image capable boards supported, but users still have to choose a specific SoC, so they can't be selected at the same time. Fix this, by restricting the menu to the non-multi-image configurations, i.e. CONFIG_ARCH_* symbols become specific to non-multi-image. The multi-image configurations on the other hand directly select the CONFIG_SOC_* symbol they require. Existing CONFIG_ARCH_* usage is adjusted to align with the new usage. Eventually, we would want to have a at91_multi_defconfig along with this, but for now leave existing configs as is. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: don't define ARCH_BAREBOX_MAX_BARE_INIT_SIZE for multi-imageAhmad Fatoum2019-10-141-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since ed04a7c3 ("pbl multiimage: Allow to check image sizes"), we can now check sizes per entry point, so no need to a Kconfig symbol that applies to all boards for that. Thus drop the Kconfig symbol for multi-image, so per-entry-point max image sizes can follow in future. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: delete no-longer needed #ifdef guardsAhmad Fatoum2019-10-141-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | c16bcbc644 ("ARM: at91: remove unused defines") removed conflicting definitions from the headers, so we can include the headers and code that uses them unconditionally now. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: at91sam9x5ek: squelch new dtc warningAhmad Fatoum2019-10-141-12/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since v1.5.0, dtc has been applying a heuristic to detect spi busses. It erroneously thinks the spi node in at91sam9x5ek.dts defines a spi bus: ./arch/arm/dts/at91sam9x5ek.dts:25.9-29.7: Warning (spi_bus_bridge): /ahb/apb/pinctrl@fffff400/spi: incorrect #address-cells for SPI bus ./arch/arm/dts/at91sam9x5ek.dts:25.9-29.7: Warning (spi_bus_bridge): /ahb/apb/pinctrl@fffff400/spi: incorrect #size-cells for SPI bus ./arch/arm/dts/at91sam9x5ek.dtb: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge' Avoid this by renaming the node. While at it move the node to top-level to reduce indentation. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | pinctrl: add gpio and pinctrl driver for sama5d2 PIO4Ahmad Fatoum2019-10-144-4/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sama5d2 features a GPIO and pin controller different than the one we support in barebox. The device tree bindings are different as well, so it makes sense to have a separate driver for it. Add the pin control and GPIO driver as well as some helpers usable from PBL, should we want to do pinmuxing that early. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: provide at91_mux_pio3_pin for use in first stageAhmad Fatoum2019-10-142-8/+40
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Low level init code may wish the ability to configure pins, e.g. for low level debug UART. The pinctrl-at91 driver already exports an at91_mux_pio3_pin function, but that one is only usable after driver probe. Instead, provide an at91_mux_pio3_pin function, which can be used at all times. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/arm'Sascha Hauer2019-10-1756-2275/+283
|\ \ \ | |/ / |/| |
| * | ARM: mmu: use client domain permissions to support ARMv7 eXecute NeverAhmad Fatoum2019-10-143-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM Architecture Reference Manual notes[1]: > When using the Short-descriptor translation table format, the XN > attribute is not checked for domains marked as Manager. > Therefore, the system must not include read-sensitive memory in > domains marked as Manager, because the XN bit does not prevent > speculative fetches from a Manager domain. To avoid speculative access to read-sensitive memory-mapped peripherals on ARMv7, let's use client domain permissions for all memory, so the XN bit (and also R/W bits) can function. This aligns us with what Linux is doing on ARMv7. This fixes cache corruption instances that had been observed on the i.MX6UL(L) when the instruction prefetcher speculates into memory following the end of a 512M SDRAM[2]. While this is not necessary to avoid speculative accesses on < ARMv7, we could probably have everything there in client domain as well, but due to lack of test coverage, we'll restrict the change to ARMv7. [1]: B3.7.2 - Execute-never restrictions on instruction fetching [2]: "Cache Corruption on MX6UL(L)": https://community.nxp.com/thread/511925 Fixes: 0198567c4 ("ARM: mmu: mark uncached regions as eXecute never on v7") Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: mmu: set R/W bits in ARMv7 translation tableAhmad Fatoum2019-10-141-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With barebox using the manager permissions for domain 0 that's used for all page table entries and directories, we never had the need so far to explicitly set R/W bits. We did so anyway for sections in the early MMU code, but later on in the normal MMU setup, we didn't do so consistently. In preparation for switching to DOMAIN_CLIENT for ARMv7, configure R/W everywhere in normal MMU code as well. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: cache-armv7: remove duplicate domain initializationAhmad Fatoum2019-10-141-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We already call set_domain each time we do __mmu_cache_on. Writing the DACR in the armv7 __mmu_cache_on is thus superfluous. Drop it. This changes existing behavior, whereas all 16 memory domains had the same access permissions set (manager) before, now only the first domain has. This is ok, as we only ever use domain 0 in barebox and on non-armv7, we don't bother with the other ones at all. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: cache-armv7: remove superfluous instructionAhmad Fatoum2019-10-141-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two tst r11, #0xf with nothing in between them that changes r11. This a left over from the kernel code that checks for VMSA twice, once to check if the page table should be setup and once to more to flush the TLB. We do the setup in the caller already, so the tst serves no useful purpose. Delete one. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: mmu: remove no longer accurate commentAhmad Fatoum2019-10-141-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This comment refers to the state of things prior to e3e54c644 ("ARM: mmu: Implement on-demand PTE allocation"). Since then, we no longer generate 2nd level page tables directly below. Remove it to avoid confusion. Cc: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: use system.h's get_cr() for cpuinfoAhmad Fatoum2019-10-141-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of open-coding the get_cr(), use the already available helper in <asm/system.h> same as we do for 64-bit ARMv8. The only difference is that the "memory" clobber is replaced by "cc". This is ok as we don't expect get_cr() to affect memory and because we do it elsewhere in barebox without a "memory" clobber already. While at it, move it out the #if/#else clause as the helper changes behavior depending on the same CONFIG option anyway. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: stm32mp: add bootm handler for imagesAhmad Fatoum2019-10-142-1/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STM32 images are preceded by a fixed-size 256 byte header, which is interpreted by the TF-A first stage bootloader and isn't executable as ARM code. To maintain the ability to network boot them, add a bootm handler that skips the header. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: aarch64: Re-implement most of barebox_arm_entry() in assemblyAndrey Smirnov2019-10-015-12/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GCC9 now produces the following warning: common.h:51:2: warning: listing the stack pointer register ‘sp’ in a clobber list is deprecated [-Wdeprecated] 51 | __asm__ __volatile__("mov sp, %0" | ^~~~~~~ common.h:51:2: note: the value of the stack pointer after an ‘asm’ statement must be the same as it was before the statement Stack pointer was added to clobber list in commit f9fc8254b2 ("ARM: Mark SP as being clobbered in arm_setup_stack()") to prevent GCC from generating code that would corrupt 'boarddata' pointer by trying to restore it from invalid stack frame. Interestingly enough, seemingly unrelated change in commit 64d95896cf ("ARM: aarch64: compile with general-regs-only") changed generated code such that adding SP to clobber list became no longer necessary. While the above can probably be a fix by itself, it seems a better and more future proof approach would be to address the problem at its root and re-implement offending startup sequence in assembly. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: remove now unused PBL codeSascha Hauer2019-10-018-108/+0
| | | | | | | | | | | | | | | | | | | | | Single PBL is now built as part of the multi PBL images, so drop the now unused single PBL code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Merge single pbl with multi pblSascha Hauer2019-10-015-111/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | So far we have two different implementations for PBL: One for a single PBL and one for multiple images. This patch implements the single PBL case as a special case of the multi PBL case. With this the single PBL becomes a multi PBL image with the entry point start_pbl. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: drop bultin DTBSascha Hauer2019-10-0112-36/+34
| | | | | | | | | | | | | | | | | | | | | | | | We can build multiple DTBs into the binary and board code can select which one to use. Drop the single builtin DTB and let the boards using it pass the correct one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Compile dtbs for lowlevel codeSascha Hauer2019-10-011-95/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | When no PBL is used then the DTB is used in the real barebox binary. We already have lwl-y for code which needs to be in PBL when existing and in the real barebox binary otherwise. Do the same for the DTBs and compile them with lwl-dtb-y. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: remove PBL_FORCE_PIGGYDATA_COPYSascha Hauer2019-09-231-13/+0
| | | | | | | | | | | | | | | | | | | | | This option is unused in the tree, remove it for now. If you need this option, let me know, we'll find another solution. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: NETX: remove architectureSascha Hauer2019-09-2319-1544/+0
| | | | | | | | | | | | | | | | | | | | | NETX support has been removed from the Kernel, so there's no point in supporting it in barebox any longer. Remove the architecture. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Remove tx53stk5_defconfigSascha Hauer2019-09-121-64/+0
| | | | | | | | | | | | | | | | | | | | | The TX53STK5 is covered by the imx_v7_defconfig, so remove the board specific config file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Remove tqma53_defconfigSascha Hauer2019-09-121-72/+0
| | | | | | | | | | | | | | | | | | | | | The TQMA53 is covered by the imx_v7_defconfig, so remove the board specific config file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Remove datamodul-edm-qmx6_defconfigSascha Hauer2019-09-121-88/+0
| | | | | | | | | | | | | | | | | | | | | The edm-qmx6 is covered by the imx_v7_defconfig, so remove the board specific config. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Remove vincell_defconfigSascha Hauer2019-09-121-110/+0
| |/ | | | | | | | | | | | | The vincell Board is covered by the imx_v7_defconfig. Remove the board specific config. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / ARM: aarch64: add image markers to linker scriptRouven Czerwinski2019-10-021-0/+4
|/ | | | | | | | | | | | The __image_start and __image_end marker are used by barebox to calculate the size of the barebox binary inside the RAM. Without the definitions barebox calculates its own size to zero, which works until a certain size is exceeded, than the PBL will place the binary lower into memory than the calculation inside barebox. Fix this by adding the appropriate image markers to the linker script. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2019-09-123-53/+72
|\
| * ARM: achilles: add bbu handlerSteffen Trumtrar2019-08-191-0/+26
| | | | | | | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Arria10: achilles: add named partitionsSteffen Trumtrar2019-08-191-0/+32
| | | | | | | | | | | | | | Add labels for the barebox1/2 and bitstream1/2 partitions. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Arria10: achilles: fix offsets in node namesSteffen Trumtrar2019-08-191-2/+2
| | | | | | | | | | | | | | | | The node names do not match the actual reg values. Fix this up. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: socfpga: fix xload on arria10Steffen Trumtrar2019-08-191-51/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Since the commit 5a1a5ed2537d7d12f851f3778707681d6c08d6e8 ARM: images: use piggydata the loading mechanism in the arria10 xload is neither functional nor needed. Now, barebox has/can be loaded like a normal image, so the filesize, that is written to the barebox header, can be evaluated. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/sandbox'Sascha Hauer2019-09-1210-9/+112
|\ \
| * | hwrng: add sandbox driver interface to host /dev/randomAhmad Fatoum2019-09-094-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux as well as other operating systems can provide /dev/random and /dev/urandom device to service userspace need for randomness. Add a driver to use /dev/random for blocking and /dev/urandom for non-blocking barebox random numbers. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | sandbox: dts: add example for barebox, hostfile backed stateAhmad Fatoum2019-09-091-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous commit now allows probing barebox,hostfile to be probed from device tree. Add a barebox state node that shows how to use it. It's not included by default, same as barebox-libftdi-example.dtsi in the same directory. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | sandbox: hostfile: allow probing from device treeAhmad Fatoum2019-09-093-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | When testing things like barebox state in sandbox, it's nice to be able to refer to a partition on a hostfile by phandle. Support this by checking for reading the barebox,filename property. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | sandbox: compile with symbol -fvisibility=hiddenAhmad Fatoum2019-08-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | barebox defines many symbols that are reserved for the C implementation. This collides with the libc, when building barebox for ARCH=sandbox. Specify -fvsibility-hidden, so libraries barebox is linked against don't inadvertently use barebox' functions. This fixes a heap corruption occurring when issuing fb0.enable=1 on my system, because X11 used strdup out of barebox, but free out of glibc[1]: binding file /lib/x86_64-linux-gnu/libX11.so.6 [0] to ./barebox [0]: normal symbol l `strdup' [GLIBC_2.2.5] [...] binding file /lib/x86_64-linux-gnu/libc.so.6 [0] to /lib/x86_64-linux-gnu/libc.so.6 [0]: normal symbol `free' [GLIBC_2.2.5] [1]: cf. CFLAGS +=-Dfree=barebox_free in arch/sandbox/Makefile Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | sandbox: redefine optarg and optind to avoid collisionsAhmad Fatoum2019-08-281-1/+2
| | | | | | | | | | | | | | | | | | | | | If we don't do this, the barebox main may fail to parse arguments. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | sandbox: remove unused ARCH_LINUX Kconfig symbolAhmad Fatoum2019-08-281-3/+0
| | | | | | | | | | | | | | | | | | | | | It's not referenced anywhere anymore, so drop it. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | sandbox: include header to provide missing prototypeAhmad Fatoum2019-08-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | sandbox_add_device lacks a prototype. Include the appropriate header to fix this. Signed-off-by: Ahmad Fatoum <ahmad@a3f.at> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/reset-source'Sascha Hauer2019-09-121-3/+1
|\ \ \
| * | | reset_source: drop reset_source_set_instance()Uwe Kleine-König2019-08-281-3/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The semantic of reset_source_set_instance() required a separate call to reset_source_set() (or reset_source_set_priority()) and checked right usage only using the type. Make the set of functions a bit easier to use by dropping reset_source_set_instance() and instead introduce a function that can set all relevant parameters (source, priority and instance) in one go. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/qemu'Sascha Hauer2019-09-126-1/+176
|\ \ \
| * | | ARM: i.MX: When generic DT image is enabled do not hardcode SoCSascha Hauer2019-08-191-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When only a single i.MX SoC is selected the cpu_is_mx?() macros expand to static 0 or 1. With the generic DT image enabled it could be though that the SoC is not a i.MX at all, so make sure that with the generic DT image enabled the cpu_is_mx?() macros always compare against __imx_cpu_type Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX: Do not hang() on unknown SoCsSascha Hauer2019-08-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic DT image built with CONFIG_ARCH_IMX has nothing really i.MX specific except that it has support for i.MX features. The DT image could be started with a non i.MX device tree which works as expected. imx_init() panics though when started with a non i.MX device tree. Remove the hang() so that we can just continue. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: Add generic device tree 2nd stage supportSascha Hauer2019-08-194-0/+166
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for building a barebox image that boots with the Linux ARM Kernel booting convention. Support for this image can be enabled in Kconfig. It picks up a device tree passed in r2. This new image helps for example with qemu. It can be started with: qemu-system-aarch64 -m 2G -M virt -kernel images/barebox-dt-2nd.img -cpu cortex-a57 -serial stdio or: qemu-system-arm -m 1G -M sabrelite -kernel images/barebox-dt-2nd.img -nographic -dtb arch/arm/dts/imx6q-sabrelite.dtb Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/omap'Sascha Hauer2019-09-124-1/+154
|\ \ \
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-24 14:03:13 +0000