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* Merge branch 'for-next/state'Sascha Hauer2017-06-142-0/+132
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| * state: Add working example dtsi fileSascha Hauer2017-05-232-0/+132
| | | | | | | | | | | | | | | | | | | | | | | | This adds a working example dtsi file for the state framework. It can be directly included by the Phytec phyFLEX i.MX6 board. The board has been chosen because it has a wide range of different storage devices suitable for state: SD, NAND, SPI NOR and i2c EEPROM. This example can be used for testing and also as a template for others to copy. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misd'Sascha Hauer2017-06-141-11/+42
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| * | sandbox: new --stdinout option to enable a bidirectional consoleAleksander Morgado2017-06-061-11/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to allowing read-only and write-only consoles with --stdin and --stdout, we now allow bidirectional read/write consoles with FIFO files. This is e.g. to allow doing RATP over the FIFO based consoles. Signed-off-by: Aleksander Morgado <aleksander@aleksander.es> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/mips'Sascha Hauer2017-06-143-8/+2
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| * | | MIPS: start.S: put entry code into the ".text_entry" sectionAntony Pavlov2017-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ".text_bare_init" section is not intended to be used for storing entry code. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: barebox.lds.S: put .text_entry contents after _stext and _textAntony Pavlov2017-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: barebox.lds.S: remove unused gotAntony Pavlov2017-05-081-3/+0
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: barebox.lds.S: drop unneeded '_start = .'Antony Pavlov2017-05-081-1/+0
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: start*.S: drop redundant .textAntony Pavlov2017-05-082-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `.text' is equivalent to the `.section .text' directive. The `.text' directive just before `.section ".text_bare_init"' or just before `.section ".text_head_entry"' is redundant so drop it. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | Merge branch 'for-next/imx'Sascha Hauer2017-06-1430-230/+682
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| * | | | ARM: i.MX6 Wandboard: enable Wandboard QuadAlexander Kurz2017-06-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the DT compatibility check to actually use the Wandboard Quad. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX6 Wandboard Quad: fix PBL UART MUXAlexander Kurz2017-06-131-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Three variants of the Wandboard exist: WBSOLO, WBDUAL and WBQUAD. For all variants, the external serial port is connected to UART1 via PAD_CSI0_DATA10 (TX) and PAD_CSI0_DATA11 (RX). Unfortunately, the IOMUX register adresses for this mux differ between i.MX6Q (WBQUAD) and others. Make the UART IOMUX for PBL compatible for WBQUAD. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX6 Wandboard: dont do MMDC Write Leveling CalibrationAlexander Kurz2017-06-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hardware requirements to perform a write leveling calibration are not fulfilled by the Wandboard modules. IMX6DQRM §44.11.6 "Write leveling Calibration" Note2 states that the first bit of each data byte group (D0, D8, ..., D56) from memory must be connected to the same data bus bit on the controller, which is not given on the Wandboard modules, resulting in unpredictable calib results and breaking the WBQUAD 2GiB SDRAM setup. Similar restrictions exist for the i.MX6SD. Remove this calibration and use the MPWLDECTRL defaults. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX6: add Technexion Pico Hobbit supportMichael Grzeschik2017-06-0712-0/+350
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the i.MX6UL Technexion Pico Hobbit. The board comes with different amounts of RAM. We create one image for the 256MB and one for the 512MB variant. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> --- v1 -> v2: - removed already prepared clock setup v2 -> v3: - added phy-reset-post-delay as the support is now available Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: phytec-som-imx6: remove needles enet refclk setupMichael Grzeschik2017-06-071-19/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All REF_CLK output setup now is generically prepared for imx6ul. The handling of the ENET_CLK_SEL (gpr[13]|gpr[14]) bits is not necessary, as 0 is their reset value. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX: setup ENET_TX_CLK_DIR in imx6_init for every imx6ulMichael Grzeschik2017-06-071-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We generically enable the output of ENET_TX_CLK. It will be output if ENET_REF_CLK is selected. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: imx6: gw54xx: use wdog1 for bareboxLucas Stach2017-06-011-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As Barebox isn't changing the external PMIC power rails the internal watchdog reset is fine for the Barebox reset purposes. Watchdog 2 is only usable on boards with revision E or later, as this on is incapable of executing an internal reset. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: imx6: gw54xx: fixup watchdog nodes on pre rev E boardsLucas Stach2017-06-011-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Older boards before revision E don't have the external watchdog signal wired up to the PMIC, so they must use watchdog 1, which is able to reset the SoC internally. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: imx6: gw54xx: add function to retrieve board revision from GSCLucas Stach2017-06-012-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This parses the board revision from the GSC EEPROm model string. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARCH: ARM: Add support for phytec-phycore-imx6ullStefan Riedmueller2017-05-176-148/+236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Created imx6ull devicetree to support Phytec phyCORE-i.MX6ULL. - 256 MB RAM - 128 MB NAND - 10/100 Mbit Ethernet Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX: Add i.MX6 ULL supportStefan Riedmueller2017-05-173-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX: HAB: update documentation of command sequence files (CSF)Marc Kleine-Budde2017-05-092-7/+13
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: mx6sx-sabresdb: the ethernet clocks get enabled by fec_imxMichael Grzeschik2017-05-081-26/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All necessary clocks get already enabled through the fec_imx driver configured by the devicetree. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: phytec-som-imx6: the ethernet clocks get enabled by fec_imxMichael Grzeschik2017-05-081-26/+1
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | All necessary clocks get already enabled through the fec_imx driver configured by the devicetree. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | Merge branch 'for-next/arm'Sascha Hauer2017-06-145-12/+29
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| * | | | ARM: mvebu: fix size mask for RAM windowUwe Kleine-König2017-06-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size field in the window control register occupies bits 31:16. So adapt ARMADA_370_XP_DDR_SIZE_MASK accordingly. This fixes detection of RAM chips smaller than 32 MiB and so probably doesn't affect any supported machine. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | arm: mach-omap: Change mountpoint of boot partitionsDaniel Schultz2017-05-171-11/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If using EMMC and SD as bootsources, mounting the boot partition of both devices to /boot makes trouble. Either the correct device is mounted to /boot or a remount of /boot has to be performed. To ensure this problem each MMCn bootsource will be mounted to his own path in /mnt/mmcN.0 Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Embedsky E9: Update environmentAndrey Panov2017-05-173-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrey Panov <rockford@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | Revert "globalvar: make globalvar functions more consistent"Sascha Hauer2017-06-135-8/+9
| |_|/ / |/| | | | | | | | | | | This reverts commit 1b4a05c9263ae26083526acfabdea1ef96531a1d.
* | | | sandbox: Fix registering file/fifo consolesSascha Hauer2017-06-011-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | barebox_register_console() uses xzalloc which requires the malloc pool to be initialized, so call it during the second option parsing when this is already done. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | sandbox: fix registering multiple consolesAleksander Morgado2017-06-013-7/+6
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consoles need to be registered with the "console" device name so that they are probed by the correct driver. The barebox_register_console() was already forcing this as it was overwriting the name that was being passed as argument, but it was failing to provide a unique id for each new console, so the underlying register_device() would just return an error when wanting to re-register a device with device name "console" and id 0. We remove the unused name parameter from barebox_register_console() as it is really nowhere used, and also specify DEVICE_ID_DYNAMIC as id, so that a new unique device id is given to each newly registered console device. Signed-off-by: Aleksander Morgado <aleksander@aleksander.es> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | ARM: socfpga: fix QSPI platform data initLucas Stach2017-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The struct member has been renamed, fix it. Fixes: fddf254b8b9a (mtd: spi-nor: cadence: change devicetree bindings to upstream) Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | ARM: i.MX50: Kindle-MX50 DT fixesAlexander Kurz2017-05-164-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * fix IOMUX for MAX14656 IRQ, it requires a pull-up to work * enable UART console for Model EY21 * set up IOMUX for EY21 GPIO lid-close hall sensor * remove IOMUX for non-existing EY21 GPIO keys * replace space indention with tabs Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | ARM: i.MX50: Amazon Kindle: Model EY21 compatibility checkAlexander Kurz2017-05-162-2/+3
| |/ |/| | | | | | | | | | | Extend the compatibility check for i.MX50 based kindles also on model EY21. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | PPC: request a consistent memory layoutJuergen Borleis2017-05-112-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Using the memory test command will crash barebox, because it tests the area where the stack is located for the PPC architecture. On PPC the stack is below the barebox binary. Below the stack the malloc area is located. Until this change some routines used the macros from 'memory_layout.h', some other calculated their values by their own - which resulted into an unrequested and unprotected stack area. Signed-off-by: Juergen Borleis <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: i.MX50: Amazon Kindle: Add missing compatibility checksSascha Hauer2017-05-113-2/+21
|/ | | | | | | | | Add the checks to prevent Kindle specific code on other machines. This also adds compatible strings for the Kindle machines as they currently lack them. Reported-by: Stefan Riedmüller <S.Riedmueller@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2017-05-0564-288/+4158
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| * ARM: socfpga: add arria10 defconfigSteffen Trumtrar2017-05-041-0/+89
| | | | | | | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: socfpga: add support for reflex achilles boardSteffen Trumtrar2017-05-048-0/+337
| | | | | | | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: socfpga: add arria10 supportSteffen Trumtrar2017-05-0321-199/+3423
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that is already supported in barebox. Both a the same in some parts, but totaly different in others. Most of the hardware blocks are the same in the SoC parts. The OCRAM is larger on the Arria10 and the SDRAM controller is different. The serial core only supports 32bit accesses (different to the 8bit accesses on the Cyclone5). As Arria10 has 256KB of OCRAM, it is possible to fit a larger barebox (and/or use PBL) instead of the two stage bootprocess used on the Cyclone5 and its 64KB OCRAM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: socfpga: make debug_ll configurableSteffen Trumtrar2017-05-031-25/+44
| | | | | | | | | | | | | | | | Allow configuring the serial port and clock rate instead of hardcoding it. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: socfpga: rename socfpga->cyclone5Steffen Trumtrar2017-05-0338-65/+266
| | | | | | | | | | | | | | | | Prepare the SoCFPGA code base for different system types (Arria10, Stratix10,...). Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/parameter-types'Sascha Hauer2017-05-059-16/+15
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| * | globalvar: make globalvar functions more consistentSascha Hauer2017-04-115-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to the device parameter functions also make the globalvar functions more consistent. This also adds support for readonly globalvars and changes several existing globalvars which should really be readonly to readonly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | param: make parameter functions more consistentSascha Hauer2017-04-113-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch creates a consitent set of device parameter functions. With this we have: dev_add_param_<type><access> "type" is one of: int32, uint32, int64, uint64, string, mac, ipv4, enum, bitmask The improvement here is that we now can exactly specify the width of the int type parameters and also correctly distinguish between signed and unsigned variables which means that a variable no longer ends up with INT_MAX when it's assigned -1. "access" can be empty for regular read/write parameter, "_ro" for readonly parameters which get their value from a variable pointer in the background or "_fixed" for parameters which are set to a fixed value (without a pointer in the background). Some more exotic types are not (yet) implemented, like dev_add_param_ip_ro. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: socfpga: change param_type struct nameSascha Hauer2017-04-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | We are going to introduce a "enum param_type" in barebox, so rename the struct type of the same name in the socfpga sequencer code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/omap'Sascha Hauer2017-05-051-0/+1
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| * | | arm: boards: Add MLO handler for EMMC devicesDaniel Schultz2017-05-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the barebox handler to flash MLOs on EMMC devices with 'barebox_update'. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | Merge branch 'for-next/mvebu'Sascha Hauer2017-05-051-0/+1
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