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* Merge branch 'for-next/misc'Sascha Hauer2022-01-193-1/+1655
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| * clk: rockchip: extend for rk3399 supportAhmad Fatoum2022-01-172-0/+1654
| * clk: change clk_get_num_parents into clk_hw_get_num_parentsAhmad Fatoum2022-01-141-1/+1
* | Revert "clk: handle CLK_OF_DECLARE in deep probe"Sascha Hauer2022-01-181-7/+1
* | clk: ignore of_device_ensure_probed error in clock lookupLucas Stach2022-01-181-4/+2
* | clk: fixed: record parent name in clk_register_fixed_rateAhmad Fatoum2022-01-051-0/+4
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* clk: bulk: improve error message on failure to getAhmad Fatoum2021-12-131-2/+2
* drivers: migrate "GPL-2.0+" license identifiers to SPDX 2.0Roland Hieber2021-11-221-1/+1
* drivers: migrate "GPL-2.0" license identifiers to SPDX 2.0Roland Hieber2021-11-2240-40/+40
* Merge branch 'for-next/spdx'Sascha Hauer2021-11-151-0/+1
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| * drivers: add missing SPDX-License-IdentifierAhmad Fatoum2021-11-011-0/+1
* | Merge branch 'for-next/rockchip'Sascha Hauer2021-11-151-1/+7
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| * | clk: handle CLK_OF_DECLARE in deep probeAhmad Fatoum2021-11-101-1/+7
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* / include: add dedicated header for printf/printkAhmad Fatoum2021-11-013-3/+3
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* clk: imx: add i.MX8MN (Nano) supportAhmad Fatoum2021-10-052-0/+560
* Merge branch 'for-next/zynqmp'Sascha Hauer2021-07-181-0/+3
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| * clk: zynqmp: do not enable already enabled clocksMichael Tretter2021-06-251-0/+3
* | Merge branch 'for-next/rockchip'Sascha Hauer2021-07-182-0/+56
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| * | clk: rockchip rk3568: Register softrst handlerSascha Hauer2021-06-281-0/+6
| * | clk: rockchip rk3568: Initialize clocksSascha Hauer2021-06-211-0/+28
| * | clk: Add clk_name_* functionsSascha Hauer2021-06-211-0/+22
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* | Merge branch 'for-next/riscv'Sascha Hauer2021-07-184-0/+431
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| * | clk: add initial StarFive clock supportAhmad Fatoum2021-06-244-0/+431
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* | Merge branch 'for-next/deep-probe'Sascha Hauer2021-07-181-0/+5
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| * | common: add initial barebox deep-probe supportMarco Felsch2021-06-251-0/+5
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* / clk: fix of clk set defaults when dev is a clk providerSascha Hauer2021-06-211-0/+2
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* Merge branch 'for-next/compiler-warnings'Sascha Hauer2021-06-162-4/+4
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| * clk: zynqmp: Fix wrong error checkSascha Hauer2021-05-181-1/+1
| * clk: tegra: Fix -Wtype-limits compiler warningSascha Hauer2021-05-181-3/+3
* | include: <io.h>: define (read|write)[bwlq]_relaxedAhmad Fatoum2021-06-111-3/+0
* | clk: rockchip: fix rk3568 cpll clk gate bitsPeter Geis2021-06-111-5/+5
* | clk: sifive: Fix missing conversion to struct clk_hwSascha Hauer2021-06-112-28/+32
* | clk: implement clk_bulk_get_optional()Sascha Hauer2021-06-101-3/+22
* | clk: bail out early when rate is already desired oneSascha Hauer2021-06-091-0/+3
* | clk: clk-composite: implement setting rate by reparentingSascha Hauer2021-06-091-3/+31
* | clk: clk-mux: implement setting rate by reparentingSascha Hauer2021-06-091-2/+80
* | clk: Rockchip: Add rk3568 clk supportSascha Hauer2021-06-092-0/+1707
* | clk: rockchip: Update to current LinuxSascha Hauer2021-06-0911-577/+2552
* | clk: implement set/get phaseSascha Hauer2021-06-081-0/+55
* | clk: implement CLK_SET_RATE_UNGATESascha Hauer2021-06-081-1/+11
* | clk: Rename CLK_GATE_INVERTED to CLK_GATE_SET_TO_DISABLESascha Hauer2021-06-083-12/+8
* | clk: Add CLK_GET_RATE_NOCACHESascha Hauer2021-06-081-1/+0
* | clk: Add Linux functions to register a muxSascha Hauer2021-06-071-0/+10
* | clk: Add Linux functions to register a gateSascha Hauer2021-06-071-0/+8
* | clk: Add Linux functions to register a fixed factor clockSascha Hauer2021-06-071-0/+7
* | clk: Add Linux functions to register a dividerSascha Hauer2021-06-071-0/+19
* | clk: Update fractional divider from LinuxSascha Hauer2021-06-071-33/+78
* | clk: move fixed_factor to include/linux/clk.hSascha Hauer2021-06-071-13/+1
* | clk: mux: Add ro opsSascha Hauer2021-06-071-0/+4
* | clk: divider: Make clk_mux_ops constSascha Hauer2021-06-071-1/+1
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-28 14:03:54 +0000