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* regulator: add SCMI regulator driverAhmad Fatoum2022-02-234-1/+382
| | | | | | | | Import the Linux v5.13 state of the SCMI clock regulator driver. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220220124736.3052502-16-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: add SCMI clock driverAhmad Fatoum2022-02-234-1/+377
| | | | | | | | Import the Linux v5.13 state of the SCMI clock protocol driver. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220220124736.3052502-15-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* reset: add SCMI supportAhmad Fatoum2022-02-234-1/+233
| | | | | | | | Import the Linux v5.13 state of the SCMI reset protocol driver. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220220124736.3052502-14-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: import Linux v5.13 SCMI supportAhmad Fatoum2022-02-239-0/+2359
| | | | | | | | | | | | | | | | | The ARM System Control and Management Interface (SCMI) is a standard way to offload handling of system resources like clocks, resets and power domain handling to the firmware. This should replace Silicon Provider specific conduits for new SoCs. Systems where this is already relevant: - STM32MP1: For trusted boot, the clock and reset controller are managed from secure world. This is not yet supported by barebox and must be disabled in TF-A - RK3568: At least the CPU clock is only controllable via SCMI - i.MX8X: Communication with the SCU occurs via SCMI Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220220124736.3052502-13-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: zynqmp-fpga: fix use of uninitialized addrMichael Tretter2022-02-031-7/+6
| | | | | | | | | | | | | | | | | | The bitstream loading API of the firmware is a bit clunky, as the driver needs to either pass the size of the bitstream or a pointer to the size of the bitstream. Commit 2f29ee311f1d ("firmware: zynqmp-fpga: do not use DMA coherent memory for bitstream") broke the loading by address, as the pointer to the bitstream size was set using the uninitialized DMA address. Fix it by determining the argument that is passed to the firmware after the bitstream has been mapped and always write the size of the bitstream at the end of the passed buffer. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20220202101054.3924339-1-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers: migrate "GPL-2.0" license identifiers to SPDX 2.0Roland Hieber2021-11-225-5/+5
| | | | | | | | | | "GPL-2.0-only" was introduced in SPDX 2.0, and the old identifier "GPL-2.0" is now considered deprecated; see <https://spdx.org/licenses>. Fixes: 28f4a6a4df76f0f1581d (2021-10-30, "drivers: add missing SPDX-License-Identifier") Signed-off-by: Roland Hieber <rhi@pengutronix.de> Link: https://lore.barebox.org/20211117113851.2022669-2-rhi@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers: add missing SPDX-License-IdentifierAhmad Fatoum2021-11-015-31/+5
| | | | | | | | | | | | | | | | | | | | This adds the suitable SPDX-License-Identifier to all files in drivers/ that previously lacked one. To aid manual inspection, following heuristics can be used: * No changes outside of comments/whitespace: git show -U0 HEAD | rg -v '^(@@|diff|index)|[-+]([-+]|//|#|[\s/]\*)' * -or-later come in pairs: git show --inter-hunk-context=19 HEAD | \ perl -0777 -F'/^@/gm' -ne 'for (@F) { @m = /later/g; print if @m & 1 }' Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20211030175632.2276077-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: zynqmp-fpga: do not use DMA coherent memory for bitstreamMichael Tretter2021-08-231-8/+15
| | | | | | | | | | | | | Trying to do unaligned access of coherent memory on AArch64 will lead to an abort. This can happen when the FPGA loader copies the bitstream to the temporary buffer for the transfer to the FPGA. Convert the driver to use regular memory for the temporary buffer to prevent the issue. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20210819081251.726840-4-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: zynqmp-fpga: avoid additional buffer for size argumentMichael Tretter2021-08-231-21/+16
| | | | | | | | | | | | | | | | | | | | There are two different APIs for loading an FPGA via the pmu-fw as indicated by the ZYNQMP_PM_FEATURE_SIZE_NOT_NEEDED feature flag. The pmu-fw expects as second argument either the size of the bitstream or a pointer to the size of the bitstream. The driver allocates a separate buffer for the size, which results in the allocation of a 4k page for storing a 32 bit value. Allocate some more memory for the bitstream and append the size of the bitstream at the end of the bitstream to avoid the additional memory allocation. Add a comment to explain the surprising size of the allocation. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20210819081251.726840-3-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: zynqmp-fpga: initialize flags at function startMichael Tretter2021-08-231-4/+1
| | | | | | | | | | The ZYNQMP_FPGA_BIT_ONLY_BIN flag is always set when programming the FPGA. Simplify the code by initializing the flags with ZYNQMP_FPGA_BIT_ONLY_BIN already set. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.barebox.org/20210819081251.726840-2-m.tretter@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: socfpga: set APPLYCFG after loading bitstreamSteffen Trumtrar2021-06-283-1/+42
| | | | | | | | | | | To make changes to the SDRAM controller effective, the APPLYCFG bit must be set after programming the bitstream to the FPGA. This has to be done without any SDRAM usage. Therefore copy the function to execute to the OCRAM and execute it from there. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Link: https://lore.barebox.org/20210625085944.11260-1-s.trumtrar@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: Fix device_node matchingSascha Hauer2021-06-253-0/+5
| | | | | | | | | | | | firmwaremgr_find_by_node() matches against the device node of the parent of the device associated to the handler. This is correct for the socfpga and zyncmp driver, but not for the altera_serial driver. Add a device_node argument to the handler which is set by the drivers to the correct device node and match against that. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210624085223.14616-9-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers: firmware: socfpga: remove bridges shutdownSteffen Trumtrar2021-06-221-9/+0
| | | | | | | | | The bridges are now handled via the bridges driver. There is no need to hardcode the memory writes anymore. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Link: https://lore.barebox.org/20210616063246.14900-9-s.trumtrar@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: import fpga-mgr.h from linuxSteffen Trumtrar2021-06-211-8/+1
| | | | | | | | | Instead of defining the fpga-mgr structure in the socfpga driver, import the fpga-mgr.h file from linux v4.13. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Link: https://lore.barebox.org/20210616063246.14900-5-s.trumtrar@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: socfpga: change function prefixesSteffen Trumtrar2021-06-211-29/+29
| | | | | | | | | Since there is now a fpgamgr framework in barebox, the function names are misleading. Change that to be SoCFPGA specific. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Link: https://lore.barebox.org/20210616063246.14900-4-s.trumtrar@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: fix unterminated of_device_id[] reported by CoccinelleAhmad Fatoum2020-10-022-0/+2
| | | | | | | | driver_d::of_compatible outght to point at a NULL-terminated array. Fix instances where this is not the case. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: zynqmp-fpga: drop example bin format headerMichael Tretter2019-12-111-59/+62
| | | | | | | | | | | | | | | | | | Avoid the example bitstream header to validate the bitstream that should be loaded into the FPGA. The header is mostly 0xFFFFFFFF with a few special values at a certain offsets and can be better described with the offsets and their magic values. As a drive by, this fixes/removes a broken check in the header validation. The != operator has a higher precedence than ?: and this check should have had parenthesis around the ?: expression: bin_header[i] != (byte_order == XILINX_BYTE_ORDER_BIT) ? bin_format[i] : __swab32(bin_format[i]) Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Reviewed-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: zynqmp-fpga: fix comparison between pointer and integerLucas Stach2019-12-021-1/+1
| | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: zynqmp-fpga: print Xilinx bitstream headerMichael Tretter2019-10-281-0/+51
| | | | | | | | | | | | | The bitstream header has 5 fields, that start with a char for the type. Four fields have a big-ending length and a null-terminated string for the design name, the part number, and the date and time of creation. The last field is a big-endian 32 bit unsigned int for the size of the bitstream. Print this info when loading the bitstream. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: zynqmp-fpga: introduce driver to load bitstream to FPGAThomas Haemmerle2019-10-283-0/+367
| | | | | | | | | The driver provides functionalities to check and load a bitstream to FPGA. A boolean parameter to check if FPGA is already programmed is added. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers: Introduce dev_set_name()Andrey Smirnov2018-10-181-1/+1
| | | | | | | | Introduce dev_set_name() in order to hide implementation details of setting device's name so it'd be easier to change it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: altera-serial: add support for Arria 10Bastian Stender2017-06-091-46/+113
| | | | | | | | | | | | | Make FPGA specific settings configurable (padding, spi bits per word, delays) and add Arria 10 support. The Arria 10 compatible is the same as in the kernel patch "fpga manager: Add altera-ps-spi driver for Altera FPGAs" (drivers/fpga/altera-ps-spi.c). The Arria 5 compatible works unchanged. This patch was tested with Arria 5 and Arria 10. Signed-off-by: Bastian Stender <bst@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: rename socfpga->cyclone5Steffen Trumtrar2017-05-031-4/+4
| | | | | | | | Prepare the SoCFPGA code base for different system types (Arria10, Stratix10,...). Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: altera-serial: simplify handling of optional gpioUwe Kleine-König2016-09-271-7/+5
| | | | | Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: altera-serial: Make the driver match the dt binding documentationUwe Kleine-König2016-09-271-7/+7
| | | | | Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* driver: replace dev_request_mem_region with dev_request_mem_resourceSascha Hauer2016-03-071-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dev_request_mem_region doesn't work properly one some SoCs on which PTR_ERR() values clash with valid return values from dev_request_mem_region. Replace them with dev_request_mem_resource where possible. This patch has been generated with the following semantic patch: // <smpl> @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) { ... - return PTR_ERR(io); -} + return PTR_ERR(iores); +} +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) - return PTR_ERR(io); -} + return PTR_ERR(iores); +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { - ret = PTR_ERR(io); +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) { + ret = PTR_ERR(iores); ... } +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) + return PTR_ERR(iores); +io = IOMEM(iores->start); ...+> } @@ identifier func; @@ func(...) { <+... struct resource *iores; -struct resource *iores; ...+> } // </smpl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* driver: Fix return check of dev_request_mem_regionSascha Hauer2016-02-231-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dev_request_mem_region returns an ERR_PTR, fix places which check for a NULL pointer instead. This patch has been generated with this semantic patch, written by me and improved by Andrey Smirnov: // <smpl> @@ expression e; expression e1; @@ e = dev_request_mem_region(...); ... -if (!e) - return e1; +if (IS_ERR(e)) + return PTR_ERR(e); @ rule1 @ expression e; @@ e = dev_request_mem_region(...); @@ expression rule1.e; identifier ret, label; constant errno; @@ if (!e) { ... ( - ret = -errno; + ret = PTR_ERR(e); ... goto label; | - return -errno; + return PTR_ERR(e); ) } @depends on rule1@ expression rule1.e; @@ - if (e == NULL) + if (IS_ERR(e)) { ... } // </smpl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
* firmware: socfpga: Add parameter "programmed" to fpgamgr driverTrent Piepho2015-11-111-11/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This boolean parameter tells you if the FPGA is programmed or not. It can be accessed from the shell as "$fpga.programmed". One could use this to not program the FPGA if it's already programmed. There is an annoying limitation of the way barebox puts parameters into the shell env: it requires they have no periods in the device name. It uses the first period to divide the variable name into a device and parameter name, which doesn't work correctly if the device name has a period in it. Since the names of any devices created from the OF device tree have a period in them, this is a problem. So what I did here was create a new device. Its parent will be the OF device for the fpgamgr and it will in turn be the parent of the firmware cdev. Previously the cdev's parent was the OF device. This device won't have period in the name and the parameter is attached to it. Even without the period limitation, doing this gives a nicer name "fpga.programmed" instead of "ff706000.fpgamgr.programmed". The fpgamgr code had a pointer to the OF device in its private state. I changed this to be a struct for the new "fpga" device, which is then used in all the places the former pointer was (nothing but dev_dbg, etc. calls). Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: socfpga: Fix a bug in fpgamgr_program_write_buf()Andrey Smirnov2015-04-231-1/+15
| | | | | | | | | Fix a bug in fpgamgr_program_write_buf() where .rbf file whose length is not a multiple of 4 would cause an integer overflow which would result in infinite loop. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: socfpga: Add necessary dependency to KconfigAndrey Smirnov2015-04-211-1/+1
| | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: altera: Make nSTAT GPIO optionalAndrey Smirnov2015-02-191-15/+44
| | | | | | | | | | By taking parts of the programming handshaking protocol on faith it is possible to make due with only two GPIO for programming Altera FPGAs. This is not a very advisable practice, but sometime unavoidable in GPIO constrained designs. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: altera serial: depend on GENERIC_GPIOSascha Hauer2014-11-281-0/+1
| | | | | | The driver needs gpio support, so depend on GENERIC_GPIO Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: altera-serial: fix printf messageLucas Stach2014-11-241-1/+1
| | | | | | | | | | Fixes: .../altera_serial.c:118:2: warning: too many arguments for format Also sz is of type size_t, so use proper format specifier. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: altera-serial: don't try to check void return valueLucas Stach2014-11-241-3/+1
| | | | | | | | Fixes: .../altera_serial.c:84:6: error: void value not ignored as it ought to be Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: altera-serial: depend on SPILucas Stach2014-11-241-0/+1
| | | | | | | This driver uses SPI bus functions. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* firmware: socfpga: depend on ARCH_SOCFPGALucas Stach2014-11-241-0/+1
| | | | | | | | This driver uses a lot of arch specific functionality and fails to build on anything but SOCFPGA. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Firmware: socfpga: Add SoCFPGA FPGA program supportSascha Hauer2014-09-093-0/+444
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Firmware: provide a handler to program Altera FPGAsJuergen Beisert2014-09-093-0/+327
This handler uses a regular SPI master and a few GPIOs to program an Altera FPGA in serial mode. Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-23 00:57:22 +0000