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* PCI: dwc: all: Split struct pcie_port into host-only and core structuresAndrey Smirnov2019-01-083-163/+196
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 442ec4c04d1235f8c664a74004dae54a7a574d18 Keep only the host-specific members in struct pcie_port and move the common members (i.e common to both host and endpoint) to struct dw_pcie. This is in preparation for adding endpoint mode support to designware driver. While at that also fix checkpatch warnings. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Jingoo Han <jingoohan1@gmail.com> CC: Richard Zhu <hongxing.zhu@nxp.com> CC: Lucas Stach <l.stach@pengutronix.de> CC: Murali Karicheri <m-karicheri2@ti.com> CC: Minghuan Lian <minghuan.Lian@freescale.com> CC: Mingkai Hu <mingkai.hu@freescale.com> CC: Roy Zang <tie-fei.zang@freescale.com> CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: Niklas Cassel <niklas.cassel@axis.com> CC: Jesper Nilsson <jesper.nilsson@axis.com> CC: Joao Pinto <Joao.Pinto@synopsys.com> CC: Zhou Wang <wangzhou1@hisilicon.com> CC: Gabriele Paoloni <gabriele.paoloni@huawei.com> CC: Stanimir Varbanov <svarbanov@mm-sol.com> CC: Pratyush Anand <pratyush.anand@gmail.com> For convenience sake, commit c0464062bfea9cd2ef6643d93429eafe8f6c2a4a PCI: dwc: Fix crashes seen due to missing assignments Fix the following crash, seen in dwc/pci-imx6. Unable to handle kernel NULL pointer dereference at virtual address 00000070 pgd = c0004000 [00000070] *pgd=00000000 Internal error: Oops: 805 [#1] SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.10.0-09686-g9e31489 #1 Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) task: cb850000 task.stack: cb84e000 PC is at imx6_pcie_probe+0x2f4/0x414 ... While at it, fix the same problem in various drivers instead of waiting for individual crash reports. The change in the imx6 driver was tested with qemu. The changes in other drivers are based on code inspection and have been compile tested only. Fixes: 442ec4c04d12 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures") Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> # designware-plat Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> was squashed into this one as well. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Remove LTSSM disable workaroundAndrey Smirnov2019-01-081-29/+28
| | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit a71280722eeba8f1afa51ad6656028dcb96e110b This causes CPU hangs when the system is reset by the watchdog, as the GPRs aren't cleared, but the clocks are back to disabled state. If the bootloader uses PCIe, it must take care to bring it down into a safe state, before passing control to the Linux kernel. This is the only way to get a properly operating system at all times and circumstances. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> LTSSM disable workaround still needs to be performed before passing control to Linux. However, in order to avoid the hang described above, we move it to imx6_pcie_remove() and apply it without relying on values in GPR. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Remove redundant "Link never came up" messageAndrey Smirnov2019-01-081-3/+1
| | | | | | | | | | | | | | | | | | | Port of a Linux commit caf3f562e1161a86bd48a4c4c33af89d3693c658 When a PCI card is not connected, the following messages are seen on mx6: imx6q-pcie 1ffc000.pcie: phy link never came up imx6q-pcie 1ffc000.pcie: Link never came up The first one comes from the pcie-designware.c core file, so remove the redundant one from the imx6 driver. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Add DT property for link gen, default to Gen1Andrey Smirnov2019-01-081-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit a5fcec480f25eb5444c0b71ecdf9b18b09236b95 Freescale has stated [1] that the LVDS clock source of the IMX6 does not pass the PCI Gen2 clock jitter test, therefore unless an external Gen2 compliant external clock source is present and supplied back to the IMX6 PCIe core via LVDS CLK1/CLK2 you can not claim Gen2 compliance. Add a DT property to specify Gen1 vs Gen2 and check this before allowing a Gen2 link. We default to Gen1 if the property is not present because at this time there are no IMX6 boards in mainline that 'input' a clock on LVDS CLK1/CLK2. In order to be Gen2 compliant on IMX6 you need to: - Have a Gen2 compliant external clock generator and route that clock back to either LVDS CLK1 or LVDS CLK2 as an input (see IMX6SX-SabreSD reference design). - Specify this clock in the PCIe node in the DT (i.e., IMX6QDL_CLK_LVDS1_IN or IMX6QDL_CLK_LVDS2_IN instead of IMX6QDL_CLK_LVDS1_GATE which configures it as a CLK output). [1] https://community.freescale.com/message/453209 Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Zhu Richard <Richard.Zhu@freescale.com> CC: Akshay Bhat <akshay.bhat@timesys.com> CC: Rob Herring <robh+dt@kernel.org> CC: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Factor out ref clock enableAndrey Smirnov2019-01-081-14/+29
| | | | | | | | | | | | | Port of a Linux commit 4d1821e729b5d2060ef8c9825af1dacc2182da38 Factor out ref clock enable to make it cleaner to add imx6sx support. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Christoph Fritz <chf.fritz@googlemail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Remove unused return valuesAndrey Smirnov2019-01-081-9/+4
| | | | | | | | | | | Port of a Linux commit 9ab021b6cf8b5bfc40ea9333c9b64b554fe01cd4 Remove unused return values. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Port error messages for imx6_pcie_deassert_core_reset()Andrey Smirnov2019-01-081-3/+10
| | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Reorder struct imx6_pcieAndrey Smirnov2019-01-081-1/+1
| | | | | | | | | | | | Port of a Linux commit 916bf1cc6528618197cdaf05ad42a9a82e9dea04 Reorder struct imx6_pcie to put generic fields first. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Use generic DesignWare accessorsAndrey Smirnov2019-01-081-66/+30
| | | | | | | | | | | | | Port of a Linux commit 2a6a85d5368e55e506abd7ca79f08131028bb0bc The dw_pcie_readl_rc() and dw_pcie_writel_rc() interfaces already add in pp->dbi_base, so use those instead of doing it ourselves in the imx6 driver. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Pass device-specific struct to internal functionsAndrey Smirnov2019-01-081-28/+25
| | | | | | | | | | | | | | | Port of a Linux commit e7d7705ace9494949863848ec77536d5a3287b0a Only interfaces used from outside the driver, e.g., those called by the DesignWare core, need to accept pointers to the generic struct pcie_port. Internal interfaces can accept pointers to the device-specific struct, which makes them more straightforward. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Pass struct imx6_pcie to PHY accessorsAndrey Smirnov2019-01-081-18/+23
| | | | | | | | | | | | Port of a Linux commit 8bad7f2fc3006d1752c426343ca77f1fbe61cf00 Pass the struct imx6_pcie pointer, not dbi_base address, to PHY accessors. This enables future simplifications. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Removed unused struct imx6_pcie.mem_baseAndrey Smirnov2019-01-081-1/+0
| | | | | | | | | | | | | | Port of a Linux commit 51c84709b8c4065fe83b84a487fe7822c2271e77 PCI: imx6: Removed unused struct imx6_pcie.mem_base Removed the unused struct imx6_pcie.mem_base member. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Add local struct device pointersAndrey Smirnov2019-01-081-7/+10
| | | | | | | | | | | | Port of a Linux commit 13957652f7242a8cb02ffb8c96f412f62c486ee1 Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init()Andrey Smirnov2019-01-081-5/+6
| | | | | | | | | | | | | | | Port of a Linux commit 40f67fb2c384fe12741aa35010d62bfe8c98286c No functional change. Get device pointer at the beginning of dw_pcie_host_init() instead of getting it all over dw_pcie_host_init(). This is in preparation for splitting struct pcie_port into host and core structures (once split pcie_port will not have device pointer). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: all: Rename cfg_read/cfg_write to read/writeAndrey Smirnov2019-01-082-8/+8
| | | | | | | | | | | | | | | | | No functional change. dw_pcie_cfg_read()/dw_pcie_cfg_write() doesn't do anything specific to access configuration space. It can be just renamed to dw_pcie_read()/dw_pcie_write() and used to read/write data to dbi space. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-By: Joao Pinto <jpinto@synopsys.com> CC: Jingoo Han <jingoohan1@gmail.com> CC: Murali Karicheri <m-karicheri2@ti.com> CC: Stanimir Varbanov <svarbanov@mm-sol.com> CC: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: designware: Move register defines to designware header fileAndrey Smirnov2019-01-083-73/+78
| | | | | | | | | | | | | | | | | Port of a Linux commmit b90dc392212d1153a12eea15cbc6eae352a3c989 No functional change. Move the register defines and other macros from pcie-designware.c to pcie-designware.h. This is in preparation to split the pcie-designware.c file into designware core file and host-specific file. While at that also fix a checkpatch warning. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-By: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Check for iATU unroll only on platforms that use ATUAndrey Smirnov2019-01-081-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit a782b5f986c3fa1cfa7f2b57941200c6a5809242 Previously we checked for iATU unroll support by reading PCIE_ATU_VIEWPORT even on platforms, e.g., Keystone, that do not have ATU ports. This can cause bad behavior such as asynchronous external aborts: OF: PCI: MEM 0x60000000..0x6fffffff -> 0x60000000 Unhandled fault: asynchronous external abort (0x1211) at 0x00000000 pgd = c0003000 [00000000] *pgd=80000800004003, *pmd=00000000 Internal error: : 1211 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.0-00009-g6ff59d2-dirty #7 Hardware name: Keystone task: eb878000 task.stack: eb866000 PC is at dw_pcie_setup_rc+0x24/0x380 LR is at ks_pcie_host_init+0x10/0x170 Move the dw_pcie_iatu_unroll_enabled() check so we only call it on platforms that do not use the ATU. These platforms supply their own ->rd_other_conf() and ->wr_other_conf() methods. [bhelgaas: changelog] Fixes: a0601a470537 ("PCI: designware: Add iATU Unroll feature") Fixes: 416379f9ebde ("PCI: designware: Check for iATU unroll support after initializing host") Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-By: Joao Pinto <jpinto@synopsys.com> CC: stable@vger.kernel.org # v4.9+ Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Swap order of dw_pcie_writel_unroll() reg/val argumentsAndrey Smirnov2019-01-081-15/+15
| | | | | | | | | | | | | Port of a Linux commit f5acb5c51de2c073ee5f80d868354113ce0227ee Swap order of dw_pcie_readl_unroll() arguments to match the "dev, pos, val" order used by pci_write_config_word() and other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Uninline register accessorsAndrey Smirnov2019-01-081-2/+2
| | | | | | | | | | | | Port of a Linux commit 3d469939bcdf044d9f370be4f6bf21436afea310 The register accessors are not performance critical and small enough that the compiler can inline them itself if it makes sense. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc()Andrey Smirnov2019-01-082-2/+4
| | | | | | | | | | | Export dw_pcie_readl_rc() and dw_pcie_writel_rc(). Many other drivers can use these instead of implementing their own versions. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Swap order of dw_pcie_writel_rc() reg/val argumentsAndrey Smirnov2019-01-082-24/+24
| | | | | | | | | | | | | Port of a Linux commit ad8802189426cf7b3a2ad0444f71981fb81312a8 Swap order of dw_pcie_writel_rc() arguments to match the "dev, pos, val" order used by pci_write_config_word() and other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfacesAndrey Smirnov2019-01-082-5/+4
| | | | | | | | | | | | | | | | | | | | Port of a Linux commit 7e00dfd0fbbb2fc276592613f76ded0b9a139a04 The struct pcie_host_ops.readl_rc() and .writel_rc() function pointers allow a driver to override the default DesignWare register accessors. Make the signature of the override functions the same as the default accessors. This makes the default dw_pcie_readl_rc() and the corresponding override more structurally similar: both will compute the final register address with "pp->dbi_base + reg". Previously dw_pcie_readl_rc() computed the address and passed it to the override. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll()Andrey Smirnov2019-01-081-8/+2
| | | | | | | | | | | | | | | Port of Linux commit a26e0108b61d6e65c151af720f2c4248a38f000d dw_pcie_readl_unroll() and dw_pcie_writel_unroll() duplicate what dw_pcie_readl_rc() and dw_pcie_writel_rc() already do, so call them directly. [bhelgaas: reworked into patch series] Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Rename dw_pcie_valid_config() to dw_pcie_valid_device()Andrey Smirnov2019-01-081-4/+4
| | | | | | | | | | | | | Port of a Linux commit 1034023606d0e971f4dee6f725e441b785a846b5 Rename dw_pcie_valid_config() to dw_pcie_valid_device() and use the result directly as a boolean value instead of testing against 0. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Exchange viewport of `MEMORYs' and `CFGs/IOs'Andrey Smirnov2019-01-081-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 68a0bfec72cb4f117198ae31df114dad4c5e405d When we have only two view ports in a DesignWare PCIe platform, iatu0 is used for both CFG and IO accesses. When CFGs are sent to peripherals (e.g., lspci), iatu0 frequently switches between CFG and IO. For such scenarios, a MEMORY might be sent as an IOs by mistake. Considering the following configurations: MEMORY -> BASE_ADDR: 0xb4100000, LIMIT: 0xb4100FFF, TYPE=mem CFG -> BASE_ADDR: 0xb4000000, LIMIT: 0xb4000FFF, TYPE=cfg IO -> BASE_ADDR: 0xFFFFFFFF, LIMIT: 0xFFFFFFFE, TYPE=io Suppose PCIe has just completed a CFG access. To switch back to IO, it sets the BASE_ADDR to 0xFFFFFFFF, LIMIT 0xFFFFFFFE and TYPE to IO. When another CFG comes, the BASE_ADDR is set to 0xb4000000 to switch to CFG. At this moment, a MEMORY access shows up, since it matches with iatu0 (due to 0xb4000000 <= MEMORY BASE_ADDR <= MEMORY LIMIT <= 0xFFFFFFF), it is treated as an IO access by mistake, then sent to perpheral. This patch fixes the problem by exchanging the assignments of `MEMORYs' and `CFGs/IOs', which assigning MEMORYs to iatu0, CFGs and IOs to iatu1. We can still have issues with IO transfer, however memory transfer is used predominantly therefore we are just minimizing the risk of failure. Actually, we can not do much when we have only two viewports. We can either not allow the less frequent IO transfers at all, or can live with a remote possibility of getting it corrupted. Signed-off-by: Dong Bo <dongbo4@huawei.com> [pratyush.anand@gmail.com: Modified commit log to capture remote risk] Signed-off-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2Andrey Smirnov2019-01-082-7/+20
| | | | | | | | | | | | | | | | Port of a Linux commit fe48cb8538421fbd16ecf8bf95829faf8d8c001e Most of the platforms have 3 or more viewports. For such platforms, We do not need to share viewports between IO and CFG. Assign viewport 2 to IO transactions in such cases. Tested-by: Dong Bo <dongbo4@huawei.com> Signed-off-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Check LTSSM training bit before deciding link is upAndrey Smirnov2019-01-081-2/+4
| | | | | | | | | | | | | | | | | | Port of a Linux commit 01c076732e8288485c22ef50f20949455a783ca9 The link may be up but still in link training. In this case, we can't think the link is up and operating correctly. Teach dw_pcie_link_up() to be aware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit. Also rewrite PCIE_PHY_DEBUG_R1_LINK_UP definition so that it's consistent with other macros. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Add iATU Unroll featureAndrey Smirnov2019-01-082-11/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit a0601a47053714eecec726aea5ebcd829f817497 Add support for the new iATU Unroll mechanism that will be used from Core version 4.80. The new Cores can support either iATU Unroll or the "old" iATU method, now called Legacy Mode. The driver is perfectly capable of performing well for both. [bhelgaas: split ATU enable timeout to separate patch] Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> To avoid breaking i.MX6 PCIE support commit 416379f9ebded501eda882e6af0a7aafc1866700 was squashed here as well PCI: designware: Check for iATU unroll support after initializing host dw_pcie_iatu_unroll_enabled() reads a dbi_base register. Reading any dbi_base register before pp->ops->host_init has been called causes "imprecise external abort" on platforms like ARTPEC-6, where the PCIe module is disabled at boot and first enabled in pp->ops->host_init. Move dw_pcie_iatu_unroll_enabled() to dw_pcie_setup_rc(), since it is after pp->ops->host_init, but before pp->iatu_unroll_enabled is actually used. Fixes: a0601a470537 ("PCI: designware: Add iATU Unroll feature") Tested-by: James Le Cuirot <chewi@gentoo.org> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Wait for iATU enableAndrey Smirnov2019-01-081-2/+13
| | | | | | | | | | | | | | Port of a Linux commit d8bbeb39fbf3ff06b6adae9d336f44bee4e3f3ec Add a loop with timeout to make sure the iATU is really enabled before subsequent config and I/O accesses. [bhelgaas: split to separate patch, use dev_err() instead of dev_dbg()] Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Move link wait definitions to .c fileAndrey Smirnov2019-01-082-4/+4
| | | | | | | | | | | | | | Port of a Linux commit c388de1c4f0e5da3e96b49efb0388e2a0d34e079 Move the link wait sleep definitions to the .c file as suggested by Jisheng Zhang in a previous patch. Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Return data directly from dw_pcie_readl_rc()Andrey Smirnov2019-01-082-11/+10
| | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 446fc23fb6f0cab15011d7daae856091856a65cc dw_pcie_readl_rc() reads a u32 value. Previously we stored that value in space supplied by the caller. Return the u32 value directly instead. This makes the calling code read better and makes it obvious that the caller need not initialize the storage. In the following example it isn't clear whether "val" is initialized before being used: dw_pcie_readl_rc(pp, PCI_COMMAND, &val); if (val & PCI_COMMAND_MEMORY) ... No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Remove incorrect RC memory base/limit configurationAndrey Smirnov2019-01-081-8/+0
| | | | | | | | | | | | | | | | | | | Port of a Linux commit a5cb903aef8c642e6f0f6810d46dacedf666b54a Currently dw_pcie_setup_rc() configures memory base and memory limit in the type1 configuration header for the root complex. In doing so it uses the CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr). This is wrong and it is useless since the configuration is overwritten later on when pci_bus_assign_resources() is called. Remove this configuration from dw_pcie_setup_rc(). Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc()Andrey Smirnov2019-01-081-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 7e57fd1444bf8f4ba9179f826ed6817c56b801d4 dw_pcie_host_init() looks up host bridge resources, ioremaps them, creates IRQ domains, and enumerates devices below the bridge. dw_pcie_setup_rc() programs the Root Complex registers. The Root Complex may lose power during suspend-to-RAM, and when we resume, we want to redo the latter but not the former. Move some Root Complex programming from dw_pcie_host_init() to dw_pcie_setup_rc() where it belongs. DesignWare-based drivers can call dw_pcie_setup_rc() in their resume paths. [Niklas Cassel <niklas.cassel@axis.com>: This change moves outbound ATU programming, which uses pp->mem_base, to dw_pcie_setup_rc(). Apply the dra7xx pp->mem_base update before calling dw_pcie_setup_rc().] [bhelgaas: changelog, fold in dra7xx fix from Niklas] Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Add default link up check if sub-driver doesn't overrideAndrey Smirnov2019-01-081-1/+9
| | | | | | | | | | | | | | | Port of a Linux commit dac29e6c5460d05774e3e8c4fdf4d6e7bd481fab Add a default DesignWare "link_up" test for use when a sub-driver doesn't supply its own pcie_host_ops.link_up() method. [bhelgaas: changelog, split into its own patch] Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Add generic dw_pcie_wait_for_link()Andrey Smirnov2019-01-083-29/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of Linux commit 886bc5ceb5cc3ad4b219502d72b277e3c3255a32 Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and spear13xx) had similar loops waiting for the link to come up. Add a generic dw_pcie_wait_for_link() for use by all these drivers so the waiting is done consistently, e.g., always using usleep_range() rather than mdelay() and using similar timeouts and retry counts. Note that this changes the Keystone link training/wait for link strategy, so we initiate link training, then wait longer for the link to come up before re-initiating link training. [bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c] Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> NOTE: For some reason, all of the changes to imx6_pcie_wait_for_link() made in 4d107d3b5a686b5834e533a00b73bf7b1cf59df7 are actually not present 886bc5ceb5cc3ad4b219502d72b277e3c3255a32. So there isn't really a kernel commit corresponding to removal of the large comment block or check for !(reg & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: imx6: Move link up check into imx6_pcie_wait_for_link()Andrey Smirnov2019-01-081-1/+19
| | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 4d107d3b5a686b5834e533a00b73bf7b1cf59df7 imx6_pcie_link_up() previously used usleep_range() to wait for the link to come up. Since it may be called while holding the config spinlock, the sleep causes a "BUG: scheduling while atomic" error. Instead of waiting for the link to come up in imx6_pcie_link_up(), do the waiting in imx6_pcie_wait_for_link(), where we're not holding a lock and sleeping is allowed. [bhelgaas: changelog, references to bugzilla and f95d3ae77191] Link: https://bugzilla.kernel.org/show_bug.cgi?id=100031 Fixes: f95d3ae77191 ("PCI: imx6: Wait for retraining") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Explain why we don't program ATU for some platformsAndrey Smirnov2019-01-081-0/+5
| | | | | | | | | | | | | | | | | | Port of a Linux commit dd193929d91e1b44b90f81509feeff10c94ddc4d Some platforms don't support ATU, e.g., pci-keystone.c. These platforms use their own address translation component rather than ATU, and they provide the rd_other_conf and wr_other_conf methods to program the translation component and perform the access. Add a comment to explain why we don't program the ATU for these platforms. [bhelgaas: changelog] Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Make config accessor override checking symmetricAndrey Smirnov2019-01-081-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 67de2dc34cc30d334cb66ab4f466e80f04d5b618 Drivers based on the DesignWare core can override the config read accessors by supplying rd_own_conf() and rd_other_conf() function pointers. dw_pcie_rd_conf() calls dw_pcie_rd_own_conf() (for accesses to the root bus) or dw_pcie_rd_other_conf(): dw_pcie_rd_conf dw_pcie_rd_own_conf # if on root bus dw_pcie_rd_other_conf # if not on root bus Previously we checked for rd_other_conf() directly in dw_pcie_rd_conf(), but we checked for rd_own_conf() in dw_pcie_rd_own_conf(). Check for rd_other_conf() in dw_pcie_rd_other_conf() to make this symmetric with the rd_own_conf() checking, and similarly for the write path. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Simplify control flowAndrey Smirnov2019-01-081-32/+21
| | | | | | | | | | | | | | | | Port of a Linux commit 116a489d78b30862a2dd04961d3ba98fe4704220 Return values immediately when possible to simplify the control flow. No functional change intended. Folded in unused variable removal as pointed out by Fabio Estevam <fabio.estevam@nxp.com>, Arnd Bergmann <arnd@arndb.de>, and Thierry Reding <thierry.reding@gmail.com>. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Ensure ATU is enabled before IO/conf space accessesAndrey Smirnov2019-01-081-0/+8
| | | | | | | | | | | | | | | | | Port of a Linux commit 17209dfb35a228e597a387bfc83b68093b247f78 Read back the ATU CR2 register to ensure ATU programming is effective before any subsequent I/O or config space accesses. Without this, PCI device enumeration is unreliable. [bhelgaas: changelog, comment] Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Make "num-lanes" an optional DT propertyAndrey Smirnov2019-01-081-5/+7
| | | | | | | | | | | | | | | | | | | Port of a Linux commit 907fce0902539ecde609e485eb2ecd7119a7a623 Currently "num-lanes" is read in dw_pcie_host_init(), but it is only used if we call dw_pcie_setup_rc() while bringing up the link. If the link has already been brought up by firmware, we need not call dw_pcie_setup_rc(), and "num-lanes" is unnecessary. Only complain about "num-lanes" if we actually need it and we didn't find a valid value. [bhelgaas: changelog] Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Require config accesses to be naturally alignedAndrey Smirnov2019-01-081-0/+8
| | | | | | | | | | | | | | | | Port of a Linux commit b6b18f589e1ddbfbc31f72ea7fb8a723a2d10058 Add sanity checks on "addr" input parameter in dw_pcie_cfg_read() and dw_pcie_cfg_write(). These checks make sure that accesses are aligned on their size, e.g., a 4-byte config access is aligned on a 4-byte boundary. [bhelgaas: changelog, set *val = 0 in failure case] Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Simplify dw_pcie_cfg_read/write() interfacesAndrey Smirnov2019-01-082-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 4c45852f494dab827291c656ee9e12f3f4ee64d6 Callers of dw_pcie_cfg_read() and dw_pcie_cfg_write() previously had to split the address into "addr" and "where". The callees assumed "addr" was 32-bit aligned (with zeros in the low two bits) and they used only the low two bits of "where". Accept the entire address in "addr" and drop the now-redundant "where" argument. As an example, this replaces this: int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) *val = readb(addr + (where & 1)); with this: int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) *val = readb(addr): [bhelgaas: changelog, split access size change to separate patch] Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> TODO: Fixup the pcie-designware.h Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Use exact access size in dw_pcie_cfg_read()Andrey Smirnov2019-01-081-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit c003ca99632e1783466f459033874a0e1e31457b dw_pcie_cfg_write() uses the exact 8-, 16-, or 32-bit access size requested, but dw_pcie_cfg_read() previously performed a 32-bit read and masked out the bits requested. Use the exact access size in dw_pcie_cfg_read(). For example, if we want an 8-bit read, use readb() instead of using readl() and masking out the 8 bits we need. This makes it symmetric with dw_pcie_cfg_write(). [bhelgaas: split into separate patch, set *val = 0 in failure case] Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> NOTE: Original Linux commit incorrectly handles the case of single byte read by doing else if (size == 1) *val = readb(addr + (where & 1)); instead of else if (size == 1) *val = readb(addr + (where & 3)); which would be symmetric with what's done in dw_pcie_cfg_write(). This was most likely overlooked since commit that follow change the signature of the function, remove 'where' as argument completely, inadvertenly fixing the problem. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASKAndrey Smirnov2019-01-081-1/+1
| | | | | | | | | | | | | | | | | | | Port of a Linux commit ed8b472df44af6dc4cb18e828dc9bb2d57f14b9e The value under PORT_LOGIC_LINK_WIDTH_MASK is 0x1, 0x2, 0x4, 0x8. In IP v4.2, bits [16:8] are defined for NUM_OF_LANES. But in IP v4.4, bits[12:8] are defined for NUM_OF_LANES, bits [16:13] are for other usages (bit 16 is AUTO_LANE_FLIP_CTRL_EN, bits [15:13] are PRE_DET_LANE). As there is no conflict about NUM_OF_LANES between v4.2 and v4.4, change the mask value to avoid future problems. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Use iATU0 for cfg and IO, iATU1 for MEMAndrey Smirnov2019-01-081-33/+46
| | | | | | | | | | | | | | | | | | | | Port of a Linux commit 2d91b491d5be13602a73be789bb8a3c28d06b7f2 Most transactions' type are cfg0 and MEM, so the current iATU usage is not balanced: iATU0 is hot while iATU1 is rarely used. Refactor the iATU usage so we use iATU0 for cfg and IO and iATU1 for MEM. This allocation idea comes from Minghuan Lian <Minghuan.Lian@freescale.com>: [bhelgaas: use link with Message-ID] Link: http://lkml.kernel.org/r/1429091315-31891-3-git-send-email-Minghuan.Lian@freescale.com Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Consolidate outbound iATU programming functionsAndrey Smirnov2019-01-081-78/+43
| | | | | | | | | | | | | | | | | | | Port of a Linux commit 63503c87f06e0f2c8c951cada81221c5500188d8 Currently, the outbound iATU programming functions are similar: the only difference is index, type, addr and size. Consolidate these functions into one. This saves about 1700 bytes in text: text data bss dec hex filename 9276 204 4 9484 250c pcie-designware.o-before 7532 204 4 7740 1e3c pcie-designware.o Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: desginware: Remove bogus prototypesAndrey Smirnov2019-01-081-2/+0
| | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers: Introduce dev_set_name()Andrey Smirnov2018-10-181-2/+1
| | | | | | | | Introduce dev_set_name() in order to hide implementation details of setting device's name so it'd be easier to change it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci_of_match_device: don't crash on MIPS MaltaAntony Pavlov2018-09-171-1/+1
| | | | | | | | In arch/mips/mach-malta/pci.c PCI controller is instantiated without dt and struct pci_controller parent field is NULL. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 20:27:13 +0000