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| * | PCI: designware: Add iATU Unroll featureAndrey Smirnov2019-01-082-11/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit a0601a47053714eecec726aea5ebcd829f817497 Add support for the new iATU Unroll mechanism that will be used from Core version 4.80. The new Cores can support either iATU Unroll or the "old" iATU method, now called Legacy Mode. The driver is perfectly capable of performing well for both. [bhelgaas: split ATU enable timeout to separate patch] Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> To avoid breaking i.MX6 PCIE support commit 416379f9ebded501eda882e6af0a7aafc1866700 was squashed here as well PCI: designware: Check for iATU unroll support after initializing host dw_pcie_iatu_unroll_enabled() reads a dbi_base register. Reading any dbi_base register before pp->ops->host_init has been called causes "imprecise external abort" on platforms like ARTPEC-6, where the PCIe module is disabled at boot and first enabled in pp->ops->host_init. Move dw_pcie_iatu_unroll_enabled() to dw_pcie_setup_rc(), since it is after pp->ops->host_init, but before pp->iatu_unroll_enabled is actually used. Fixes: a0601a470537 ("PCI: designware: Add iATU Unroll feature") Tested-by: James Le Cuirot <chewi@gentoo.org> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Wait for iATU enableAndrey Smirnov2019-01-081-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit d8bbeb39fbf3ff06b6adae9d336f44bee4e3f3ec Add a loop with timeout to make sure the iATU is really enabled before subsequent config and I/O accesses. [bhelgaas: split to separate patch, use dev_err() instead of dev_dbg()] Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Move link wait definitions to .c fileAndrey Smirnov2019-01-082-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit c388de1c4f0e5da3e96b49efb0388e2a0d34e079 Move the link wait sleep definitions to the .c file as suggested by Jisheng Zhang in a previous patch. Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Return data directly from dw_pcie_readl_rc()Andrey Smirnov2019-01-082-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 446fc23fb6f0cab15011d7daae856091856a65cc dw_pcie_readl_rc() reads a u32 value. Previously we stored that value in space supplied by the caller. Return the u32 value directly instead. This makes the calling code read better and makes it obvious that the caller need not initialize the storage. In the following example it isn't clear whether "val" is initialized before being used: dw_pcie_readl_rc(pp, PCI_COMMAND, &val); if (val & PCI_COMMAND_MEMORY) ... No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Remove incorrect RC memory base/limit configurationAndrey Smirnov2019-01-081-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit a5cb903aef8c642e6f0f6810d46dacedf666b54a Currently dw_pcie_setup_rc() configures memory base and memory limit in the type1 configuration header for the root complex. In doing so it uses the CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr). This is wrong and it is useless since the configuration is overwritten later on when pci_bus_assign_resources() is called. Remove this configuration from dw_pcie_setup_rc(). Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc()Andrey Smirnov2019-01-081-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 7e57fd1444bf8f4ba9179f826ed6817c56b801d4 dw_pcie_host_init() looks up host bridge resources, ioremaps them, creates IRQ domains, and enumerates devices below the bridge. dw_pcie_setup_rc() programs the Root Complex registers. The Root Complex may lose power during suspend-to-RAM, and when we resume, we want to redo the latter but not the former. Move some Root Complex programming from dw_pcie_host_init() to dw_pcie_setup_rc() where it belongs. DesignWare-based drivers can call dw_pcie_setup_rc() in their resume paths. [Niklas Cassel <niklas.cassel@axis.com>: This change moves outbound ATU programming, which uses pp->mem_base, to dw_pcie_setup_rc(). Apply the dra7xx pp->mem_base update before calling dw_pcie_setup_rc().] [bhelgaas: changelog, fold in dra7xx fix from Niklas] Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Add default link up check if sub-driver doesn't overrideAndrey Smirnov2019-01-081-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit dac29e6c5460d05774e3e8c4fdf4d6e7bd481fab Add a default DesignWare "link_up" test for use when a sub-driver doesn't supply its own pcie_host_ops.link_up() method. [bhelgaas: changelog, split into its own patch] Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Add generic dw_pcie_wait_for_link()Andrey Smirnov2019-01-083-29/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of Linux commit 886bc5ceb5cc3ad4b219502d72b277e3c3255a32 Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and spear13xx) had similar loops waiting for the link to come up. Add a generic dw_pcie_wait_for_link() for use by all these drivers so the waiting is done consistently, e.g., always using usleep_range() rather than mdelay() and using similar timeouts and retry counts. Note that this changes the Keystone link training/wait for link strategy, so we initiate link training, then wait longer for the link to come up before re-initiating link training. [bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c] Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> NOTE: For some reason, all of the changes to imx6_pcie_wait_for_link() made in 4d107d3b5a686b5834e533a00b73bf7b1cf59df7 are actually not present 886bc5ceb5cc3ad4b219502d72b277e3c3255a32. So there isn't really a kernel commit corresponding to removal of the large comment block or check for !(reg & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: imx6: Move link up check into imx6_pcie_wait_for_link()Andrey Smirnov2019-01-081-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 4d107d3b5a686b5834e533a00b73bf7b1cf59df7 imx6_pcie_link_up() previously used usleep_range() to wait for the link to come up. Since it may be called while holding the config spinlock, the sleep causes a "BUG: scheduling while atomic" error. Instead of waiting for the link to come up in imx6_pcie_link_up(), do the waiting in imx6_pcie_wait_for_link(), where we're not holding a lock and sleeping is allowed. [bhelgaas: changelog, references to bugzilla and f95d3ae77191] Link: https://bugzilla.kernel.org/show_bug.cgi?id=100031 Fixes: f95d3ae77191 ("PCI: imx6: Wait for retraining") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Explain why we don't program ATU for some platformsAndrey Smirnov2019-01-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit dd193929d91e1b44b90f81509feeff10c94ddc4d Some platforms don't support ATU, e.g., pci-keystone.c. These platforms use their own address translation component rather than ATU, and they provide the rd_other_conf and wr_other_conf methods to program the translation component and perform the access. Add a comment to explain why we don't program the ATU for these platforms. [bhelgaas: changelog] Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Make config accessor override checking symmetricAndrey Smirnov2019-01-081-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 67de2dc34cc30d334cb66ab4f466e80f04d5b618 Drivers based on the DesignWare core can override the config read accessors by supplying rd_own_conf() and rd_other_conf() function pointers. dw_pcie_rd_conf() calls dw_pcie_rd_own_conf() (for accesses to the root bus) or dw_pcie_rd_other_conf(): dw_pcie_rd_conf dw_pcie_rd_own_conf # if on root bus dw_pcie_rd_other_conf # if not on root bus Previously we checked for rd_other_conf() directly in dw_pcie_rd_conf(), but we checked for rd_own_conf() in dw_pcie_rd_own_conf(). Check for rd_other_conf() in dw_pcie_rd_other_conf() to make this symmetric with the rd_own_conf() checking, and similarly for the write path. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Simplify control flowAndrey Smirnov2019-01-081-32/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 116a489d78b30862a2dd04961d3ba98fe4704220 Return values immediately when possible to simplify the control flow. No functional change intended. Folded in unused variable removal as pointed out by Fabio Estevam <fabio.estevam@nxp.com>, Arnd Bergmann <arnd@arndb.de>, and Thierry Reding <thierry.reding@gmail.com>. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Ensure ATU is enabled before IO/conf space accessesAndrey Smirnov2019-01-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 17209dfb35a228e597a387bfc83b68093b247f78 Read back the ATU CR2 register to ensure ATU programming is effective before any subsequent I/O or config space accesses. Without this, PCI device enumeration is unreliable. [bhelgaas: changelog, comment] Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Make "num-lanes" an optional DT propertyAndrey Smirnov2019-01-081-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 907fce0902539ecde609e485eb2ecd7119a7a623 Currently "num-lanes" is read in dw_pcie_host_init(), but it is only used if we call dw_pcie_setup_rc() while bringing up the link. If the link has already been brought up by firmware, we need not call dw_pcie_setup_rc(), and "num-lanes" is unnecessary. Only complain about "num-lanes" if we actually need it and we didn't find a valid value. [bhelgaas: changelog] Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Require config accesses to be naturally alignedAndrey Smirnov2019-01-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit b6b18f589e1ddbfbc31f72ea7fb8a723a2d10058 Add sanity checks on "addr" input parameter in dw_pcie_cfg_read() and dw_pcie_cfg_write(). These checks make sure that accesses are aligned on their size, e.g., a 4-byte config access is aligned on a 4-byte boundary. [bhelgaas: changelog, set *val = 0 in failure case] Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Simplify dw_pcie_cfg_read/write() interfacesAndrey Smirnov2019-01-082-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 4c45852f494dab827291c656ee9e12f3f4ee64d6 Callers of dw_pcie_cfg_read() and dw_pcie_cfg_write() previously had to split the address into "addr" and "where". The callees assumed "addr" was 32-bit aligned (with zeros in the low two bits) and they used only the low two bits of "where". Accept the entire address in "addr" and drop the now-redundant "where" argument. As an example, this replaces this: int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) *val = readb(addr + (where & 1)); with this: int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) *val = readb(addr): [bhelgaas: changelog, split access size change to separate patch] Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> TODO: Fixup the pcie-designware.h Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Use exact access size in dw_pcie_cfg_read()Andrey Smirnov2019-01-081-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit c003ca99632e1783466f459033874a0e1e31457b dw_pcie_cfg_write() uses the exact 8-, 16-, or 32-bit access size requested, but dw_pcie_cfg_read() previously performed a 32-bit read and masked out the bits requested. Use the exact access size in dw_pcie_cfg_read(). For example, if we want an 8-bit read, use readb() instead of using readl() and masking out the 8 bits we need. This makes it symmetric with dw_pcie_cfg_write(). [bhelgaas: split into separate patch, set *val = 0 in failure case] Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> NOTE: Original Linux commit incorrectly handles the case of single byte read by doing else if (size == 1) *val = readb(addr + (where & 1)); instead of else if (size == 1) *val = readb(addr + (where & 3)); which would be symmetric with what's done in dw_pcie_cfg_write(). This was most likely overlooked since commit that follow change the signature of the function, remove 'where' as argument completely, inadvertenly fixing the problem. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASKAndrey Smirnov2019-01-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit ed8b472df44af6dc4cb18e828dc9bb2d57f14b9e The value under PORT_LOGIC_LINK_WIDTH_MASK is 0x1, 0x2, 0x4, 0x8. In IP v4.2, bits [16:8] are defined for NUM_OF_LANES. But in IP v4.4, bits[12:8] are defined for NUM_OF_LANES, bits [16:13] are for other usages (bit 16 is AUTO_LANE_FLIP_CTRL_EN, bits [15:13] are PRE_DET_LANE). As there is no conflict about NUM_OF_LANES between v4.2 and v4.4, change the mask value to avoid future problems. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Use iATU0 for cfg and IO, iATU1 for MEMAndrey Smirnov2019-01-081-33/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 2d91b491d5be13602a73be789bb8a3c28d06b7f2 Most transactions' type are cfg0 and MEM, so the current iATU usage is not balanced: iATU0 is hot while iATU1 is rarely used. Refactor the iATU usage so we use iATU0 for cfg and IO and iATU1 for MEM. This allocation idea comes from Minghuan Lian <Minghuan.Lian@freescale.com>: [bhelgaas: use link with Message-ID] Link: http://lkml.kernel.org/r/1429091315-31891-3-git-send-email-Minghuan.Lian@freescale.com Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: designware: Consolidate outbound iATU programming functionsAndrey Smirnov2019-01-081-78/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 63503c87f06e0f2c8c951cada81221c5500188d8 Currently, the outbound iATU programming functions are similar: the only difference is index, type, addr and size. Consolidate these functions into one. This saves about 1700 bytes in text: text data bss dec hex filename 9276 204 4 9484 250c pcie-designware.o-before 7532 204 4 7740 1e3c pcie-designware.o Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | PCI: desginware: Remove bogus prototypesAndrey Smirnov2019-01-081-2/+0
| |/ | | | | | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/net'Sascha Hauer2019-01-155-4/+354
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| * | macb: disable second priority queue for zynqmp gem supportThomas Hämmerle2019-01-092-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Provide descriptors for second priority rx and tx queues and disable the the queues if hardware is GEM. Otherwise the function macb_send() will run into a timeout. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | macb: fix memory leakage due to double allocation of rx_bufferThomas Hämmerle2019-01-091-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove memory allocation of rx buffer in function macb_init_rx_buffer_size, which caused a memory leak since it also is alocated in macb_probe(). Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | macb: fix check if hw is gemThomas Hämmerle2019-01-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix check for peripheral version in MACB_MID register to treat Xilinx ZynqMP as GEM. All MIDs >= 2 indicate a GEM not only MID == 2. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | macb: fix format specifiers for debug outputThomas Hämmerle2019-01-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fixes compiler warning "format '%d' expects argument of type 'int', but argument 4 has type 'size_t {aka long unsigned int}' [-Wformat=]". Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | dp83867: port from linuxThomas Hämmerle2019-01-093-0/+329
| |/ | | | | | | | | | | | | Port driver for TI DP83867 Gigabit Ethernet PHY from linux. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/mtd'Sascha Hauer2019-01-157-315/+418
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| * | mtd: core: Fix erase area alignment for non power of 2 erasesizeLadislav Michl2019-01-141-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Devices as AT45DB161 DataFlash uses non power of two page size (528) while present alignment algorithm relies on erasesize being power of 2. Fix that by introducing helper functions rounding to any multiply. Note that logic is sligthly changed to be consistent as ending address is moved forward to include also last byte meant to be erased while previous implementation moved it backward. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand: nand_base: Fix compile warning if CONFIG_MTD_WRITE is not enabledTeresa Remmet2018-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/mtd/nand/nand_base.c:337:12: warning: 'nand_default_block_markbad' defined but not used [-Wunused-function] Add __maybe_unused again to silence warning when CONFIG_MTD_WRITE is not enabled. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand: detect OOB size for Toshiba 24nm raw SLCLadislav Michl2018-12-171-0/+14
| | | | | | | | | | | | | | | | | | | | | Linux commit 60c673824561. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand: Kill cellinfoLadislav Michl2018-12-171-9/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | The only information used from cellinfo field is whenever flash is SLC or MLC, therefore eliminate it completely. This patch is based on Linux commit 7db906b79f69. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand: Kill the chip->scan_bbt() hookLadislav Michl2018-12-174-29/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux commit e80eba758151 adapted for Barebox: None of the existing drivers are overloading the ->scan_bbt() method, let's get rid of it and replace calls to ->scan_bbt() by nand_create_bbt() ones. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand_bbt: scan for next free bbt block if writing bbt failsLadislav Michl2018-12-141-6/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux commit 10ffd570f117 adapted for Barebox: If erasing or writing the BBT fails, we should mark the current BBT block as bad and use the BBT descriptor to scan for the next available unused block in the BBT. We should only return a failure if there isn't any space left. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand_bbt: Move BBT block selection logic out of write_bbt()Ladislav Michl2018-12-141-36/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux commit c3baf278d3bf adapted for Barebox: This clarifies the write_bbt() function by removing the write label and simplifying the error/exit path. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand_bbt: unify/fix error handling in nand_scan_bbt()Ladislav Michl2018-12-141-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux commit 83c59542d0af adapted for Barebox: Don't leak this->bbt, and return early if check_create() fails. It helps to have a single error path to avoid these problems. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand_bbt: make nand_scan_bbt() staticLadislav Michl2018-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Linux commit 17799359e7b adapted for Barebox: This implementation detail is no longer needed outside of nand_bbt.c. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand_bbt: handle error case for nand_create_badblock_pattern()Ladislav Michl2018-12-141-2/+6
| | | | | | | | | | | | | | | | | | | | | Linux commit abb9cf78e80a adapted for Barebox. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand_bbt: kill NAND_BBT_SCANALLPAGESLadislav Michl2018-12-142-35/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux commit 5961ad2cb4dd adapted for Barebox: Now that the last user of NAND_BBT_SCANALLPAGES has been removed, let's kill this peculiar BBT feature flag. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand: simplify nand_bch_init() usageLadislav Michl2018-12-142-16/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux commit a8c65d504e0b modified for Barebox: nand_bch_init() requires several arguments which could directly be deduced from the mtd device. Get rid of those useless parameters. nand_bch_init() is also requiring the caller to provide a proper eccbytes value, while this value could be deduced from the ecc.size and ecc.strength value. Fallback to eccbytes calculation when it is set to 0. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: atmel_nand: Add per board ECC setupLadislav Michl2018-12-141-0/+3
| | | | | | | | | | | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand: Request strength instead of bytes for soft BCHLadislav Michl2018-12-141-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux commits e0377cdebaf3 and 438320dd34a4 combined and adapted for Barebox: Previously, we requested that drivers pass ecc.size and ecc.bytes when using NAND_ECC_SOFT_BCH. However, a driver is likely to only know the ECC strength required for its NAND, so each driver would need to perform a strength-to-bytes calculation. Avoid duplicating this calculation in each driver by asking drivers to pass ecc.size and ecc.strength so that the strength-to-bytes calculation need only be implemented once. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand: remove NAND_BBT_SCANEMPTYLadislav Michl2018-12-142-29/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Relevant part of Linux commit dad2256269cb: NAND_BBT_SCANEMPTY is a strange, badly-supported option with omap as its single remaining user. NAND_BBT_SCANEMPTY was likely used by accident in omap2[1]. And anyway, omap2 doesn't scan the chip for bad blocks (courtesy of NAND_SKIP_BBTSCAN), and so its use of this option is irrelevant. This patch drops the NAND_BBT_SCANEMPTY option. [1] http://lists.infradead.org/pipermail/linux-mtd/2012-July/042902.html Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand: hide in-memory BBT implementation detailsLadislav Michl2018-12-142-64/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux commit b32843b772db adapted for Barebox: nand_base.c shouldn't have to know the implementation details of nand_bbt's in-memory BBT. Specifically, nand_base shouldn't perform the bit masking and shifting to isolate a BBT entry. Instead, just move some of the BBT code into a new nand_markbad_bbt() interface. This interface allows external users (i.e., nand_base) to mark a single block as bad in the BBT. Then nand_bbt will take care of modifying the in-memory BBT and updating the flash-based BBT (if applicable). Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand: remove multiplied-by-2 block logicLadislav Michl2018-12-141-48/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux commit b4d20d601f1e adapted for Barebox This patch removes any points where the block number is doubled/halved/otherwise-shifted, instead representing the block number in its most natural form: as the actual block number. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mtd: nand: refactor chip->block_markbad interfaceLadislav Michl2018-12-141-35/+52
| |/ | | | | | | | | | | | | | | | | | | | | | | Linux commit 5a0edb251ae9 adapted for Barebox: The chip->block_markbad pointer should really only be responsible for writing a bad block marker for new bad blocks. It should not take care of BBT-related functionality, nor should it handle bookkeeping of bad block stats. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/mmc'Sascha Hauer2019-01-156-22/+5
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| * | mci: mxs: Drop explicit devname setup codeAndrey Smirnov2018-12-101-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | Drop explicit devname setup code. Same setup will be done by mci_of_parse(). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mci: imx-esdhc: Drop explicit devname setup codeAndrey Smirnov2018-12-101-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | Drop explicit devname setup code. Same setup will be done by mci_of_parse(). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mci: omap_hsmmc: Drop explicit devname setup codeAndrey Smirnov2018-12-101-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | Drop explicit devname setup code. Same setup will be done by mci_of_parse(). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-21 14:24:51 +0000