| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Linux has phy helpers to access paged registers and to modify phy
registers. Add them to barebox for upcoming realtek phy support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Based on Linux commit 8636a1f9677db4f883f29a072f401303acfc2edd
This will be needed when you sync Kconfig with Linux 5.0 or later.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This patch fixes the parsing of the display timings options if
the range is specified (min/typ/max). Also fixed the double
release of memory in case of failure.
barebox 2018.12.0-00341-g23b28d33a-dirty #6 Fri Mar 15 09:20:25 MSK 2019
Board: Mega-Milas Informer i.MX6
detected i.MX6 Quad revision 1.2
i.MX reset reason POR (SRSR: 0x00000001)
mdio_bus: miibus0: probed
eth0: got preset MAC address: 50:2d:f4:07:71:0b
nand: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd3 (Samsung NAND 1GiB 3,3V 8-bit), 1024MiB, page size: 2048, OOB size: 64
Bad block table found at page 524224, version 0x01
Bad block table found at page 524160, version 0x01
m25p80 flash@00: n25q128a13 (16384 Kbytes)
imx-usb 2184000.usb@2184000: USB EHCI 1.00
imx-usb 2184200.usb@2184200: USB EHCI 1.00
imx-esdhc 2198000.usdhc@2198000: registered as mmc2
imx-ipuv3 2400000.ipu@2400000: IPUv3H probed
ERROR: /ldb/lvds-channel@0/display-timings/PH320240T: illegal timing specification in clock-frequency
ERROR: /ldb/lvds-channel@0/display-timings/PH320240T: error reading timing properties
ERROR: /ldb/lvds-channel@0: error in timing 1
ERROR: unable to handle NULL pointer dereference at address 0x00000013
pc : [<4fe05742>] lr : [<4fe05849>]
sp : 4ffefa80 ip : ffffffff fp : 2fefe84c
r10: 2ff656e8 r9 : 0000002c r8 : 2ff19630
r7 : 00000000 r6 : 0000004c r5 : 2ff65960 r4 : 00000007
r3 : 00000013 r2 : 00000000 r1 : 4fe87584 r0 : 2fefb460
Flags: nzcv IRQs off FIQs off Mode SVC_32
[<4fe05742>] (remove_free_block+0xe/0x3e) from [<4fe05849>] (block_locate_free+0x7f/0x88)
[<4fe05849>] (block_locate_free+0x7f/0x88) from [<4fe0599b>] (tlsf_malloc+0x17/0x32)
[<4fe0599b>] (tlsf_malloc+0x17/0x32) from [<4fe0559b>] (malloc+0x13/0x24)
[<4fe0559b>] (malloc+0x13/0x24) from [<4fe3a1f3>] (strdup+0x11/0x22)
[<4fe3a1f3>] (strdup+0x11/0x22) from [<4fe006f3>] (pr_puts+0x33/0x84)
[<4fe006f3>] (pr_puts+0x33/0x84) from [<4fe00803>] (dev_printf+0x6f/0x8c)
[<4fe00803>] (dev_printf+0x6f/0x8c) from [<00000000>] (0x0)
[<4fe54715>] (unwind_backtrace+0x1/0x60) from [<4fe00de1>] (panic+0x1d/0x34)
[<4fe00de1>] (panic+0x1d/0x34) from [<4fe5285d>] (do_exception+0xd/0x10)
[<4fe5285d>] (do_exception+0xd/0x10) from [<4fe528bd>] (do_data_abort+0x21/0x2c)
[<4fe528bd>] (do_data_abort+0x21/0x2c) from [<4fe524d4>] (do_abort_6+0x48/0x54)
### ERROR ### Please RESET the board ###
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Toggle GCTL.CORESOFTRESET before trying to access any of the block's
registers. Without this additional step, first read of DWC3_GHWPARAMS*
that follows results in assertion of GSTS.CSRTIMEOUT and IP block
stuck in a non-functional state.
Note that all above has only been observerd on i.MX8MQ (ZII Zest
board) for USB1 controller. USB2 doesn't seem to be affected by this.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds support for the clock controller found on Layerscape
SoCs. This is mostly an adoption of the corresponding Linux
driver. This is tested on the LS1046a SoC. Other ARM based Layerscape
SoCs should work aswell, support for the PowerPC based SoCs has
been removed.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds the Freescale ddr driver used on various PowerPC and
Layerscape SoCs. This is based on U-Boot-2019.01 but with many
adjustments:
- PowerPC support has been removed
- CPP #ifdeffery replaced with C
- No more global variables/functions expected from the driver,
configuration is passed by the board code which calls the driver
We already have the driver in the tree in an older version forked from
U-Boot-2013.04. This version lacks Layerscape support and many quirks
in the driver are PowerPC specific. Since the existing driver should
work on all known PowerPC and PowerPC is a dead end I decided not to
improve the existing driver and instead add a new Layerscape specific
driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Layerscape SoCs feature the same watchdog as the i.MX SoCs, but in big
endian mode. Add support for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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In preparation of adding big endian support in the next step.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds ethernet support for the Freecale Layerscape SoCs. The
architecture in these SoCs is called "Data Path Acceleration
Architecture" (DPAA). It is comprised of:
- The Queue Manager (QMan)
- Buffer Manager (BMan)
- Frame Manager (FMan)
- Multirate Ethernet Media Access Controller (mEMAC)
The code is based on the corresponding U-Boot driver enriched with
device tree parsing and proper device driver support.
Tested on LS1046a, should work on other SoCs aswell with some minor
quirks. SerDes support has been removed for now.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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15b64fd520 introduced the ESDHC_FLAG_CACHE_SNOOPING for layerscape
support, but didn't actually set it for layerscape. Add the new
flag to the layerscape SoC data.
Fixes: 15b64fd520 ("mci: imx-esdhc: Add layerscape support")
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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For the new "fixed-partitions" binding we ignore the partitions
subnode for creating reproducible names and set node to its parent.
To get the number of address cells we must call of_n_addr_cells()
before setting node to its parent though, not afterwards. With the
current behaviour we always get OF_ROOT_NODE_ADDR_CELLS_DEFAULT (=1).
This happens to work then the partitioned device is less than 4GiB
in size. On bigger devices #address-cells = <2> is chosen by the
mtd partition fixup code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reported-by: Bastian Krause <bst@pengutronix.de>
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With commit 3354adee3920 ("mci: imx-esdhc: Add bigendian register access
support") and commit 15b64fd520c2 ("mci: imx-esdhc: Add layerscape support")
two ESDHC_FLAGs got assigned to already existing values. This conflict made
the imx6sl usdhc appear to be big endian.
Resolve this conflict by assign the new flags to the next vacant values.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Initialize is_be, otherwise the value of is_be is undefined.
So it is possible that the i.MX8 will not boot because the bigendian
functions are used.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Our cyc_crc16() function is the same function as crc_itu_t() in the
Linux kernel. Import and use crc_itu_t() from the Kernel for
consistency.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The driver was missing a call to mci_of_parse() which fills in properties such
as "bus-width", "no-sd" into the mci_host struct.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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pinctrl driver needs to be initialized before mci driver on Raspberry Pi.
Otherwise the pinctrl device tree properties in the mci node are ignored.
pinctrl is initialized by coredevice_initcall(), so moving mci-bcm2835 to
device_initcall() ensures that it is initialized later.
There is no reason for mci-bcm2835 to use coredevice_initcall(). Other mci
drivers already use device_initcall().
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds hooks for the pin controller driver to the existing
bcm2835_set_function().
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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BCM2835 watchdog timeout can be set to maximum 15 seconds (0xffffff >> 16).
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Import a very abridged NVME implementation from Linux kernel in order
to be able to access NVME storage attached via PCIe.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Replace all of the generic PCI boilerplate with device_pci_driver().
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This function may be called repeatedly while establishing the link,
so printing a message each time a working link is found can add quite
a bit of noise. Tune those messages down to the debug level.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Drop dummy_probe() due to lack of users in the tree.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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make it properly represented by menuconfig
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Port of Linux patch https://patchwork.kernel.org/patch/10766235/
The HW can swap the USB differential-pair (D+/D-) for each port
separately. So the USB signals can be re-aligned with a misplaced
USB connector on the PCB.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Richard Leitner <richard.leitner@skidata.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Port Microchip USB251x USB hub driver from Linux. Needed by ZII's
i.MX8MQ boards.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Import DWC3 USB controller driver from Linux. This is a bare minimum
port of the code needed to support USB host functionality on
i.MX8MQ. No other use-case is explicitly supported.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Import a subset of clk_bulk API from Linux to support porting kernel
code that uses it.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Regardless of the value of CONFIG_HAVE_CLK, clk_put() implementation
is always a no-op. Move the definition to linux/clk.h and drop the
rest of the code implementing it.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Port i.MX8MQ USB PHY driver from Linux.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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In order to support PHY driver probe deferral change the code to
assume EPROBE_DEFER instead of ENODEV when requested PHY is missing
from phy_provider_list.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Make use of lo_hi_readq/writeq() to implement xhci_read/write_64()
helpers, same as it is done in the Linux kernel.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Simplify route string building loop by avoiding checking
top_dev->parent->descriptor->bDeviceClass twice.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Initialize TRT flag for xHCI >= 1.0, not just == 1.0. This is what
Linux xHCI driver does.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Simplfy xhci_submit_normal()'s logic a bit by using helper variables
and making sure that usb_pipein(pipe) is only called once.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Drop 'dma' field from struct xhci_hcd since it is not really used
anywhere.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Current TRB initialization code in xHCI driver is:
a) Somewhat inconsistent in endianness correctness: LE is insured
in some places whereas in some places it isn't
b) Somewhat inconsistent in how DMA buffer address is being
written: some places utilize xhci_write_64, whereas others just
assing cmd_trb field directly
c) A bit wasetful since in a number of codepaths where TRB is used
it is memset to zero first only to have 80+% of its fields
changed to something else right after.
To fix all of the above introduce xhci_init_event_cmd_trb(), that will
initialize all of the fileds to desired values only once as well as
taking care of endianness.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Convert xhci_submit_control() to use dma_(un)map_single(). These
functions both allow us to handle potential physical/virtual address
differences as well as allowing to drop a number of typecasts.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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