| Commit message (Collapse) | Author | Age | Files | Lines |
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Add support for the following ZII i.MX8MQ based boards:
- ZII i.MX8MQ RMB3
- ZII i.MX8MQ Zest
Most of the basic peripherals are supported by this patch. More
advanced features such as PCIe, display support, etc, are planned to
be added later.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Original patch from Uwe Kleine-König, I fixed the
review comments and the imxcfg file to use the udoo neo values.
I also tested the support on the udoo neo full board.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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pblx-* has been removed in 5a1a5ed253 ("ARM: images: use piggydata")
and using it (e.g. because a patchset was rebased) results in a non-obvious:
make[1]: *** No rule to make target 'images/*.pblx.*', \
needed by 'images/barebox-*.img'. Stop.
Avoid this by explicitly failing with an error message whenever pblx-y
or pblx- has been defined.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Now that we compile the compressed binary into the decompressor we
no longer need fix_size but can use the linker to fill in the image
size into the binary.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add support for the Xilinx Zynq Ultrascale+ MPSoC architecture (ZynqMP)
and the Xilinx ZCU104 board.
Barebox is booted as BL33 in EL-1 and expects that a BL2 (i.e. the FSBL)
already took care of initializing the RAM. Also for debug_ll, the UART
is expected to be already setup correctly. Thus, you have to add the
Barebox binary to a boot image as described in "Chapter 11: Boot and
Configuration" of "Zynq Ultrascale+ Device Technical Reference Manual".
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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"#alloc" is not working with MIPS compiler. The "a" variant
seems to be more generic and works with ARM and MIPS.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Based on the following Linux commits:
- 54a702f70589 ("kbuild: mark $(targets) as .SECONDARY and remove
.PRECIOUS markers")
- 8e9b61b293d9 ("kbuild: move .SECONDARY special target to
Kbuild.include")
This consolidates those two commits and adjusts commit log for barebox.
GNU Make automatically deletes intermediate files that are updated
in a chain of pattern rules.
Example 1) %.dtb.o <- %.dtb.S <- %.dtb <- %.dts
Example 2) %.o <- %.c <- %.c_shipped
arch/arm/crypto/Makefile marks such targets as .PRECIOUS to prevent Make
from deleting them, but the correct way is to use .SECONDARY.
.SECONDARY
Prerequisites of this special target are treated as intermediate
files but are never automatically deleted.
.PRECIOUS
When make is interrupted during execution, it may delete the target
file it is updating if the file was modified since make started.
If you mark the file as precious, make will never delete the file
if interrupted.
Both can avoid deletion of intermediate files, but the difference is
the behavior when Make is interrupted; .SECONDARY deletes the target,
but .PRECIOUS does not.
The use of .PRECIOUS is relatively rare since we do not want to keep
partially constructed (possibly corrupted) targets.
.SECONDARY with no prerequisites causes all targets to be treated as
secondary. This agrees the policy of Kbuild.
scripts/Kbuild.include seems a suitable place to add it because it is
included from almost all sub-makes.
I deleted 'SECONDARY' (no dot) from images/Makefile, which I guess
a typo.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This is a cumulative patch for the Digi ConnectCore CCMX51 SOM.
It includes:
- Switch board to devicetree probe.
- Add MMC update handler.
- Switch to multiimage support.
- Cleanup and optimize board code.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Some older pca100 boards were available with 64MB RAM. The chips
require a slightly different sdram controller initialization. Support
this by building bootloader images for both variants.
Signed-off-by: Florian Bäuerle <florian.baeuerle@allegion.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds support for the AM3517 based WAGO pfc200 SPS.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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piggy.o would be build for every time barebox was built
This had the sideeffect that the image(s) would
always be rebuilt despite no changes
Fix this by adding piggy.o to targets
and avoid an extra command in the rule to create .pblb files
The patch includes the removal of a stray assignment
Fixes: 5a1a5ed253 ("ARM: images: use piggydata")
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This brings back the image size written into the built images which got
lost in the conversion to using piggydata in the PBL images.
Fixes: 5a1a5ed253 ("ARM: images: use piggydata")
Reported-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
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The phyCORE-i.MX 6ULL now comes in a full featured (Y2 variant) and a
low cost (Y0 variant) version. The main difference for the barebox is
the missing second USB OTG port on the Y0 variant and the RAM configuration.
So to account for these differences the existing low cost version is
renamed and the full featured version added.
The results are following phyCORE-i.MX 6ULL modules:
phyCORE-i.MX 6ULL low cost:
- i.MX 6ULL Y0
- 256 MB RAM
- NAND
- Ethernet 10/100 MBits
- USB OTG
phyCORE-i.MX 6ULL full featured:
- i.MX 6ULL Y2
- 512 MB RAM
- NAND
- Ethernet 10/100 MBits
- USB OTG
- USB Host
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The way we assemble the multi images on ARM is rather complicated and
error prone. We currently cat the compressed barebox image behind the
PBL executable and need some magic to obtain the size of the payload and
also have to do tricks to reliably get a pointer to the compressed
image.
This patch switches over to compile the compressed payload into the PBL
image itself which has proven to work for the single PBL case and for
the ARM Linux Kernel aswell.
The goal is to unify the single PBL and the multi PBL cases together in
the future to get an easier startup path for ARM.
This patch has been tested on the i.MX53 QSB, i.MX53 Vincell, Beaglebone
black (both MLO and 2nd stage) and a Phytec phyFLEX i.MX6 board.
SoCFPGA Arria10 has also be changed slightly with this patch. We used to
generate a single image (barebox-socfpga-achilles.img) which was
used as xload image and full image. We now instead generate two images:
barebox-socfpga-achilles-xload.img and barebox-socfpga-achilles.img, the
former loaded by the ROM and the latter loaded by the xload image.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This patch removes the xload mechanism to configure SDRAM and instead
installs a DCD table. The DCD table has been generated from the FSL
DDR3 script aid Excel sheet (version 0.0.1). The calibration values
were taken from a calibration run with the barebox internal functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds basic support at the same feature level as the other
supported raspberry pi boards.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Roland Hieber <r.hieber@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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liteboard is a development board which uses liteSOM as its
base. liteSOM can't exist on its own, but is used as part
of other boards - it only contains processor and memory.
Hardware specification:
* liteSOM:
- i.MX6UL
- 256M or 512M DDR3 RAM
- eMMC (uSDHC2)
* Ethernet PHY
* USB host (usb_otg1)
* MicroSD slot (uSDHC1)
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The EVB-KSZ9477 is an evaluation board for the KSZ9477 ethernet switch.
This board is equipped with a atsama5d3 SoC with 256MiB of SDRAM, 256MiB
of NAND flash and a SD card slot.
For now only second stage booting is supported with AT91bootstrap as
first stage loader.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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mxsimage can now build unencrypted images with -u, so make use of it in
the Makefile. To keep the existing rules simple, name the generated
images *.mxsbsu instead of *.mxsbs.
Signed-off-by: Roland Hieber <r.hieber@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add .esimximg and .esimximg.dek targets for signed and encrypted
images and their corresponding DEKs. Also add rule to generate final
.img.dek files.
As an example, adding encrypted images for imx6ull_evk would look like
this:
FILE_barebox-nxp-imx6ull-evk-encrypted.img = start_nxp_imx6ull_evk.pblx.esimximg
image-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += barebox-nxp-imx6ull-evk-encrypted.img
FILE_barebox-nxp-imx6ull-evk-encrypted.img.dek = start_nxp_imx6ull_evk.pblx.esimximg.dek
image-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += barebox-nxp-imx6ull-evk-encrypted.img.dek
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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After being introduced 3 years ago this feature ended up being
"obsoleted by events" and project it was supposed to be a part of
winded down.
Revert this feature due to:
a) Lack of users
b) Existence of better way to make barebox load via SRAM as
intermediary step that does not require two separate images to be
built (.imx-sram-img)
This reverts commit 903c9477a08c5655161779ef4144886928ecc7d1.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Previously the FPGA was configured externally on the Achilles. On newer versions
this is changed and barebox has to configure the FPGA before the SDRAM can be
used.
If the FPGA is configured via JTAG or from an external memory, the *-bringup
version can be used.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Some Arria10 boards don't have the FPGA programmed externally.
Instead barebox needs to do that. As the Arria10 has the SDRAM
controller in the FPGA, the first thing we need to do is,
configure the FPGA before the SDRAM can even be used.
It works like this:
1. boot ROM fetches the PBL from MMC
2. read the MBR from MMC (this depends on the setup done by the boot ROM)
3. read the Bitstream from the MMC and program the FPGA
4. re-read the barebox image from MMC, this time with the full barebox
that is appended to the PBL
5. jump into the full barebox
Only supported boot device is eMMC.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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ZII RDU1 is a i.MX51 based, Babbagde board derivative supported by
upstream kernel. This commit add support for it to Barebox.
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add Phytec phyCORE-i.MX6 Solo:
- imx6dl-phytec-phycore-som-nand:
- 1GiB RAM on 1 Bank with 32Bit
- 100Mbit Ethernet
- NAND
- SD
- UART
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Add Phytec phyCORE-i.MX6 QuadPlus:
- imx6qp-phytec-phycore-som-nand:
- 1GiB RAM on 2 Banks with 64Bit
- 1000Mbit Ethernet
- NAND
- SD
- UART
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
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Add support for Advantech i.MX6 SOM named ROM-7421.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Looks like *.pblx was accidentally dropped from ignored files list and
now my "git status" is clobbered by every *.pblx image that is being
built (that's quite a lot for imx_v7_defconfig). Re-add original rule
to prevent that.
Fixes eed8a41c5 ("gitignore: ignore pblx.simximg files")
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The pblx-y variables for the TX53 have _imx53 twice in their names. With
this the names do not match the names in the FILE_* variables. This
results in the make system removing the pblx files as intermediate
files. Fix the names.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Karo is deploying their latest tx53 modules with samsung instead of
nanya ram. Unfortunatly the still keep the old revision for that
modules. We add this modules as an extra xx30 samsung variant.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Since nobody likes to use platformcode based machines any more, we also
switch this one to use dts based booting.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
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Add at91sam9263ek.dts to build.
Include mmc1 in at91sam9263ek.dts, as mmc1 is what the evaluation
kit uses for the SD card.
Add DT specific of_init
Adjust build to drop non-DT files from mach-at91
RomBOOT
>AT91Bootstrap 3.0.1
patch-0.8 64MB Ram
Load from SD-Card
Loading from SD-Card
Open: u-boot.bin
Loading from SD-Card - Success
barebox 2017.12.0-00036-gda46de29e #23 Sun Dec 31 09:15:39 CET 2017
Board: Atmel at91sam9263ek
gpio-at91 fffff200.gpio: AT91 gpio driver registered
gpio-at91 fffff400.gpio: AT91 gpio driver registered
gpio-at91 fffff600.gpio: AT91 gpio driver registered
gpio-at91 fffff800.gpio: AT91 gpio driver registered
gpio-at91 fffffa00.gpio: AT91 gpio driver registered
pinctrl-at91 pinctrl.2: AT91 pinctrl registered
AT91: Detected soc type: at91sam9263
AT91: Detected soc subtype: Unknown
mdio_bus: miibus0: probed
macb fffbc000.ethernet: Cadence MACB at 0xfffbc000
at91_udc fff78000.gadget: at91_udc version 3 May 2006
atmel_mci fff80000.mmc: version: 0x210
atmel_mci fff80000.mmc: registered as fff80000.mmc
atmel_mci fff84000.mmc: version: 0x210
atmel_mci fff84000.mmc: registered as fff84000.mmc
malloc space: 0x239fab00 -> 0x23dfaaff (size 4 MiB)
barebox-environment environment.6: probe failed: No such device
environment load /dev/env0: No such file or directory
Maybe you have to create the partition.
running /env/bin/init...
\e[?25h
Hit any key to stop autoboot: 3
barebox@Atmel at91sam9263ek:/ iomem
0x00000000 - 0xffffffff (size 0x00000000) iomem
0x00300000 - 0x00313fff (size 0x00014000) 300000.sram
0x00500000 - 0x00503fff (size 0x00004000) 500000.sram
0x00700000 - 0x00700fff (size 0x00001000) 700000.fb
0x20000000 - 0x23ffffff (size 0x04000000) ram0
0x239fab00 - 0x23dfaaff (size 0x00400000) malloc space
0x23dfab00 - 0x23dfffe2 (size 0x000054e3) board data
0x23e00000 - 0x23e53cc8 (size 0x00053cc9) barebox
0x23e53cc9 - 0x23e6404f (size 0x00010387) barebox data
0x23e64050 - 0x23e6754b (size 0x000034fc) bss
0x23fe4000 - 0x23fe7fff (size 0x00004000) ttb
0x23fe8000 - 0x23feffff (size 0x00008000) stack
0xfff78000 - 0xfff7bfff (size 0x00004000) fff78000.gadget
0xfff80000 - 0xfff805ff (size 0x00000600) fff80000.mmc
0xfff84000 - 0xfff845ff (size 0x00000600) fff84000.mmc
0xfff8c000 - 0xfff8c1ff (size 0x00000200) fff8c000.serial
0xfffbc000 - 0xfffbc0ff (size 0x00000100) fffbc000.ethernet
0xffffee00 - 0xffffefff (size 0x00000200) ffffee00.serial
0xfffff200 - 0xfffff3ff (size 0x00000200) fffff200.gpio
0xfffff400 - 0xfffff5ff (size 0x00000200) fffff400.gpio
0xfffff600 - 0xfffff7ff (size 0x00000200) fffff600.gpio
0xfffff800 - 0xfffff9ff (size 0x00000200) fffff800.gpio
0xfffffa00 - 0xfffffbff (size 0x00000200) fffffa00.gpio
0xfffffd30 - 0xfffffd3e (size 0x0000000f) fffffd30.timer
barebox@Atmel at91sam9263ek:/ devinfo
`-- global
`-- nv
`-- platform
`-- mem0
`-- 0x00000000-0x03ffffff ( 64 MiB): /dev/ram0
`-- 300000.sram
`-- 0x00000000-0x00013fff ( 80 KiB): /dev/sram0
`-- 500000.sram
`-- 0x00000000-0x00003fff ( 16 KiB): /dev/sram1
`-- ahb.0
`-- apb.1
`-- fffff000.interrupt-controller
`-- fffffc00.pmc
`-- ffffe200.ramc
`-- ffffe400.smc
`-- ffffe800.ramc
`-- ffffea00.smc
`-- ffffec00.matrix
`-- fffffd30.timer
`-- fff7c000.timer
`-- fffffd00.rstc
`-- fffffd10.shdwc
`-- pinctrl.2
`-- fffff200.gpio
`-- fffff400.gpio
`-- fffff600.gpio
`-- fffff800.gpio
`-- fffffa00.gpio
`-- ffffee00.serial
`-- cs0
`-- 0x00000000-0xffffffffffffffff ( 0 Bytes): /dev/cs0
`-- fff8c000.serial
`-- cs1
`-- 0x00000000-0xffffffffffffffff ( 0 Bytes): /dev/cs1
`-- fffbc000.ethernet
`-- miibus0
`-- eth0
`-- fff78000.gadget
`-- usbgadget
`-- fff80000.mmc
`-- mci0
`-- fff84000.mmc
`-- mci1
`-- fffffd40.watchdog
`-- fffa4000.spi
`-- fffac000.can
`-- 700000.fb
`-- a00000.ohci
`-- 10000000.ebi
`-- i2c-gpio-0.3
`-- leds.4
`-- gpio_keys.5
`-- cs2
`-- 0x00000000-0xffffffffffffffff ( 0 Bytes): /dev/cs2
`-- soc
`-- mem1
`-- 0x00000000-0xfffffffe ( 4 GiB): /dev/mem
`-- environment.6
`-- mdio_bus
`-- fs
`-- ramfs0
`-- devfs0
`-- net
`-- udc0
`-- fb0
`-- 0x00000000-0x000257ff ( 150 KiB): /dev/fb0
barebox@Atmel at91sam9263ek:/ drvinfo
Driver Device(s)
--------------------
syscon
at91-pit
fffffd30.timer
gpio-at91
fffff200.gpio
fffff400.gpio
fffff600.gpio
fffff800.gpio
fffffa00.gpio
pinctrl-at91
pinctrl.2
atmel_usart
ffffee00.serial
fff8c000.serial
ramfs
ramfs0
devfs
devfs0
fat
tftp
at91sam9-smc
Generic PHY
macb
fffbc000.ethernet
atmel_nand
cfi_flash
at91_udc
fff78000.gadget
atmel_mci
fff80000.mmc
fff84000.mmc
atmel_lcdfb
700000.fb
gpio-leds
leds.4
gpio_keys
gpio_keys.5
mmio-sram
300000.sram
500000.sram
mem
mem0
mem1
barebox-environment
Use 'devinfo DEVICE' for more information
barebox@Atmel at91sam9263ek:/ gpioinfo
GPIOs 0-31, chip fffff200.gpio:
dir val requested label
GPIO 0: unk hi false
GPIO 1: unk hi false
GPIO 2: in hi false
GPIO 3: unk hi false
GPIO 4: unk hi false
GPIO 5: unk hi false
GPIO 6: unk lo false
GPIO 7: unk hi false
GPIO 8: unk hi false
GPIO 9: unk hi false
GPIO 10: unk hi false
GPIO 11: unk hi false
GPIO 12: unk hi false
GPIO 13: in hi false
GPIO 14: in hi false
GPIO 15: in hi false
GPIO 16: in hi false
GPIO 17: in hi false
GPIO 18: in hi false
GPIO 19: in lo false
GPIO 20: in hi false
GPIO 21: in hi false
GPIO 22: in hi false
GPIO 23: in hi false
GPIO 24: in hi false
GPIO 25: in lo true udc_vbus
GPIO 26: unk hi false
GPIO 27: unk hi false
GPIO 28: unk hi false
GPIO 29: unk hi false
GPIO 30: in lo false
GPIO 31: in hi false
GPIOs 32-63, chip fffff400.gpio:
dir val requested label
GPIO 32: in hi false
GPIO 33: in hi false
GPIO 34: in hi false
GPIO 35: in hi false
GPIO 36: in hi false
GPIO 37: in hi false
GPIO 38: in hi false
GPIO 39: out hi true d3
GPIO 40: in hi false
GPIO 41: unk hi false
GPIO 42: in hi false
GPIO 43: in hi false
GPIO 44: in hi false
GPIO 45: in hi false
GPIO 46: in hi false
GPIO 47: in hi false
GPIO 48: in hi false
GPIO 49: in hi false
GPIO 50: in hi false
GPIO 51: in hi false
GPIO 52: in hi false
GPIO 53: in hi false
GPIO 54: in hi false
GPIO 55: in hi false
GPIO 56: in hi false
GPIO 57: in hi false
GPIO 58: in hi false
GPIO 59: out lo active low PHY 50 MHz oscillator
GPIO 60: in hi false
GPIO 61: in hi false
GPIO 62: in hi false
GPIO 63: in hi false
GPIOs 64-95, chip fffff600.gpio:
dir val requested label
GPIO 64: in hi false
GPIO 65: unk hi false
GPIO 66: unk hi false
GPIO 67: unk hi false
GPIO 68: in hi true gpio_keys
GPIO 69: in hi true gpio_keys
GPIO 70: unk lo false
GPIO 71: unk lo false
GPIO 72: unk lo false
GPIO 73: unk lo false
GPIO 74: unk lo false
GPIO 75: unk lo false
GPIO 76: unk lo false
GPIO 77: in hi false
GPIO 78: unk lo false
GPIO 79: unk lo false
GPIO 80: unk lo false
GPIO 81: unk lo false
GPIO 82: unk lo false
GPIO 83: unk lo false
GPIO 84: in hi false
GPIO 85: in hi false
GPIO 86: unk lo false
GPIO 87: unk lo false
GPIO 88: unk lo false
GPIO 89: unk lo false
GPIO 90: unk lo false
GPIO 91: unk lo false
GPIO 92: in hi false
GPIO 93: in hi true d2
GPIO 94: unk hi false
GPIO 95: unk hi false
GPIOs 96-127, chip fffff800.gpio:
dir val requested label
GPIO 96: in hi false
GPIO 97: in hi false
GPIO 98: in hi false
GPIO 99: in hi false
GPIO 100: in hi false
GPIO 101: in hi false
GPIO 102: in hi false
GPIO 103: in hi false
GPIO 104: in hi false
GPIO 105: in hi false
GPIO 106: in hi false
GPIO 107: in hi false
GPIO 108: unk lo false
GPIO 109: unk lo false
GPIO 110: unk lo false
GPIO 111: in hi false
GPIO 112: unk lo false
GPIO 113: unk hi false
GPIO 114: unk hi false
GPIO 115: unk lo false
GPIO 116: unk hi false
GPIO 117: unk hi false
GPIO 118: unk hi false
GPIO 119: unk hi false
GPIO 120: unk lo false
GPIO 121: unk hi false
GPIO 122: unk hi false
GPIO 123: unk lo false
GPIO 124: unk hi false
GPIO 125: unk hi false
GPIO 126: unk hi false
GPIO 127: unk hi false
GPIOs 128-159, chip fffffa00.gpio:
dir val requested label
GPIO 128: in hi false
GPIO 129: in hi false
GPIO 130: in hi false
GPIO 131: in hi false
GPIO 132: in hi false
GPIO 133: in hi false
GPIO 134: in hi false
GPIO 135: in hi false
GPIO 136: in hi false
GPIO 137: in hi false
GPIO 138: in hi false
GPIO 139: in hi false
GPIO 140: in hi false
GPIO 141: in hi false
GPIO 142: in hi false
GPIO 143: in hi false
GPIO 144: in hi false
GPIO 145: in hi false
GPIO 146: in lo true mci_cd
GPIO 147: in hi false
GPIO 148: in hi false
GPIO 149: unk lo false
GPIO 150: in hi false
GPIO 151: unk lo false
GPIO 152: unk lo false
GPIO 153: unk lo false
GPIO 154: unk lo false
GPIO 155: unk lo false
GPIO 156: unk lo false
GPIO 157: unk lo false
GPIO 158: unk hi false
GPIO 159: in hi false
barebox@Atmel at91sam9263ek:/ clk_dump
slow_xtal (rate 32768, enabled)
prog0 (rate 32768, enabled)
pck0 (rate 32768, disabled)
prog1 (rate 32768, enabled)
pck1 (rate 32768, disabled)
prog2 (rate 32768, enabled)
pck2 (rate 32768, disabled)
prog3 (rate 32768, enabled)
pck3 (rate 32768, disabled)
main_xtal (rate 16367660, enabled)
main_osc (rate 16367660, enabled)
mainck (rate 16367660, enabled)
pllbck (rate 98205960, enabled)
usbck (rate 49102980, enabled)
uhpck (rate 49102980, disabled)
udpck (rate 49102980, disabled)
pllack (rate 204595750, enabled)
masterck (rate 102297875, enabled)
pioA_clk (rate 102297875, enabled)
pioB_clk (rate 102297875, enabled)
pioCDE_clk (rate 102297875, enabled)
usart0_clk (rate 102297875, enabled)
usart1_clk (rate 102297875, disabled)
usart2_clk (rate 102297875, disabled)
mci0_clk (rate 102297875, disabled)
mci1_clk (rate 102297875, disabled)
can_clk (rate 102297875, disabled)
twi0_clk (rate 102297875, disabled)
spi0_clk (rate 102297875, disabled)
spi1_clk (rate 102297875, disabled)
ssc0_clk (rate 102297875, disabled)
ssc1_clk (rate 102297875, disabled)
ac97_clk (rate 102297875, disabled)
tcb_clk (rate 102297875, disabled)
pwm_clk (rate 102297875, disabled)
macb0_clk (rate 102297875, enabled)
g2de_clk (rate 102297875, disabled)
udc_clk (rate 102297875, disabled)
isi_clk (rate 102297875, disabled)
lcd_clk (rate 102297875, enabled)
dma_clk (rate 102297875, disabled)
ohci_clk (rate 102297875, disabled)
barebox@Atmel at91sam9263ek:/ led
registered LEDs:
0 : name: d3 max_value: 1
1 : name: d2 max_value: 1
barebox@Atmel at91sam9263ek:/ led 1 1
barebox@Atmel at91sam9263ek:/ led 0 1
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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There is a problem in the data path between 1GB RAM devices and the
core, which leads to wrong read operations after DDR initialization
in soft resets. This needs more investigation, but until we didn't
found the problem, we will return to the origin MLO for 1GB RAM devices
with static RAM timings and without memory access.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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