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path: root/include/linux/clk.h
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* clk: Enable clk_bulk_* functions only with CONFIG_COMMON_CLKSascha Hauer2022-03-081-144/+149
* clk: add clock driver for stm32f4 and stm32f7Ahmad Fatoum2022-02-011-0/+5
* clk: gate: add clk_hw registration functionsAhmad Fatoum2022-02-011-0/+11
* clk: implement of_clk_add_hw_providerAhmad Fatoum2022-02-011-0/+13
* clk: mux: export clk_mux_round_rateAhmad Fatoum2022-02-011-0/+3
* clk: mux: add clk_hw registration functionsAhmad Fatoum2022-02-011-0/+27
* clk: define clk_hw_registerAhmad Fatoum2022-02-011-0/+5
* clk: clk-fixed: add clk_hw registration functionsAhmad Fatoum2022-02-011-0/+4
* clk: fixed-factor: add clk_hw registration functionsAhmad Fatoum2022-02-011-0/+4
* clk: divider: add clk_hw registration functionsAhmad Fatoum2022-02-011-0/+11
* clk: composite: add clk_hw registration functionsAhmad Fatoum2022-02-011-0/+8
* clk: Move clk_hw_get_num_parents out of ifdefSascha Hauer2022-02-011-5/+5
* clk: propagate error pointers in clk_hw_to_clk and clk_to_clk_hwAhmad Fatoum2022-01-141-2/+2
* clk: change clk_get_num_parents into clk_hw_get_num_parentsAhmad Fatoum2022-01-141-2/+2
* clk: Add clk_name_* functionsSascha Hauer2021-06-211-0/+4
* clk: implement clk_bulk_get_optional()Sascha Hauer2021-06-101-0/+20
* clk: implement set/get phaseSascha Hauer2021-06-081-0/+5
* clk: implement CLK_SET_RATE_UNGATESascha Hauer2021-06-081-0/+1
* clk: Rename CLK_GATE_INVERTED to CLK_GATE_SET_TO_DISABLESascha Hauer2021-06-081-1/+1
* clk: Add CLK_GET_RATE_NOCACHESascha Hauer2021-06-081-0/+1
* clk: Add Linux functions to register a muxSascha Hauer2021-06-071-0/+5
* clk: Add Linux functions to register a gateSascha Hauer2021-06-071-0/+4
* clk: Add Linux functions to register a fixed factor clockSascha Hauer2021-06-071-0/+3
* clk: Add Linux functions to register a dividerSascha Hauer2021-06-071-0/+9
* clk: Add lock to different clock typesSascha Hauer2021-06-071-0/+5
* clk: Update fractional divider from LinuxSascha Hauer2021-06-071-0/+44
* clk: move fixed_factor to include/linux/clk.hSascha Hauer2021-06-071-0/+15
* clk: mux: Add ro opsSascha Hauer2021-06-071-0/+1
* clk: divider: Make clk_mux_ops constSascha Hauer2021-06-071-1/+1
* clk: divider: Add ro opsSascha Hauer2021-06-071-0/+1
* clk: divider: Make clk_divider_ops constSascha Hauer2021-06-071-1/+1
* clk: introduce clk_register()Sascha Hauer2021-06-071-0/+2
* clk: introduce struct clk_hwSascha Hauer2021-06-071-19/+77
* clk: rename clk_register() to bclk_register()Sascha Hauer2021-06-071-1/+1
* clk: introduce clk init opSascha Hauer2021-06-071-0/+1
* clk: Add clk_bulk_[get|put]_all()Sascha Hauer2020-09-241-0/+46
* clk_dump command: Allow printing a single clockSascha Hauer2020-09-231-0/+1
* Merge branch 'for-next/misc'Sascha Hauer2020-07-271-5/+4
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| * treewide: Convert files covered by ARM copyright to SPDXUwe Kleine-König2020-07-141-5/+4
* | clk: sync of_clk_get_parent_name with upstreamAhmad Fatoum2020-06-231-1/+1
|/
* clk: add clk_unregister stubAhmad Fatoum2020-04-151-0/+4
* clk: implement clk_register_fixed_rateAhmad Fatoum2020-04-151-1/+8
* clk: divider: export clk_div_mask() helperMarcin Niestroj2019-07-041-0/+2
* clk: divider: Make generic for usage elsewhereMarcin Niestroj2019-07-021-0/+8
* clk: mux: Support CLK_SET_RATE_NO_REPARENT flagSascha Hauer2019-03-111-0/+1
* clk: mux: Support CLK_MUX_READ_ONLY flagSascha Hauer2019-03-111-0/+1
* clk: mux: Support mux specific flagsSascha Hauer2019-03-111-6/+8
* clk: divider: Support CLK_DIVIDER_READ_ONLY flagSascha Hauer2019-03-111-0/+1
* clk: divider: pass divider flagsSascha Hauer2019-03-111-6/+10
* clk: Support CLK_IS_CRITICAL flagSascha Hauer2019-03-111-0/+1
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