path: root/scripts/socfpga_mkimage.c
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* scripts: socfpga_mkimage: add size feature for PBL bareboxSteffen Trumtrar2018-08-081-2/+23
| | | | | | | | Add the switch 's' to fixup the image size into the barebox header. This is used by the Arria10 PBL code to know the complete image size. Signed-off-by: Steffen Trumtrar <> Signed-off-by: Sascha Hauer <>
* socfpga: Add support for V1 images to socfpga_mkimageTrent Piepho2016-08-181-34/+110
| | | | | | | | | | | | | | | | | | | | | | | Altera's SocFPGA Arria10 SoC uses a new image format, different from the one used on CycloneV. The formats are similar, with the header matching up to the point where the version field is 1 instead of 0. At that point the header fields diverge. The CRC and checksum use is the same between the two. This patch extends socfpga_mkimage to support generating the new format with a version command line option. The default will be V0 for CycloneV. The new format is, IMHO, not as good as the previous one. It requires the start location be after the header, while the V0 format would allow the start location to be before or after. Barebox boot images are designed to start from offset 0, which is before the header. To avoid modifying the common barebox start code specifically for Arria10, I instead add a trampoline instruction after the V1 header to jump to the real start location, wherever it might be. Signed-off-by: Trent Piepho <> Signed-off-by: Sascha Hauer <>
* socfpga: correct start vector when not using extra barebox headerTrent Piepho2016-05-231-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The barebox ARM image has a 0x50 byte header that consists of: Bytes 0x00 - 0x0a: Instruction(s) to jump to start of code Bytes 0x20 - 0x2f: Signature and some other data The rest of header is basically padding. On SocFPGA, the ROM bootloader expects the 2nd stage bootloader (barebox) to have a 0x40 byte header with the following fields: Bytes 0x40 - 0x4b: Signature and some other data Bytes 0x4c - 0x4f: Instruction to jump to start of code These two headers are compatible, as everything defined in the SocFPGA header is at a location that is padding the barebox header. socfpga_mkimage has two methods for creating a SocFPGA image. One method prepends an extra 512 byte header to the barebox image, which contains the SoCFPGA header described above. The start vector at 0x4c is hard coded to jump to offset 512, where the barebox header's start vector will be. socfpga_mkimage can also not prepend this additional header and instead modify the barebox header to be SoCFPGA compatible. But it only writes bytes 0x40-0x4b and not the start vector at 0x4c, leaving that word as padding. And so this image will not boot when the ROM bootloader runs it. This changes the SoCFPGA header creator to write a correct start vector for both methods. It will create a branch instruction at 0x4c that jumps to the start of the barebox image, whether it be at offset 0 or offset 512 (or any other location). This makes SoCFPGA images without the extra header bootable. Signed-off-by: Sascha Hauer <>
* socfpga_mkimage: Fix/clarify error messageSascha Hauer2015-07-081-2/+2
| | | | | | | | | The actual max_image_size may be smaller than the define MAX_IMAGE_SIZE due to the additional header needed, so print max_image_size in the error message. Also, when complaining about a too big image say how big the image actually is. Signed-off-by: Sascha Hauer <>
* scripts: Add Altera SoCFPGA mkimage supportSascha Hauer2013-09-231-0/+287
The Altera SoCFPGAs expect a simple header for their first stage loaders. This adds a tool to generate images for the SoCFPGAs. The header is either embedded into the image or optionally prepended to the image. In this case code is added to jump over the image header. Signed-off-by: Sascha Hauer <>