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#
# Board configuration file for the Zodiac RDU3 boards
#
interface ftdi
ftdi_vid_pid 0x0403 0x6011
ftdi_layout_init 0x0038 0x003b
ftdi_layout_signal nSRST -data 0x0010
ftdi_layout_signal LED -data 0x0020
# select JTAG
transport select jtag
reset_config srst_only srst_push_pull connect_deassert_srst
# set a slow default JTAG clock, can be overridden later
adapter_khz 1000
# delay after SRST goes inactive
adapter_nsrst_delay 70
# board has an i.MX8MQ with 4 Cortex-A53 cores
set CHIPNAME imx8mq
set CHIPCORES 4
# source SoC configuration
source [find target/imx8m.cfg]
source [find mem_helper.tcl]
proc ddr_init { } {
echo "Bootstrap: Initializing DDR"
#
# We use the same start address as is configured in our i.MX boot
# header (address originally taken from U-Boot).
#
set IMX8MQ_TCM_BASE_ADDR 0x007e1000
set IMX8MQ_TCM_MAX_SIZE 0x3f000
#
# Header word at offset 0x28 is not used on AArch64 and is just
# filled with placeholder value 0xffff_ffff, see
# arch/arm/include/asm/barebox-arm-head.h for more details
#
set RDU3_TCM_MAIC_LOCATION [expr $IMX8MQ_TCM_BASE_ADDR + 0x28]
set RDU3_TCM_MAGIC_REQUEST 0xdeadbeef
set RDU3_TCM_MAGIC_REPLY 0xbaadf00d
echo "Bootstrap: Uploading DDR helper"
halt
load_image images/start_zii_imx8mq_dev.pblb \
$IMX8MQ_TCM_BASE_ADDR \
bin \
$IMX8MQ_TCM_BASE_ADDR \
$IMX8MQ_TCM_MAX_SIZE
echo "Bootstrap: Running DDR helper"
mww phys $RDU3_TCM_MAIC_LOCATION $RDU3_TCM_MAGIC_REQUEST
resume $IMX8MQ_TCM_BASE_ADDR
echo "Bootstrap: Waiting for DDR helper to finish"
if {[catch {wait_halt} errmsg] ||
[mrw $RDU3_TCM_MAIC_LOCATION] != $RDU3_TCM_MAGIC_REPLY} {
echo "Bootstrap: DDR initialization FAILED"
} else {
echo "Bootstrap: DDR is ready"
}
}
proc start_barebox {} {
#
# We have to place our image at MX8M_ATF_BL33_BASE_ADDR in order
# to be able to initialize ATF firmware since that's where it
# expects entry point to BL33 would be
#
set MX8M_ATF_BL33_BASE_ADDR 0x40200000
echo "Bootstrap: Loading Barebox"
load_image images/start_zii_imx8mq_dev.pblb $MX8M_ATF_BL33_BASE_ADDR bin
echo [format "Bootstrap: Jumping to 0x%08x" $MX8M_ATF_BL33_BASE_ADDR]
resume $MX8M_ATF_BL33_BASE_ADDR
}
proc board_init { } {
ddr_init
}
${_TARGETNAME}.0 configure -event reset-init { board_init }
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