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# SPDX-License-Identifier: GPL-2.0-only
soc imx6
loadaddr 0x20000000
ivtofs 0x400
#include <mach/imx6-ddr-regs.h>
#include <mach/imx6q-ddr-regs.h>
wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
wm 32 MX6_IOM_DRAM_SDQS1 0x00000030
wm 32 MX6_IOM_DRAM_SDQS2 0x00000030
wm 32 MX6_IOM_DRAM_SDQS3 0x00000030
wm 32 MX6_IOM_DRAM_SDQS4 0x00000030
wm 32 MX6_IOM_DRAM_SDQS5 0x00000030
wm 32 MX6_IOM_DRAM_SDQS6 0x00000030
wm 32 MX6_IOM_DRAM_SDQS7 0x00000030
wm 32 MX6_IOM_DRAM_DQM0 0x00020030
wm 32 MX6_IOM_DRAM_DQM1 0x00020030
wm 32 MX6_IOM_DRAM_DQM2 0x00020030
wm 32 MX6_IOM_DRAM_DQM3 0x00020030
wm 32 MX6_IOM_DRAM_DQM4 0x00020030
wm 32 MX6_IOM_DRAM_DQM5 0x00020030
wm 32 MX6_IOM_DRAM_DQM6 0x00020030
wm 32 MX6_IOM_DRAM_DQM7 0x00020030
wm 32 MX6_IOM_DRAM_CAS 0x00020030
wm 32 MX6_IOM_DRAM_RAS 0x00020030
wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030
wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030
wm 32 MX6_IOM_DRAM_RESET 0x00020030
wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000
wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000
wm 32 MX6_IOM_DRAM_SDBA2 0x00000000
wm 32 MX6_IOM_DRAM_SDODT0 0x00003030
wm 32 MX6_IOM_DRAM_SDODT1 0x00003030
wm 32 MX6_IOM_GRP_B0DS 0x00000030
wm 32 MX6_IOM_GRP_B1DS 0x00000030
wm 32 MX6_IOM_GRP_B2DS 0x00000030
wm 32 MX6_IOM_GRP_B3DS 0x00000030
wm 32 MX6_IOM_GRP_B4DS 0x00000030
wm 32 MX6_IOM_GRP_B5DS 0x00000030
wm 32 MX6_IOM_GRP_B6DS 0x00000030
wm 32 MX6_IOM_GRP_B7DS 0x00000030
wm 32 MX6_IOM_GRP_ADDDS 0x00000030
wm 32 MX6_IOM_DDRMODE_CTL 0x00020000
wm 32 MX6_IOM_GRP_DDRPKE 0x00000000
wm 32 MX6_IOM_GRP_DDRMODE 0x00020000
wm 32 MX6_IOM_GRP_CTLDS 0x00000030
wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000
wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333
wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333
wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333
wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333
wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333
wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333
wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333
wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333
wm 32 MX6_MMDC_P0_MDMISC 0x00081740
wm 32 MX6_MMDC_P0_MDSCR 0x00008000
wm 32 MX6_MMDC_P0_MDCFG0 0x555a7975
wm 32 MX6_MMDC_P0_MDCFG1 0xff538e64
wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db
wm 32 MX6_MMDC_P0_MDRWD 0x000026d2
wm 32 MX6_MMDC_P0_MDOR 0x005b0e21
wm 32 MX6_MMDC_P0_MDOTC 0x09444040
wm 32 MX6_MMDC_P0_MDPDC 0x00025576
wm 32 MX6_MMDC_P0_MDASP 0x00000027
wm 32 MX6_MMDC_P0_MDCTL 0x831a0000
wm 32 MX6_MMDC_P0_MDSCR 0x04088032
wm 32 MX6_MMDC_P0_MDSCR 0x0408803a
wm 32 MX6_MMDC_P0_MDSCR 0x00008033
wm 32 MX6_MMDC_P0_MDSCR 0x0000803b
wm 32 MX6_MMDC_P0_MDSCR 0x00428031
wm 32 MX6_MMDC_P0_MDSCR 0x00428039
wm 32 MX6_MMDC_P0_MDSCR 0x09408030
wm 32 MX6_MMDC_P0_MDSCR 0x09408038
wm 32 MX6_MMDC_P0_MDSCR 0x04008040
wm 32 MX6_MMDC_P0_MDSCR 0x04008048
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380003
wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1380003
wm 32 MX6_MMDC_P0_MDREF 0x00005800
wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022227
wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022227
wm 32 MX6_MMDC_P0_MPDGCTRL0 0x434b0350
wm 32 MX6_MMDC_P0_MPDGCTRL1 0x034c0359
wm 32 MX6_MMDC_P1_MPDGCTRL0 0x434b0350
wm 32 MX6_MMDC_P1_MPDGCTRL1 0x03650348
wm 32 MX6_MMDC_P0_MPRDDLCTL 0x4436383b
wm 32 MX6_MMDC_P1_MPRDDLCTL 0x39393341
wm 32 MX6_MMDC_P0_MPWRDLCTL 0x35373933
wm 32 MX6_MMDC_P1_MPWRDLCTL 0x48254A36
wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001f001f
wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001f001f
wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x00440044
wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x00440044
wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
wm 32 MX6_MMDC_P1_MPMUR0 0x00000800
wm 32 MX6_MMDC_P0_MDSCR 0x00000000
wm 32 MX6_MMDC_P0_MAPSR 0x00011006
wm 32 0x020c4068 0x00c03f3f
wm 32 0x020c406c 0x0030fc03
wm 32 0x020c4070 0x0fffc000
wm 32 0x020c4074 0x3ff00000
wm 32 0x020c4078 0x00fff300
wm 32 0x020c407c 0x0f0000c3
wm 32 0x020c4080 0x000003ff
/* enable AXI cache for VDOA/VPU/IPU */
wm 32 0x020e0010 0xf00000cf
/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7 */
wm 32 0x020e0018 0x007f007f
wm 32 0x020e001c 0x007f007f
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