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soc imx6
loadaddr 0x10000000
ivtofs 0x400
#include "ddr3-defines.imxcfg"
/* Debug */
wm 32 0x020e0228 0x00000005
/* wm 32 0x020e0244 0x00000005 */
wm 32 0x020e05f8 0x000130b0
/* wm 32 0x020e0614 0x000130b0 */
#include "padsetup-q.imxcfg"
/* Set Read data delay 3 delay units for all bits */
wm 32 0x021b081c 0x33333333
wm 32 0x021b0820 0x33333333
wm 32 0x021b0824 0x33333333
wm 32 0x021b0828 0x33333333
wm 32 0x021b481c 0x33333333
wm 32 0x021b4820 0x33333333
wm 32 0x021b4824 0x33333333
wm 32 0x021b4828 0x33333333
/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */
wm 32 0x021b0018 0x00011742
check 32 until_all_bits_clear 0x021b0018 0x00000002
/* CSCR: Configuration mode */
wm 32 0x021b001c 0x00008000
check 32 until_any_bit_set 0x021b001c 0x00004000
wm 32 0x021b000c MDCFG0_8G_533MHZ_CL7
wm 32 0x021b0010 MDCFG1_533MHZ
wm 32 0x021b0014 MDCFG2_533MHZ
/* MDRWD */
wm 32 0x021b002c 0x000026d2
wm 32 0x021b0030 MDOR_8G_533MHZ
wm 32 0x021b0008 MDOTC_533MHZ
wm 32 0x021b0004 MDPDC_533MHZ
wm 32 0x021b0040 MDASP_4GIB00
wm 32 0x021b0000 MDCTL_8G
// check 32 until_any_bit_set 0x021b0018 0x80000000
/* DDR3 MR config */
wm 32 0x021b001c DDR3_MR2_533MHZ_RTT_120
/*
* DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest).
*/
wm 32 0x021b001c 0x00008033
wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40
wm 32 0x021b001c DDR3_MR0_533MHZ_CL7
/*
* ZQ calibration, n = 0x10 (Precharge all):
* Bit 10 = 1: Start ZQ calibration
* REGISTER: 0x04008040
*/
wm 32 0x021b001c 0x04008040
/* MPZQHWCTRL */
wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */
wm 32 0x021b4800 0xa1390003
wm 32 0x021b0020 MDREF_64KHZ
wm 32 0x021b0818 MPODTCTRL_ODT_60
wm 32 0x021b4818 MPODTCTRL_ODT_60
/* DQS gating calibration measured on UT2 and UTC boards */
wm 32 0x021b083c 0x43000300
wm 32 0x021b483c 0x430a0310
wm 32 0x021b0840 0x030002b0
wm 32 0x021b4840 0x02b00255
/* MPRDDLCTL, MPWRDLCTL */
/* Measured on UT2 and UTC, good averages */
wm 32 0x021b0848 0x453a3a3a
wm 32 0x021b4848 0x403b3947
wm 32 0x021b0850 0x40444540
wm 32 0x021b4850 0x46404840
/* MPWLDECTRL0,1 */
/* Measured and averaged on UT2 and UTC boards */
wm 32 0x021b080c 0x00200020
wm 32 0x021b0810 0x0026001e
wm 32 0x021b480c 0x00100028
wm 32 0x021b4810 0x0012001b
/* MPMUR0 */
wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */
wm 32 0x021b48b8 0x00000800
/* MDSCR */
wm 32 0x021b001c 0x00000000 /* Disable configuration req */
/* MAPSR */
wm 32 0x021b0404 0x00001006 /* Enable autorefresh */
/* Clock configuration (CCM) */
/* CCGR0..6 */
wm 32 0x020c4068 0x00c03f3f
wm 32 0x020c406c 0x0030fc03
wm 32 0x020c4070 0x0fffc000
wm 32 0x020c4074 0x3ff00000
wm 32 0x020c4078 0x00fff300
wm 32 0x020c407c 0x0f0000c3
wm 32 0x020c4080 0x000003ff
/* enable AXI cache for VDOA/PCIe/VPU/IPU */
wm 32 0x020e0010 0xff0000cf
/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */
wm 32 0x020e0018 0x007f007f
wm 32 0x020e001c 0x007f007f
/* DEBUG leds */
wm 32 0x020e0244 0x00000005
wm 32 0x020e0614 0x000130b0
/* RGMII config */
wm 32 0x020e0790 0x00080000 /* 1V2 DDR IO */
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