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/*
* SPDX-License-Identifier: GPL-2.0-or-later
* SPDX-FileCopyrightText: 2014-2016 Freescale Semiconductor, Inc.
* SPDX-FileCopyrightText: 2016 Variscite Ltd.
* SPDX-FileCopyrightText: 2022 Gossen Metrawatt GmbH
* SPDX-FileCopyrightText: 2022 Roland Hieber, Pengutronix <rhi@pengutronix.de>
*/
soc imx7
loadaddr 0x80000000
ivtofs 0x400
#include <mach/imx/imx7-ddr-regs.h>
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* Change DDR freq. to 400Mhz */
wm 32 0x30360070 0x00703021
wm 32 0x30360090 0x00000000
wm 32 0x30360070 0x00603021
check 32 until_all_bits_set 0x30360070 0x80000000
wm 32 0x30389880 0x00000001
wm 32 0x30340004 0x4F400005 /* Enable OCRAM EPDC */
/* Clear then set bit30 to ensure exit from DDR retention */
wm 32 0x30360388 0x40000000
wm 32 0x30360384 0x40000000
wm 32 0x30391000 0x00000002 /* deassert presetn */
/* ddrc */
wm 32 0x307a0000 0x01040001 /* mstr */
wm 32 0x307a01a0 0x80400003 /* dfiupd0 */
wm 32 0x307a01a4 0x00100020 /* dfiupd1 */
wm 32 0x307a01a8 0x80100004 /* dfiupd2 */
wm 32 0x307a0064 0x00400046 /* rfshtmg */
wm 32 0x307a0490 0x00000001 /* pctrl_0 */
wm 32 0x307a00d0 0x00020083 /* init0 */
wm 32 0x307a00d4 0x00690000 /* init1 */
wm 32 0x307a00dc 0x09300004 /* init3 */
wm 32 0x307a00e0 0x04080000 /* init4 */
wm 32 0x307a00e4 0x00100004 /* init5 */
wm 32 0x307a00f4 0x0000033f /* rankctl */
wm 32 0x307a0100 0x09081109 /* dramtmg0 */
wm 32 0x307a0104 0x0007020d /* dramtmg1 */
wm 32 0x307a0108 0x03040407 /* dramtmg2 */
wm 32 0x307a010c 0x00002006 /* dramtmg3 */
wm 32 0x307a0110 0x04020205 /* dramtmg4 */
wm 32 0x307a0114 0x03030202 /* dramtmg5 */
wm 32 0x307a0120 0x00000803 /* dramtmg8 */
wm 32 0x307a0180 0x00800020 /* zqctl0 */
wm 32 0x307a0190 0x02098204 /* dfitmg0 */
wm 32 0x307a0194 0x00030303 /* dfitmg1 */
wm 32 0x307a0200 0x00000016 /* addrmap0 */
wm 32 0x307a0204 0x00080808 /* addrmap1 */
wm 32 0x307a0210 0x00000f0f /* addrmap4 */
wm 32 0x307a0214 0x07070707 /* addrmap5 */
wm 32 0x307a0218 0x0F070707 /* addrmap6 */
wm 32 0x307a0240 0x06000604 /* odtcfg */
wm 32 0x307a0244 0x00000001 /* odtmap */
wm 32 0x30391000 0x00000000 /* deassert presetn */
/* ddr_phy */
wm 32 0x30790000 0x17420f40 /* phy_con0 */
wm 32 0x30790004 0x10210100 /* phy_con1 */
wm 32 0x30790010 0x00060807 /* phy_con4 */
wm 32 0x307900b0 0x1010007e /* mdll_con0 */
wm 32 0x3079009c 0x00000d6e /* drvds_con0 */
wm 32 0x30790020 0x08080808 /* offset_rd_con0 */
wm 32 0x30790030 0x08080808 /* offset_wr_con0 */
wm 32 0x30790050 0x01000010 /* cmd_sdll_con0 (OFFSETD_CON0) */
wm 32 0x30790050 0x00000010 /* cmd_sdll_con0 (OFFSETD_CON0) */
wm 32 0x307900c0 0x0e407304 /* zq_con0 */
wm 32 0x307900c0 0x0e447304 /* zq_con0 */
wm 32 0x307900c0 0x0e447306 /* zq_con0 */
check 32 until_all_bits_set 0x307900c4 0x1
wm 32 0x307900c0 0x0e447304 /* zq_con0 */
wm 32 0x307900c0 0x0e407304 /* zq_con0 */
wm 32 0x30384130 0x00000000 /* Disable Clock */
wm 32 0x30340020 0x00000178 /* IOMUX_GRP_GRP8 - Start input to PHY */
wm 32 0x30384130 0x00000002 /* Enable Clock */
wm 32 0x30790018 0x0000000f /* ddr_phy lp_con0 */
check 32 until_all_bits_set 0x307a0004 0x1
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