path: root/arch/arm/dts/imx8mp-congatec-qmx8p.kernel.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// SPDX-FileCopyrightText: 2019 NXP
// SPDX-FileCopyrightText: 2022 congatec GmbH
// SPDX-FileCopyrightText: 2023 Pengutronix, Johannes Zink <j.zink@pengutronix.de>

#include <arm64/freescale/imx8mp.dtsi>
#include "imx8mp.dtsi"
#include <dt-bindings/usb/pd.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/net/ti-dp83867.h>

/ {
	model = "conga-QMX8-Plus";
	compatible = "congatec,qmx8p", "fsl,imx8mp";

	aliases {
		ethernet0 = &eqos;
		rtc0 = &rtc_ext;     /* external I2C RTC M4162 */
		rtc1 = &snvs_rtc;    /* internal in SoC */
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells= <0>;
		clock-frequency = <100000000>;
	};

	reg_usb1_host_vbus: regulator-usb1-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb1_vbus>;
		gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
		regulator-name = "usb1_host_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
	};

	reg_usb2_host_vbus: regulator-usb2-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb2_vbus>;
		gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
		regulator-name = "usb2_host_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
	};

	/* reset line for SD1 (Qseven SD Card) interface */
	reg_usdhc1_vmmc: regulator-usdhc1 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc1_vmmc>;
		gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
		regulator-name = "3v3-sd1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		enable-active-high;
		startup-delay-us = <100>;
		off-on-delay-us = <12000>;
	};

	/* reset line for SD2 (on-SoM µSD) interface */
	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		regulator-name = "3v3-sd2";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		enable-active-high;
		startup-delay-us = <100>;
		off-on-delay-us = <12000>;
	};

	/* reset line for SD3 (on-SoM eMMC) interface */
	reg_usdhc3_vmmc: regulator-usdhc3 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc3_vmmc>;
		gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
		regulator-name = "3v3-sd3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		enable-active-high;
		startup-delay-us = <100>;
		off-on-delay-us = <12000>;
	};

	reg_lfp_vdd: regulator-lfp-vdd {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_display_vdd_en>;
		gpio = <&gpio4 1 GPIO_ACTIVE_HIGH>; // LFP0_VDD_EN
		regulator-name = "Display_Panel_Vdd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_backlight_enable: regulator-backlight {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lvds0_backlight>;
		gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
		regulator-name = "backlight";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		enable-active-high;
	};

	lvds0_backlight: lvds0-backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm2 0 100000 0>;
		power-supply = <&reg_backlight_enable>;
		brightness-levels = <0 100>;
		num-interpolated-steps = <100>;
		default-brightness-level = <80>;
	};

	fan0: pwm-fan {
		compatible = "pwm-fan";
		pwms = <&pwm4 4 100000 0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_interrupt_fan_in>;
		#cooling-cells = <2>;
		interrupt-parent = <&gpio5>;
		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
		status = "disabled";
	};
};

&A53_0 {
	cpu-supply = <&buck2>;
};

&A53_1 {
	cpu-supply = <&buck2>;
};

&A53_2 {
	cpu-supply = <&buck2>;
};

&A53_3 {
	cpu-supply = <&buck2>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
};

&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	#address-cells = <1>;
	#size-cells = <0>;
};

&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs0>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
};

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_gbe0_rst>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		/* on-SoM PHY */
		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
			reset-assert-us = <1000>;
			reset-deassert-us = <1000>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
		};
	};
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	w25q64fw: flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <80000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	pca9450: pmic@25 {
		compatible = "nxp,pca9450c";
		reg = <0x25>;
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio4>; /* PMIC_nINT */
		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;

		regulators {
			buck1: BUCK1 {
				regulator-name = "BUCK1";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck2: BUCK2 {
				regulator-name = "BUCK2";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck3: BUCK3 {
				regulator-name = "BUCK3";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5: BUCK5 {
				regulator-name = "BUCK5";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6: BUCK6 {
				regulator-name = "BUCK6";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1: LDO1 {
				regulator-name = "LDO1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2: LDO2 {
				regulator-name = "LDO2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1150000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3: LDO3 {
				regulator-name = "LDO3";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4: LDO4 {
				regulator-name = "LDO4";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo5: LDO5 {
				regulator-name = "LDO5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};
};

&i2c2 {
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};

&i2c3 {
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};

/* i2c-5: RTC */
&i2c5 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c5>;
	pinctrl-1 = <&pinctrl_i2c5_gpio>;
	scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	rtc_ext: rtc@68 {
		compatible = "microcrystal,rv4162";
		reg = <0x68>;
	};
};

/* i2c-6: I2C splitter */
&i2c6 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c6>;
	pinctrl-1 = <&pinctrl_i2c6_gpio>;
	scl-gpios = <&gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	mux@70 {
		compatible = "nxp,pca9548";
		reg = <0x70>;
		#address-cells = <1>;
		#size-cells = <0>;

		/* MIPI-CSI 1 */
		imux0: i2c@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		/* MIPI-CSI 2 */
		imux1: i2c@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		/* Qseven LVDS_DID */
		imux2: i2c@2 {
			reg = <2>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		/* Qseven LVDS_BLC */
		imux3: i2c@3 {
			reg = <3>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		/* Ports 4 .. 7 not used */
	};
};

&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio4 12 GPIO_ACTIVE_LOW>;
	fsl,max-link-speed = <2>;
};

&pcie_phy {
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	clocks = <&pcie0_refclk>;
	clock-names= "ref";
};

&uart1 { /* UART0 connector on Qseven */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	uart-has-rtscts;
};

&uart2 {
	/* on-SoM UART connector */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usb3_phy0 { /* on-SoM hub */
	fsl,phy-tx-vref-tune = <8>;		// note: downstream
	fsl,phy-tx-preemp-amp-tune = <3>;	// note: downstream
	vbus-supply = <&reg_usb1_host_vbus>;
	status = "okay";
};

&usb3_0 {
	status = "okay";
};

&usb_dwc3_0 { /* Qseven USB_P1 */
	dr_mode = "otg";
	usb-role-switch;
	role-switch-default-mode = "host";

	connector {
		compatible = "gpio-usb-b-connector", "usb-b-connector";
		id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb_overcurrent>;
	};
};

&usb3_phy1 {
	vbus-supply = <&reg_usb2_host_vbus>;
	status = "okay";
};

&usb3_1 {
	status = "okay";
};

&usb_dwc3_1 { /* Qseven USB_P0 */
	dr_mode = "host";
	status = "okay";
};

/* Qseven SD Card interface */
&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
	cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
	vmmc-supply = <&reg_usdhc1_vmmc>;
	bus-width = <4>;
};

/* on-SoM µSD Card slot */
&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	bus-width = <4>;
	status = "okay";
};

/* on-SoM eMMC */
&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	vmmc-supply = <&reg_usdhc3_vmmc>;
	bus-width = <8>;
	non-removable;
	no-sd;
	no-sdio;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&gpio1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gbe0_phy_reg>;
};

&gpio4 {
	stby_en-hog {
		gpio-hog;
		gpios = <11 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "CB_STBY_EN";
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 =
		<&pinctrl_hog>,
		<&pinctrl_android_buttons>,
		<&pinctrl_pm>,
		<&pinctrl_q7_suspend>,
		<&pinctrl_q7_wdt>;

	pinctrl_hog: hog-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09		0x01c0 /* PM_WAKE#   (X19:32) */
			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x01c0 /* SMB_ALERT# (X19:20) */
			MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31		0x01c0 /* I2S_RST# */
		>;
	};

	pinctrl_display_vdd_en: lvds-vdd-enable-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01		0x0100 /* LFP_VDD_EN */
		>;
	};

	pinctrl_hdmi: hdmi-grp {
		fsl,pins = <
			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3
			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3
			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x40000019
			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x40000019
		>;
	};

	/* On module Android buttons (X7) */
	pinctrl_android_buttons: androidbutton-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07		0x01c0 /* X7-2: Btn Vol Up */
			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06		0x01c0 /* X7-3: Btn Home */
			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07		0x01c0 /* X7-4: Btn Search */
			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x01c0 /* X7-5: Btn Back */
			MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08		0x01c0 /* X7-6: Btn Menu */
			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x01c0 /* X7-7: Btn Vol Down */
		>;
	};

	/* Qseven PM signals */
	pinctrl_pm: pm-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x01c0 /* Q7-21: Sleep Btn */
			MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10		0x01c0 /* Q7-22: Lid Btn */
			MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06		0x01c0 /* Q7-27: Bat Low */
			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x01c0 /* Q7-69: Thrm */
			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20		0x01c0 /* Q7-71: Thrm Trip (X19:19) */
		>;
	};

	/* Qseven WDT */
	pinctrl_q7_wdt: q7-wdt-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04		0x01c0 /* Q7-70: WDT Trig */
			MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13		0x0100 /* Q7-72: WDT Out */
		>;
	};

	/* Qseven suspend signals */
	pinctrl_q7_suspend: q7-suspend-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11		0x0100 /* Q7-18: SUS_S3# (enable signal from PMIC) */
			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01		0x0100 /* Q7-19: SUS_STAT | GP_OUT0*/
		>;
	};

	/* USB overcurrent */
	pinctrl_usb_overcurrent: usb-overcurrent-grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC		0x01c0
			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29		0x01c0 /* USB1 OC as GPIO */
		>;
	};

	pinctrl_pwm1: pwm1-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT		0x116
		>;
	};

	pinctrl_pwm2: pwm2-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT		0x116
		>;
	};

	pinctrl_pwm4: pwm4-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT		0x116
		>;
	};

	pinctrl_ecspi1: ecspi1-grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x82
			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x82
			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x82
		>;
	};

	pinctrl_ecspi1_cs: ecspi1cs-grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x01c0
		>;
	};

	pinctrl_ecspi2: ecspi2-grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82
			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82
			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82
		>;
	};

	pinctrl_ecspi2_cs0: ecspi2cs0-grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x01c0
		>;
	};

	pinctrl_ecspi2_cs1: ecspi2cs1-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25		0x01c0
		>;
	};

	pinctrl_eqos: eqos-grp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3
			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3
			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91
			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91
			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91
			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91
			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91
			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f
			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f
			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f
			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f
			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f
			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f

			/* PTP capture INT */
			MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN			0x1c0
		>;
	};

	pinctrl_flexcan1: flexcan1-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX			0x150
			MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX			0x150
		>;
	};

	pinctrl_flexcan2: flexcan2-grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART3_TXD__CAN2_RX			0x150
			MX8MP_IOMUXC_UART3_RXD__CAN2_TX			0x150
		>;
	};

	pinctrl_flexspi0: flexspi0-grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c0
			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82
			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
		>;
	};

	pinctrl_i2c1: i2c1-grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c3
			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c3
		>;
	};

	pinctrl_i2c1_gpio: i2c1-gpio-grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001c3
			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2-grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x400001c3
			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3-grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x400001c3
			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x400001c3
		>;
	};

	pinctrl_i2c5: i2c5-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL			0x400001c3
			MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA			0x400001c3
		>;
	};

	pinctrl_i2c6: i2c6-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL		0x400001c3
			MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA			0x400001c3
		>;
	};

	pinctrl_i2c2_gpio: i2c2grp-gpio-grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x400001c3
			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x400001c3
		>;
	};

	pinctrl_i2c3_gpio: i2c3grp-gpio-grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x400001c3
			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x400001c3
		>;
	};

	pinctrl_i2c5_gpio: i2c5grp-gpio-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03		0x400001c3
			MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04		0x400001c3
		>;
	};

	pinctrl_i2c6_gpio: i2c6grp-gpio-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x400001c3
			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x400001c3
		>;
	};

	pinctrl_pcie: pcie-grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B		0x160  /* #OE of on-SoM PCIe CLK generator */
			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x41   /* WAKE */
			MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12		0x0100 /* reset */
		>;
	};

	pinctrl_pmic: pmicirq-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05		0x41
		>;
	};

	pinctrl_sai5: sai5-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK	0xd6
			MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK	0xd6
			MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC	0xd6
			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00	0xd6
			MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00	0xd6
		>;
	};

	pinctrl_uart1: uart1-grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX		0x49
			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX		0x49
			MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x49
			MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS		0x49
		>;
	};

	pinctrl_uart2: uart2-grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49
			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49
		>;
	};

	pinctrl_uart4: uart4-grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49
			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49
		>;
	};

	pinctrl_usb1: usb1-grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x140	/* USB1 ID */
		>;
	};

	/* Qseven SD Card interface */
	pinctrl_usdhc1: usdhc1-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0
			MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4
			MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6
			MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc1_gpio: usdhc1-gpio-grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x1c4 /* Q7-43: SD CD */
			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x1c4 /* Q7-46: SD WP */
		>;
	};

	pinctrl_usdhc1_vmmc: usdhc1-vmmc-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x41	/* reset */
		>;
	};

	/* on-SoM µSD Card slot */
	pinctrl_usdhc2: usdhc2-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 		0x1c4
		>;
	};

	pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x41
		>;
	};

	/* on-SoM eMMC */
	pinctrl_usdhc3: usdhc3-grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
		>;
	};

	pinctrl_usdhc3_vmmc: usdhc3-vmmc-grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16		0x41
		>;
	};

	pinctrl_wdog: wdog-grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6
		>;
	};

	pinctrl_gpt1_capture1: gpt1-capture1-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1		0x01C0
		>;
	};

	pinctrl_interrupt_fan_in: interrupt-fan-in-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00		0x01C0
		>;
	};

	pinctrl_usb1_vbus: usb1-vbus-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17		0x0100 /* USB1_PWR */
		>;
	};

	pinctrl_usb2_vbus: usb2-vbus-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16		0x0100 /* USB0S_PWR */
		>;
	};

	pinctrl_gbe0_phy_reg: gbe0-phy-reg-grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x01C0 /* GBE0_PWR_EN# */
		>;
	};

	pinctrl_gbe0_rst: gbe0-rst-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25		0x01C0 /* GBE0_RST# */
		>;
	};

	pinctrl_lvds0_backlight: lvds0-backlight-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x0100 /* BL_EN */
		>;
	};
};