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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* VFxxx shared DDR IOMUX DCD code. Intended use is to share code
* between all board that copy VF610 Tower Board DDR reference
* layout/design
*
* Copyright (C) 2018 Zodiac Inflight Innovations
*/
#define VF610_DDR_PAD_CTRL 0x00000180 /* 40 Ohm drive strength */
#define VF610_DDR_PAD_CTRL_1 0x00010180 /* ditto + differential input */
wm 32 VF610_PAD_DDR_A15__DDR_A_15 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A14__DDR_A_14 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A13__DDR_A_13 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A12__DDR_A_12 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A11__DDR_A_11 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A10__DDR_A_10 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A9__DDR_A_9 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A8__DDR_A_8 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A7__DDR_A_7 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A6__DDR_A_6 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A5__DDR_A_5 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A4__DDR_A_4 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A3__DDR_A_3 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A2__DDR_A_2 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A1__DDR_A_1 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_A0__DDR_A_0 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_BA2__DDR_BA_2 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_BA1__DDR_BA_1 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_BA0__DDR_BA_0 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_CAS__DDR_CAS_B VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_CKE__DDR_CKE_0 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_CLK__DDR_CLK_0 VF610_DDR_PAD_CTRL_1
wm 32 VF610_PAD_DDR_CS__DDR_CS_B_0 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D15__DDR_D_15 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D14__DDR_D_14 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D13__DDR_D_13 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D12__DDR_D_12 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D11__DDR_D_11 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D10__DDR_D_10 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D9__DDR_D_9 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D8__DDR_D_8 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D7__DDR_D_7 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D6__DDR_D_6 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D5__DDR_D_5 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D4__DDR_D_4 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D3__DDR_D_3 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D2__DDR_D_2 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D1__DDR_D_1 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_D0__DDR_D_0 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_DQM1__DDR_DQM_1 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_DQM0__DDR_DQM_0 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_DQS1__DDR_DQS_1 VF610_DDR_PAD_CTRL_1
wm 32 VF610_PAD_DDR_DQS0__DDR_DQS_0 VF610_DDR_PAD_CTRL_1
wm 32 VF610_PAD_DDR_RAS__DDR_RAS_B VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_WE__DDR_WE_B VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_ODT1__DDR_ODT_0 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_ODT0__DDR_ODT_1 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_RESETB VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 VF610_DDR_PAD_CTRL
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