blob: 9af0b7ef65e9f11b1a8ea0c4a4fcd33dc6482b9f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
// SPDX-License-Identifier: GPL-2.0-only
#include <mach/tzasc.h>
#include <linux/bitops.h>
#include <mach/imx8m-regs.h>
#include <io.h>
#define GPR_TZASC_EN BIT(0)
#define GPR_TZASC_SWAP_ID BIT(1)
#define GPR_TZASC_EN_LOCK BIT(16)
static void enable_tzc380(bool bypass_id_swap)
{
u32 __iomem *gpr = IOMEM(MX8M_IOMUXC_GPR_BASE_ADDR);
/* Enable TZASC and lock setting */
setbits_le32(&gpr[10], GPR_TZASC_EN);
setbits_le32(&gpr[10], GPR_TZASC_EN_LOCK);
if (bypass_id_swap)
setbits_le32(&gpr[10], BIT(1));
/*
* set Region 0 attribute to allow secure and non-secure
* read/write permission. Found some masters like usb dwc3
* controllers can't work with secure memory.
*/
writel(0xf0000000, MX8M_TZASC_BASE_ADDR + 0x108);
}
void imx8mq_tzc380_init(void)
{
enable_tzc380(false);
}
void imx8mn_tzc380_init(void) __alias(imx8mm_tzc380_init);
void imx8mp_tzc380_init(void) __alias(imx8mm_tzc380_init);
void imx8mm_tzc380_init(void)
{
enable_tzc380(true);
}
bool tzc380_is_enabled(void)
{
u32 __iomem *gpr = IOMEM(MX8M_IOMUXC_GPR_BASE_ADDR);
return (readl(&gpr[10]) & (GPR_TZASC_EN | GPR_TZASC_EN_LOCK))
== (GPR_TZASC_EN | GPR_TZASC_EN_LOCK);
}
|