1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
// SPDX-License-Identifier: GPL-2.0
#include <common.h>
#include <soc/fsl/immap_lsch2.h>
#include <asm-generic/sections.h>
#include <asm/cache.h>
#include <mach/layerscape/xload.h>
#include <mach/layerscape/layerscape.h>
/*
* The offset of the 2nd stage image in the output file. This must match with the
* offset the pblimage tool puts barebox to.
*/
#define BAREBOX_START (128 * 1024)
struct layerscape_base_addr {
void *qspi_reg_base;
void *membase;
void *qspi_mem_base;
};
static int layerscape_qspi_start_image(struct layerscape_base_addr *base,
unsigned long r0, unsigned long r1, unsigned long r2)
{
void (*barebox)(unsigned long, unsigned long, unsigned long) = base->membase;
/* Switch controller into little endian mode */
out_be32(base->qspi_reg_base, 0x000f400c);
memcpy(base->membase, base->qspi_mem_base + BAREBOX_START, barebox_image_size);
sync_caches_for_execution();
printf("Starting barebox\n");
barebox(r0, r1, r2);
printf("failed\n");
return -EIO;
}
int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
unsigned long r2)
{
struct layerscape_base_addr base;
base.qspi_reg_base = IOMEM(LSCH2_QSPI0_BASE_ADDR);
base.membase = IOMEM(LS1046A_DDR_SDRAM_BASE);
base.qspi_mem_base = IOMEM(0x40000000);
return layerscape_qspi_start_image(&base, r0, r1, r2);
}
int ls1021a_qspi_start_image(unsigned long r0, unsigned long r1,
unsigned long r2)
{
struct layerscape_base_addr base;
base.qspi_reg_base = IOMEM(LSCH2_QSPI0_BASE_ADDR);
base.membase = IOMEM(LS1021A_DDR_SDRAM_BASE);
base.qspi_mem_base = IOMEM(0x40000000);
return layerscape_qspi_start_image(&base, r0, r1, r2);
}
|
