blob: 37d267b4a976ebae209a7ebc4d3fed613ec177fc (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
|
// SPDX-License-Identifier: GPL-2.0-or-later
// SPDX-FileCopyrightText: 2011 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
/* i.MX23 USBPHY setup */
#include <common.h>
#include <io.h>
#include <mach/mxs/imx23-regs.h>
#include <mach/mxs/power.h>
#include <mach/mxs/usb.h>
#define USBPHY_PWD (IMX_USBPHY_BASE + 0x0)
#define USBPHY_CTRL (IMX_USBPHY_BASE + 0x30)
#define USBPHY_CTRL_SFTRST 0x80000000
#define USBPHY_CTRL_CLKGATE 0x40000000
#define CLK_PLLCTRL0 (IMX_CCM_BASE + 0x0)
#define PLLCTRL0_EN_USB_CLKS 0x00040000
#define DIGCTRL_CTRL (IMX_DIGCTL_BASE + 0x0)
#define DIGCTL_CTRL_USB_CLKGATE 0x00000004
#define SET 0x4
#define CLR 0x8
int imx23_usb_phy_enable(void)
{
imx_power_prepare_usbphy();
/* Reset USBPHY module */
writel(USBPHY_CTRL_SFTRST, USBPHY_CTRL + SET);
udelay(10);
/* Remove CLKGATE and SFTRST */
writel(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST, USBPHY_CTRL + CLR);
/* Turn on the USB clocks */
writel(PLLCTRL0_EN_USB_CLKS, CLK_PLLCTRL0 + SET);
writel(DIGCTL_CTRL_USB_CLKGATE, DIGCTRL_CTRL + CLR);
/* Power up the PHY */
writel(0, USBPHY_PWD);
/*
* Set precharge bit to cure overshoot problems at the
* start of packets
*/
writel(1, USBPHY_CTRL + SET);
return 0;
}
|
