blob: 90791ecf3e07d5c985209a8284e6e291dcc9f0e9 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* SPDX-FileCopyrightText: 2012 Marc Kleine-Budde <mkl@pengutronix.de> */
#ifndef __ASM_DMA_H
#define __ASM_DMA_H
#include <linux/string.h>
#include <linux/compiler.h>
#include <xfuncs.h>
#include <malloc.h>
/*
* x86 is cache coherent, so we need not do anything special here
*/
#define dma_alloc_coherent dma_alloc_coherent
static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
{
void *ret = xmemalign(4096, size);
if (dma_handle)
*dma_handle = (dma_addr_t)ret;
memset(ret, 0, size);
return ret;
}
#define dma_free_coherent dma_free_coherent
static inline void dma_free_coherent(void *mem, dma_addr_t dma_handle,
size_t size)
{
free(mem);
}
#define dma_sync_single_for_cpu dma_sync_single_for_cpu
static inline void dma_sync_single_for_cpu(dma_addr_t address, size_t size,
enum dma_data_direction dir)
{
}
#define dma_sync_single_for_device dma_sync_single_for_device
static inline void dma_sync_single_for_device(dma_addr_t address, size_t size,
enum dma_data_direction dir)
{
}
#endif /* __ASM_DMA_H */
|
